Abstract: Methods and apparatus to encode message input symbols in accordance with an accumulate-repeat-accumulate code with repetition three or four are disclosed. Block circulant matrices are used. A first method and apparatus make use of the block-circulant structure of the parity check matrix. A second method and apparatus use block-circulant generator matrices.
Type:
Grant
Filed:
June 24, 2005
Date of Patent:
March 3, 2009
Assignees:
California Institute of Technology, The Regents of the University of California
Inventors:
Dariush Divsalar, Aliazam Abbasfar, Christopher R. Jones, Samuel J. Dolinar, Jeremy C. Thorpe, Kenneth S. Andrews, Kung Yao
Abstract: A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal.
Type:
Grant
Filed:
January 30, 1997
Date of Patent:
July 4, 2000
Assignee:
Mitel Semiconductor Americas Inc.
Inventors:
Razmik Karabed, Nersi Nazari, Andrew Popplewell, Isaiah A. Carew
Abstract: A method for compression of digital data in a computer having a processor and a memory, wherein a group of consecutive bits having the same binary value is represented by a result number corresponding to the number of the consecutive bits. The method involves the following steps. A block of digital data to be compressed is provided. A bit detect selection parameter determines a bit value to be counted for counting consecutive bits. The processor is instructed to count from a first end of the block of digital data toward a second end of the block of digital data the number of consecutive bits having the bit value determined by the bit detect selection parameter. The number of bits so counted is stored, and the bit detect selection parameter is toggled. The processor is then instructed to count from the last bit counted toward the second end of the block of digital data the number of bits having the bit value determined by the current bit detect selection parameter.
Type:
Grant
Filed:
January 24, 1997
Date of Patent:
November 24, 1998
Assignee:
Texas Instruments Incorporated
Inventors:
Natarajan Seshan, Laurence R. Simar, Jr.