Abstract: A self-adaptable data compression technique includes compressing the digital data points of a waveform according to at least a first protocol and a second protocol, and various comparing the compressed data under various protocols to determine which would require the least memory for storage.

Abstract: A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.

Abstract: Methods of and apparatuses for optimizing quantization noise cancellation in multi-phase sampled MASH ADCs are disclosed. A test signal is combined with quantization noise produced by a delta-sigma modulator. Two parallel adaptive filters (i.e. even and odd filters) are configured to receive respective even and odd samples of a digital output signal of a MASH ADC analog modulator. Adaptive coefficients for the even adaptive filter are derived from correlation results between the even samples of the test signal and associated even samples of the final digital output signal. Similarly, adaptive coefficients for the odd adaptive filter are derived from correlation results between the odd samples of the test signal and associated odd samples of the final digital output signal. Using the adaptive coefficients, the even and odd adaptive filters are able to independently compensate for analog variations in the two paths.

Abstract: A system for two processors communicating though unidirectional links by embedding a strobe signal into the data by providing differential signals with different common mode signal levels.

Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.

Abstract: An offset-difference coding process for data encoding and decoding wherein for each of the paired input data, the encoding process first determines the greater of the two input data, then calculates the difference between the two input data, replaces the larger input data with the calculated difference, and encodes the calculated difference and the smaller input data. The offset-difference coding process also generates an indicator if the larger input data that is replaced by the calculated difference is not statistically larger than the smaller input data.

Abstract: A method for creating a frequency domain semblance for use in conjunction with acoustic logging tools is disclosed. Such a frequency domain semblance may be obtained by transforming an acoustic signal received at multiple depths into the frequency domain, combining the received waveforms corresponding to the different depth, and expressing the result in a graph with slowness and frequency axes. This graph shows the frequency-slowness location for the acoustic signal, as well as for other related signals that may inadvertently be generated by the acoustic logging tool. This information may then be used to more clearly measure the slowness of the received acoustic signal. Another aspect of the invention is the treatment of two or more time domain semblances as probability density functions of the slowness for an acoustic signal. This enables the combination of time domain semblances from the same depth in the wellbore.

Abstract: A method and apparatus for providing fast data recovery with adaptive pulse code modulation (ADPCM) coding wherein, an ADPCM encoder periodically records the compressional parameters in memory together with regular compressed codes, and an ADPCM decoder retrieves the previously saved compressional parameters when reading the regular data from memory. In case any error occurs in the data compression and decompression processes which would cause a data divergence in the output of the ADPCM decoder, the previously saved compressional parameters can be used to correct the output data, thus enabling fast data recovery in the data outputting process without affecting downstream data in the data stream.

Abstract: In a method of lossless processing of an integer value signal in a prediction filter which includes a quantiser, a numerator of the prediction filter is implemented prior to the quantiser and a denominator of the prediction filter is implemented recursively around the quantiser to reduce the peak data rate of an output signal. In the lossless processor, at each sample instant, an input to the quantiser is jointly responsive to a first sample value of a signal input to the prediction filter, a second sample value of a signal input to the prediction filter at a previous sample instant, and an output value of the quantiser at a previous sample incident. In a preferred embodiment, the prediction filter includes noise shaping for affecting the output of the quantiser.

Abstract: A computer implemented method and system for selecting a string for serving as a reference string for a comparison scheme for compressing a set of strings calculates preliminary compression results for every string relative to an initial reference string, and uses the preliminary compression results to find a better reference string without additional compression tests. According to one embodiment, a histogram is calculated showing the number of occurrences of each compressed length for each string in the set plotted against the initial reference string and the better reference string has a length corresponding to an average compression length or center of gravity of the histogram.

Abstract: An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a+a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b+b], wherein b<a. The adaptation stage produces the adaptive feedback signal such that the amplitude of the adaptive signal keeps the difference signal within the second range [−b+b].

Abstract: The present invention relates to a method and apparatus for providing fast data recovery with adaptive pulse code modulation (ADPCM) coding. In this coding technique, an ADPCM encoder periodically records the compressional parameters in memory together with regular compressed codes, and an ADPCM decoder retrieves the previously saved compressional parameters when reading the regular data from memory. In case any error occurs in the data compression and decompression processes which would cause a data divergence in the output of the ADPCM decoder, the previously saved compressional parameters can be used to correct the output data, thus enabling fast data recovery in the data outputting process without affecting downstream data in the data stream. To further enhance data safety, Gray Code is applied in the compression process before writing data to memory.

Abstract: A method of decompressing data words of an instruction set includes:

Abstract: A differential microphone (50) produces a differential pair of output signals which are applied by a differential analogue amplifier (52). The amplified differential signals are converted to 1-bit form by a pair of analogue to digital converters (54, 55) and are combined in a 1-bit Delta Sigma Modulator.

Abstract: The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantizers. The digital signals having a word length of m-bits are fed to a first control loop in the series. The quantization error signal of each quantizer is filtered and fed back to the corresponding digital control loop. It is then fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u-bits which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter.

Abstract: A delta sigma modulator which uses at least one quantizer having a dead zone. The dead zone quantizer outputs a zero when its input is within the dead zone range. It outputs a predetermined value if the input is above the dead zone range. If the input is below the dead zone range, the quantizer outputs another predetermined value. Ideally, the quantizer dead zone thresholds are complimentary in that the upper threshold for an input is the positive value of the lower threshold. Also, to save on accumulator bits, the delta sigma modulator selects a predetermined number of most significant bits at different stages.

Abstract: In methods for compressing data, when differences between two adjacent data among a series of N data , where N is a positive integer, are all less than a reference value, delta data values are generated on the basis of the differences. When the differences are the reference value or less and at least one delta data is stored, a command indicating that compression operations are performed on the basis of the differences, the number of the stored delta data, and the stored delta data are generated as compressed data. The compression method of the present method can obtain higher compression efficiency as compared with conventional RLC or modified-RLC compression methods.

Abstract: A data conversion device converts a series of digital signals into an analog signal. The device has a current selection circuit that can vary the direction and magnitude of the current it outputs and an integrating circuit that integrates the current supplied from the current selection circuit to output a voltage. The direction of the current is determined in accordance with the digital signals fed in. When the absolute value of the current is great, the value by which the absolute value of the current is increased is decreased, and the value by which the absolute value of the current is decreased is increased.

Abstract: An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a +a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b +b], wherein b<a. The adaptation stage produces the adaptive feedback signal such that the amplitude of the adaptive signal keeps the difference signal within the second range [−b +b].

Abstract: In a logic analyzer or similar binary signal-analyzing instrument, hardware circuitry, such as an ASIC, or other dedicated hardware, is used to perform waveform compression and summarization more rapidly than it could be done by software alone. The hardware is used to perform the compression of the data and to summarize its behavior for visual display. In one embodiment, the hardware starts from a given memory address and compares current timestamp values with final timestamp values to determine the length of the timeslice. Within the timeslice, all of the data is compared to determine whether it remains the same throughout the timeslice or whether it changes. The same approach can be used on violation data, such as glitches and setup and hold violations.

Abstract: In accordance with one aspect of the invention, a method operates to compare an input value of the input signal stream with an output value of an integration function of a previous binary value to generate a new binary value based upon the comparison. The method then stores a plurality of successive binary values from the comparing step, and simulates an integration function for a plurality of possible bit sequences of the plurality of successive binary values. Finally, the method determines which sequence results in the smallest error between the input signal stream and the output value of the integration function, and uses the most significant bit of the determined sequence to adjust the integration function. In accordance with another aspect of the invention, an encoder is provided for encoding an input signal stream.

Abstract: There are disclosed methods for quantizing image data with signal-dependent noise to a fewer number of values so that noise information is discarded while signal information is maintained. This is achieved by deriving a set of equations, the solution to which may be numerically computed and whose solution constitutes an optimal relative mean square error quantization for a signal with noise. Two low complexity explicit heuristic formulas for quantization are also provided.

Abstract: An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means 43 for determining the absolute value of the n-bit signal, means 46, 51 for producing a dynamics control signal dependent on the said absolute value, means 48 for applying the dynamics control signal to the 1-bit input signal, and means 49 for requantizing the dynamics controlled signal as a 1-bit signal and shaping the noise in the requantized 1-bit signal. Circuits for producing LOG base 2 and the corresponding anti-log are also disclosed.

Abstract: A system and method for encoding data is provided. A relational differentiation encoding module is used to encode a target value by constructing a set of values including the target, and then by differentiating the target from the constructed set of values. The constructed set of values may be defined by calculating the senior most bit (SMB) and the so many on/off bits (SMOB) of the target value. Armatures may be calculated to further differentiate the target value.

Abstract: A sample-and-hold circuit and an analog-to-digital conversion circuit are provided, and a latch circuit is provided downstream of the analog-to-digital conversion circuit. For example, a correlated double sampling (CDS) circuit is configured in which a first latch circuit is disposed downstream of the analog-to-digital conversion circuit and a second latch circuit is disposed downstream of the first latch circuit. Delayed output signals of the respective latch circuits are sent to a calculation section, which takes subtraction between those output signals. Resulting data is output via another latch circuit.

Abstract: An encoder/decoder architecture for buses, capable of minimizing power consumption by reducing the switching activity, generates, from an input information value relating to a given instant, a corresponding current output value on encoded bus lines relating to the same given instant. The architecture including storage device for storing respective preceding values of input information and output information relating to instants preceding the aforesaid given instant. A prediction block generates, from the preceding value of input information, an estimate of the current input information value. A decorrelation block decorrelates the current input information value with respect to the said estimate. A selection block selects as the current output value one out of the current input information value, the result of the decorrelation implemented by the decorrelation block or the preceding output value.

Abstract: A voice recording/reproducing device implemented by using an ADPCM (Adaptive Differential Pulse Code Modulation) method is provided which is capable of reproducing faithfully an original voice even at a time of performing a fast-forward reproduction by removing or culling a specified voice block from a continued series of voice blocks.

Abstract: A delta-sigma modulator comprises a 1-bit quantizer located for quantizing an analog signal applied thereto, and for outputting a first quantized digital signal, a 1-bit DA converter converting the first quantized digital signal into a quantized analog signal, a subtracting circuit for subtracting the quantized analog signal output from the 1-bit DA converter from the analog signal input to the 1-bit quantizer, and an input integrating circuit series including a series of one or more stages each of which includes a subtracter and an integrator for integrating an output of the subtracter, one subtracter at a first stage subtracting the quantized analog signal delayed by a delay element from an input analog signal input to the delta-sigma modulator, and one integrator at a final stage outputting its output to the 1-bit quantizer. A multiple-bit quantizer quantizes an analog output of the subtracting circuit and outputs a second quantized digital signal.

Abstract: A data processing apparatus includes an input terminal for receiving an audio signal, a 1-bit A/D converter for A/D converting the audio signal so as to obtain a bitstream signal, and a prediction unit for carrying out a prediction step on the bitstream signal so as to obtain a predicted bitstream signal. The data processing apparatus further includes a signal combination unit for combining the bitstream signal and the predicted bitstream signal so as to obtain a residue bitstream signal, and an output terminal for supplying the residual bitstream signal. A recording apparatus or a transmitter apparatus can use the data processing apparatus.

Abstract: An analog-to-digital or digital-to-analog system contains a converter (706). The converter is supplied with a clock signal (CLK1) at a frequency fs derived from a crystal of a frequency fs/N. The frequency fs is derived from the fs/N crystal frequency by using an edge-triggered clock multiplier 705 which multiplies the crystal frequency by the factor N. The result is a low-cost clock solution that incorporates clock jitter around a localized frequency of fs/N. Sigma delta processing circuitry (702) is then used to place a null (e.g., low gain area) in the quantization noise at the same frequency where clock jitter noise is high in order to cancel the adverse cumulative effects of these two types of noise.

Abstract: An analog signal, for example in a sound recording process, is converted into an input series of digital signals and is then encoded using a special differential encoding scheme. The scheme involves generating two series of signals, one series corresponding to some of the terms of the input signals, while other terms of the input series are excluded. For example the first series may include every second term of the input series. The second series includes terms corresponding to a difference between at least two terms of the input series, at least one of which is not included in the first series. Preferably the two terms of the input series defining a term of the second series are sequential or at most separated by one other term. The two series can be combined and can be either transmitted to a receiver or recorded on a medium. A high quality output is then obtained by reconstructing the input series from the two series.

Abstract: A technique for conserving digital memory space is disclosed. This technique includes sequentially transmitting a first address and a second address on a first bus coupled to a FIFO memory. The first address is stored in the memory and compared to the second address to determine a first value corresponding to a difference between the first and second addresses. This first value is written in the memory to represent the second address and has a bit size smaller than the second address. A method to decode the first value to regenerate the second address is also disclosed. These techniques may be further enhanced by only storing an address in a sequential access memory when it differs from the most recently stored address in the memory.

Abstract: In order to reduce memory bandwidth when predicting B-frames from stored anchor frames in an MPEG-2 video decoder, memory access requests (20) to external memory (14) storing anchor frames are selectively suppressed (18) so that only data is accessed which is required for the current data to be displayed. To still further reduce memory bandwidth, a prediction type (frame picture-frame prediction-half pel filtering) which requires a large number of memory requests is approximated to a type (field prediction) which requires half as many memory requests.

Abstract: A sensing system for detecting the position of a manually operated shift lever in an automatic transmission. The sensing system includes a plate member movable in response to movement of a shift lever. The plate member includes a generally flat contact surface having a predetermined pattern of electrically conductive and non-conductive areas. An electrical sensor unit is mounted in the transmission and positioned to communicate with the contact surface of the plate member. At least five electrical contact members engage the conductive and non-conductive areas on the contact surface generate binary codes having combinations that are indicative of the shift lever position in each of the predetermined operating modes. The engagement between the contact members and the contact surface further generates at least four unique binary codes indicative of the transitions between the predetermined operating modes.

Abstract: Known ADPCM transcoders use processors for coding and decoding, which are time and power consuming. Such a known ADPCM transcoder comprising one processor for coding and decoding can handle four channels, while according to DECT twelve channels need to be available, which requires three known ADPCM transcoders. By delaying signals in an ADPCM transcoder, it is no longer necessary to use processors, but, instead of said processors, logic elements can be used, which is very advantageous, because of such an ADPCM transcoder being able to handle sixteen channels.

Abstract: An adaptive linear predictor is used to predict samples, and residuals from such predictions are encoded using Golomb-Rice encoding. Linear prediction of samples of a signal which represents digitized sound tends to produce relatively low residuals and those residuals tend to be distributed exponentially. Accordingly, linear prediction combined with Golomb-Rice encoding produces particularly good compression rates with very efficient and simple implementation. A code length used in Golomb-Rice, which is typically referred to as the parameter k, is adapted for each sample in a predictable and repeatable manner to further reduce the size of a Golomb-Rice encoding for each sample. An infinite incident response filter of processed residuals automatically reduces influences of previously processed residuals upon such adaptation as additional samples are processed.

Abstract: An improved DC compensation method for use in conjunction with telephony signalling. The method includes defining a frame that includes at least two n-bit codewords. An unsigned codeword is then identified within the frame by applying a rule to the codewords in the defined frame. Next, a sign bit is appended to the unsigned codeword, thereby producing a DC compensating codeword. The sign bit is selected based upon a weighting function of the linear values associated with previously transmitted codewords. The remaining unsigned codewords in the frame are assigned sign bits from user data.

Abstract: In the data compression method and apparatus, difference value data each consisting of m bits that include an absolute value represented by m-1 bits and a 1-bit sign bit representing a sign are received, each of the difference value data having been obtained by calculating a difference between data to be coded and data immediately preceding it. N of the received difference value data are rearranged on a bit-by-bit basis, to generate a bit sequence in which bits at the same place of the n difference value data appear consecutively in predetermined order. A coded bit sequence is generated by compressing the generated bit sequence by a predetermined compression method. In the data expansion apparatus and method, a bit sequence of consecutive bits is generated by expanding a coded bit sequence by a decoding method corresponding to a predetermined compression method.

Abstract: In a transmission system for transmitting speech and music signals, an input signal is coded in a coder (11) by a time domain coder (4). The output signal of the time domain coder (4) is decoded by a time domain decoder (8) and the signal thus decoded is subtracted from the input signal by a subtracter circuit (10). To improve the coding quality, the difference signal is coded by a frequency domain coder (12) and the output signal of the time domain coder (4) and the frequency domain coder (12) are combined in a multiplexer (14) and transmitted to a receiver.

Abstract: A compressive encoding-decoding system is provided specifically for the realization of the lossless encoding system having a good efficiency. Herein, input signals are subjected to analog-to-digital conversion to generate a series of linear PCM data. Then, the system generates a series of difference value data, each representing a difference between adjacent samples of the linear PCM data, which are then combined with respect to each frame. Requantization is performed on the difference value data on the basis of a word length. In a first mode, the word length is determined to coincide with a minimum number of bits which are required to represent the difference value data having a maximum absolute value within the difference value data contained in each frame.

Abstract: A digital data slicer which can allow the digital sum value (DSV) of the sliced signal to approach zero is provided. The digital data slicer includes a comparator for comparing the input signal with an analog reference slice level to thereby generate the sliced signal. A DSV calculator is used to obtain the DSV of the sliced signal. A DSV processor is used to compare the DSV with a predefined tolerance window to thereby generate a digital correcting signal. A digital-to-analog (D/A) converter is then used to convert the digital correcting signal into an analog form which either raises or lowers the reference slice level to the comparator. This feedback control goes on until the DSV is within the range defined by the tolerance window.

Abstract: A method for testing protocol converters is presented, which permits the achievement of a test of all commands, independently of a corresponding test system. A modified protocol converter itself is used for the test. With the help of this method, a test for conversion of data structures can be carried out, of a slow protocol into the corresponding data structures of a fast protocol in the original speed.

Abstract: The present invention relates to data compression systems and methods wherein text can be compressed by encoding repetitions of blocks of characters, or through a straight encoding scheme that converts eight-bit character values to four-bit character values by eliminating values for characters that are not valid word-starting characters or valid next-letter characters for a given preceding letter. Block compression is accomplished through the use of data structures that track the successive occurrence of valid block-repetition starting characters, and their lengths. Repeat-relative block compression is accomplished by detecting character sequences that can be expressed as the value of a previously-occurring character sequence plus or minus an offset.

Abstract: In a computer implemented method for encoding digital values that are arranged in a successively increasing order, a delta value is determined for each pair of immediately successive values. The delta values are the differences between the pair of immediately successive values. For each delta value which can be encoded as a single byte, a logical zero is stored in the least significant bit of the single byte, and the delta value is stored in the most significant bits of the single byte. Otherwise, for each delta value which must be encoded as a plurality of bytes, a logical one is stored in the least significant bit of the first byte of the plurality of bytes, and a first portion of the delta value is stored in the most significant bits of the first byte. In this case, a logical zero is stored in the most significant bit of the next byte, and a next portion of the delta value is stored in the least significant bits of the next byte.

Abstract: A D/A converter has a plurality of input terminals, a plurality of current switchers, an adder for adding together the output currents from the plurality of current switchers, and a current-to-voltage converter. The D/A converter receives, via its input terminals, digital sound signals modulated by the adaptive delta modulation method or the delta modulation method. Each of the current switchers outputs a predetermined current, and switches the direction of the current in accordance with the digital signal it receives via the input terminal. The output currents of all of the current switchers are first added together by the adder, and then converted into a voltage by the current-to-voltage converter.

Abstract: Disclosed is a differential decoder circuit, which has: a pair of first and second transistors which form a differential connection, wherein a base of the first transistor is supplied with a reference bias voltage and a base of the second transistor is supplied with an input signal to be decoded to thereby output a decode output depending on the input signal from collector outputs of the first and second transistors; a constant-voltage source; a first bias means for supplying a bias voltage determined by a constant voltage of the constant-voltage source with the base of the first transistor; and a second bias means for supplying the alternative of a voltage determined by the input signal and the voltage determined by the constant voltage depending on a level of the input signal with the base of the second transistor.

Abstract: The apparatus and method describes herein shows a system of digitizing analog or digital electronic or optical signals with very high single bit serial digital data streams which digitizing is suitable to automatically adapt the transmission of multiple types of analog and digital signals. The system is especially well suited for allowing the coupling and transmission of signals.

Abstract: A method of transmitting and receiving a differential self-clocking data stream. The communications link comprises the coding of information signals onto two signal wires using two logic levels on each wire for a total of four possible coding symbols. The four symbols are utilized to encode data and control-states in both electrically differential and common mode manner upon the two signal wires. The coding sequence is chosen so as to facilitate the communications of binary data and control signals along with demarcation of each successive bit boundary by utilizing the consecutive symbol sequences which are nonrepetitive.

Abstract: An audio signal encoder is provided which is designed to A/D-convert an analog input signal at a first sampling frequency without being compressed and at a second sampling frequency that is two or four times higher than the first sampling frequency in data compression for minimizing data compression-caused errors in high-frequency components encoded. A decoder decoding digital signals produced by the encoder and a record carrier storing therein the digital signals are also provided.

Abstract: A data encoding and decoding device and method uses simple algorithms and keeps encoding error to a minimum. The data encoding device includes an original data splitting section for splitting data into "higher order data" and "lower order data," which represents the most significant portion of a digital data sample and the least significant portion of the digital data sample, respectively. Further, a differential calculation section calculates a difference between successive samples of the higher order data, and a number-of-items calculation section determines the number of data samples in the input data series. The lower order data and the differential data are then combined to obtain the encoded data.