Z Buffer (depth Buffer) Patents (Class 345/422)
  • Patent number: 7518615
    Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: April 14, 2009
    Assignee: Silicon Graphics, Inc.
    Inventors: John M. Airey, Mark S. Peercy, Robert A. Drebin, John Montrym, David L. Dignam, Christopher J. Migdal, Danny D. Loh
  • Patent number: 7518607
    Abstract: A hidden-line removal method is provided which is executed in an image processing apparatus. The method includes the steps of extracting portions of the polygons contained in each of the divided areas on a two-dimensional plane using the projected three-dimensional model and calculating memory consumption for each of the areas using the extracted polygons. The method includes the steps of determining the optimized division style based on the calculated memory consumption and executing the hidden-line removal based on the optimized division style.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: April 14, 2009
    Assignee: Fujitsu Limited
    Inventor: Masayuki Kidera
  • Patent number: 7518608
    Abstract: A method of rendering a first image having a plurality of particles. The method comprises: receiving a z-depth image that provides a z-value for each pixel in the first image; generating a single pixel particle of an opaque transparency for each pixel in the z-depth image positioned at the same x-y position as the each pixel in the z-depth image and at a z-position indicated by the z-value; sorting the plurality of particles with a plurality of the generated single pixel particles in the first image based on the z-position; and rendering the sorted plurality of particles and single pixel particles based on the sorted order.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: April 14, 2009
    Assignees: Sony Corporation, Sony Pictures Entertainment Inc.
    Inventors: Rob Bredow, Brian Hall
  • Publication number: 20090091569
    Abstract: An apparatus for rendering an image includes a command binning module. The command binning module generates binned image information by classifying command information into bins that each correspond to a display tile of an image to be rendered. The command binning module generates image depth information for each display tile based on the binned command information.
    Type: Application
    Filed: October 8, 2007
    Publication date: April 9, 2009
    Applicant: ATI Technologies Inc.
    Inventors: Petri O. Nordlund, Mika H. Tuomi
  • Publication number: 20090085914
    Abstract: Methods and apparatus relating to video analysis are described. In an embodiment, a method comprises determining desirable features of the video content values, determining undesirable features of the video content values, constructing a quality model using the desirable features and the undesirable features, and storing the quality model in a memory module. Other embodiments are also described.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventor: Jorge E. Caviedes
  • Patent number: 7508390
    Abstract: A method for rendering a shadow in a 3 D scene includes generating a penumbra map using a z-buffer and generating an occluder map using the z-buffer. The penumbra map and the occluder map are projected into a 3 D scene to render at least one shadow having a penumbra region and an umbra region.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: March 24, 2009
    Assignee: NVIDIA Corporation
    Inventor: Joseph E. Demers
  • Publication number: 20090066693
    Abstract: A computer implemented method of calculating and encoding depth data from captured image data is disclosed. In one operation, the computer implemented method captures two successive frames of image data through a single image capture device. In another operation, differences between a first frame of image data and a second frame of the image data are determined. In still another operation, a depth map is calculated when pixel data of the first frame of the image data is compared to pixel data of the second frame of the image data. In another operation, the depth map is encoded into a header of the first frame of image data.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 12, 2009
    Inventor: Roc Carson
  • Publication number: 20090058852
    Abstract: A plurality of rows of tiles is defined in a graphics display field comprising a plurality of rows of pixels, each tile including pixels from at least two rows of pixels. Occlusion flags for respective tiles of a row of tiles for a graphics primitive are set based on whether respective representative depth values for the tiles of the row of tiles meet an occlusion criterion. Pixels in rows of pixels corresponding to the row of tiles are processed for the graphics primitive in a row-by-row manner responsive to the occlusion flags. The processing may include processing rows of pixels in the row of tiles using a zig-zag traversal algorithm.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 5, 2009
    Inventors: Jacob Strom, Tomas Akenine-Moller
  • Patent number: 7492363
    Abstract: A telestrator system is disclosed that allows a broadcaster to annotate video during or after an event. For example, while televising a sporting event, an announcer (or other user) can use the present invention to draw over the video of the event to highlight one or more actions, features, etc. In one embodiment, when the announcer draws over the video, it appears that the announcer is drawing on the field or location of the event. Such an appearance can be performed by mapping the pixels location from the user's drawing to three dimensional locations at the event. Other embodiments include drawing on the video without obscuring persons and/or other specified objects, and/or smoothing the drawings in real time.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: February 17, 2009
    Assignee: Sportsvision, Inc.
    Inventors: Kevin R. Meier, Walter Hsiao, James R. Gloudemans, Marvin S. White, Richard H. Cavallaro, Stanley K. Honey
  • Publication number: 20090027389
    Abstract: An object is to provide a three-dimensional shape drawing device which is capable of drawing a three-dimensional shape at a high speed. A high order bit comparing section compares high order bits of a depth value retained by a high order Z-buffer memory with high order bits of a depth value calculated by a depth value calculation section. If these two sets of high order bits are same, a low order bit comparing section compares low order bits of the depth value retained by a low order Z-buffer memory with low order bits of the depth value calculated by the depth value calculation section. If a depth indicated by the high order bits of the depth value calculated by the depth value calculation section is shallow, the high order bits of the depth value retained by the high order Z-buffer memory and the low order bits of the depth value retained by the low order Z-buffer memory are updated.
    Type: Application
    Filed: June 8, 2005
    Publication date: January 29, 2009
    Inventor: Yorihiko Wakayama
  • Patent number: 7474313
    Abstract: A graphics system coalesces Z data and color data for a raster operations stage. The Z data and color data are stored in a memory aligned tile format. In one embodiment, rendering modes in which the tile does not have a data capacity corresponding to Z data or color data for a whole number of pixels have data for at least one pixel split across entries to improve packing efficiency. Rendering modes having a number of bits for Z data or color data that does not equal a power of two such as 24 bits, 48 bits, and 96 bits, may be implemented with a high packing efficiency in tile formats having a data capacity corresponding to a power of 2 bits.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: January 6, 2009
    Assignee: Nvidia Corporation
    Inventors: Donald A. Bittel, Dorcas T. Hsia, David Kirk McAllister, Jonah M. Alben
  • Publication number: 20090002368
    Abstract: A device for generating a 3D image based on 2D graphical content of an image and depth information (i.e., Z-map) to be displayed on a display includes an application processor, a graphical processing unit (GPU), a 3D rendering unit and a display. The application processor is capable of sending 2D graphical content to the GPU, which is stored in memory. The GPU also includes a depth table having predefined depth information corresponding to the 2D graphical content. The GPU includes a depth module which monitors or identifies the 2D graphical content and requests a graphics library to paint a corresponding area in the Z-map that has the same size and position in the Z-map as that of the 2D graphical content. The GPU sends the 2D graphical content and the painted Z-map to a 3D rendering unit which creates a 3D image to be shown on a display.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Timo Vitikainen, Marko Suoknuuti, Jussi Ruutu, Ossi Korhonen
  • Publication number: 20080309666
    Abstract: A stereo graphics system based on depth-based image rendering is disclosed. A master pipeline renders a first image from graphics data and derives a depth image relating to the first image. A rendering unit accesses the first image and the depth image from the master pipeline and renders a second image based on the first image and the depth image. First and second frame buffers retrieves and stores the first and second images, and a compositor accesses the first and second images from the frame buffers and combines the images to generate a resulting image.
    Type: Application
    Filed: June 18, 2007
    Publication date: December 18, 2008
    Applicant: MEDIATEK INC.
    Inventors: Wan-Yu Chen, Chih-Hui Kuo
  • Publication number: 20080297506
    Abstract: An image is generated that includes ray traced pixel data and rasterized pixel data. A synergistic processing unit (SPU) uses a rendering algorithm to generate ray traced data for objects that require high-quality image rendering. The ray traced data is fragmented, whereby each fragment includes a ray traced pixel depth value and a ray traced pixel color value. A rasterizer compares ray traced pixel depth values to corresponding rasterized pixel depth values, and overwrites ray traced pixel data with rasterized pixel data when the corresponding rasterized fragment is “closer” to a viewing point, which results in composite data. A display subsystem uses the resultant composite data to generate an image on a user's display.
    Type: Application
    Filed: July 1, 2008
    Publication date: December 4, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gordon Clyde Fossum, Barry L. Minor, VanDung Dang To
  • Publication number: 20080297505
    Abstract: A computer implemented method of providing a photo-realistic view on demand of a real-time interactive three dimensional simulation, the method comprising: providing a real-time interactive three dimensional simulation; selecting a camera position; and ray tracing the provided real-time interactive three dimensional simulation as a function of the selected camera position, the ray tracing providing the photo-realistic view.
    Type: Application
    Filed: May 26, 2008
    Publication date: December 4, 2008
    Applicant: RDV SYSTEMS, LTD.
    Inventors: Nathan ELSBERG, Alex HAZANOV
  • Patent number: 7460117
    Abstract: Subsets of volume data are sequentially stored for volume rendering from two dimensional textures. For example, pairs of adjacent two-dimensional images are loaded into RAM or cache. One or more strips of texture data are interpolated for polygons extending between the two-dimensional images. The strips or polygons are more orthogonal to a viewing direction than the two-dimensional images. After interpolating texture data from the two-dimensional images for a plurality of non-coplanar polygons, the texture data is rendered. The rendered information represents one portion of the three dimensional representation. Other portions are rendered by repeating the process for other pairs or subset groups of adjacent two-dimensional images. A lower cost apparatus, such as a programmed computer or a GPU with a limited amount of memory, is able to render images for three dimensional representations of very large three-dimensional arrays. The images may be rendered without copying volume data for different main axes.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: December 2, 2008
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Klaus D. Engel, Gianluca Paladini
  • Publication number: 20080284780
    Abstract: An alpha-to-coverage transformation is performed by a pixel shader. The pixel shader compares data of a transparency column of a pixel and thresholds of sub-pixels of the pixel to generate a plurality of coverage masks, and stores the plurality of coverage masks in the LSBs of the transparency column of the pixel, and finally update the data of the sub-pixels according to the coverage masks stored in the transparency column of the pixel. A new instruction “a2c” is invented to speed up such thresholds comparison and coverage mask generation.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Inventor: R-Ming Hsu
  • Patent number: 7453458
    Abstract: A method is provided for multi-pass semitransparent processing having three passes. The method provides for displaying image data about a plurality of objects including opaque objects and semitransparent objects on a computer display screen by using an updatable Z-buffer as a storage, utilizing information about a depth direction for each object. A hardware resource capable of implementing the multi-pass method is also disclosed. The hardware resource, for example, is implemented as a drawing apparatus which can display image data about a plurality of objects including opaque objects and semitransparent objects on a computer display screen, utilizing information about a depth direction for each object.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Haruo Komooka, Kazuhiko Hasegawa
  • Patent number: 7450118
    Abstract: Three-dimensional models with three-dimensional coordinates for a certain area to be displayed on the screen based on coordinates of a reference position are received. The received three-dimensional models are classified according to the positions of nodes of polygons for the three-dimensional models. As for the three-dimensional models of which the nodes of the polygons exist on the same plane, they are displayed on the screen through automatic triangulation using a general three-dimensional graphic library. As for the three-dimensional models of which the nodes of the polygons do not exist on the same plane, they are displayed on the screen by converting the three-dimensional coordinates of the nodes of the polygons into three-dimensional coordinates based on a view point, converting the converted three-dimensional coordinates into two-dimensional coordinates through projection conversion onto a projection plane, and converting the two-dimensional coordinates into screen coordinates.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: November 11, 2008
    Assignee: LG Electronics Inc.
    Inventor: Hang Shin Cho
  • Patent number: 7450132
    Abstract: A method and/or apparatus for high speed visualization of depth image-based 3D graphic data. The method includes: reading point texture data of a 3D object; performing a 3D warping for each of the reference images of the simple texture data at a predetermined view point to obtain warped images; performing a depth test and a splatting for each pixel of the plurality of warped images to obtain final color data; and visualizing an object by using the final color data. Accordingly, it is possible to reduce memory usage and increase the number of visualization per a second and to effectively implement visualization of 3D graphic object in, particularly, a mobile terminal.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: November 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Inkyu Park, Gyeongia Jang, Jooyeon Han, Seokyoon Jung, Keunho Kim
  • Patent number: 7450121
    Abstract: A method is described of compositing a plurality of graphical objects to create an image comprising a plurality of parts, where the parts may be a run of pixels along a scanline or a region of the image. For each part of the image to be composited, the method identifies a set of the graphical objects that contribute to the part, and determines one or more required bit depths for compositing the set. The set is composited within the part at the one or more required bit depths. Thus selected parts of the image may be generated using a higher compositing bit depth.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: November 11, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: David Karlov, Paul Frederick Birchall
  • Patent number: 7450120
    Abstract: A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: November 11, 2008
    Assignee: Nvidia Corporation
    Inventors: Ziyad S. Hakura, Michael Brian Cox, Brian K. Langendorf, Brad W. Simeral
  • Publication number: 20080273033
    Abstract: Described are a video graphics system, graphics processor, and methods for rendering three-dimensional objects. A buffer is partitioned into tiles of pixels. Each pixel of each tile includes at least one sample. A primitive is received and determined to fully cover one of the tiles of the buffer. A section of the primitive that maps to the fully covered tile is tested to determine whether that section of the primitive may be drawn in its entirety. A value is stored in the buffer for the fully covered tile in response to determining that the section of the primitive may be drawn in its entirety. The value indicating that every sample of the fully covered tile has a depth value determined by the primitive.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 6, 2008
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Christopher Brennan
  • Patent number: 7439973
    Abstract: An image that includes ray traced pixel data and rasterized pixel data is generated. A synergistic processing unit (SPU) uses a rendering algorithm to generate ray traced data for objects that require high-quality image rendering. The ray traced data is fragmented, whereby each fragment includes a ray traced pixel depth value and a ray traced pixel color value. A rasterizer compares ray traced pixel depth values to corresponding rasterized pixel depth values, and overwrites ray traced pixel data with rasterized pixel data when the corresponding rasterized fragment is “closer” to a viewing point, which results in composite data. A display subsystem uses the resultant composite data to generate an image on a user's display.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: October 21, 2008
    Assignee: International Business Machines Corporation
    Inventors: Gordon Clyde Fossum, Barry L Minor, VanDung Dang To
  • Patent number: 7439983
    Abstract: A pixel shader is operated to perform a first texture lookup in an index buffer to obtain a vertex index value for a geometric primitive to be displayed. The pixel shader is also operated to perform a second texture lookup in a vertex buffer to obtain vertex data, wherein the vertex data corresponds to the previously obtained vertex index value for the geometric primitive to be displayed. The first and second texture lookups are repeated by the pixel shader such that vertex data is obtained for each vertex required to define the geometric primitive to be displayed. The pixel shader is then operated to rasterize the geometric primitive to be displayed, wherein the rasterizing is performed using the vertex data previously obtained by the pixel shader.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: October 21, 2008
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Remi Arnaud, Roy Hashimoto
  • Patent number: 7439974
    Abstract: A method of volume rendering two digital images includes providing a volume-rendering computing sub-system, loading a first image volume into a memory of the volume-rendering sub-system, rendering the first image volume, wherein a 2-dimensional image is output into an image buffer and a set of depth values are output into a depth buffer, loading a second image volume into a memory of the volume-rendering sub-system, rendering the second image volume up to the depth values output from the first image volume, wherein values from the rendering of the second image volume are merged with non-zero values of the image buffer, and rendering the remainder of the second image volume to include second image volume points beyond the depth values output from the rendering of the first image volume, wherein values from the rendering of the remainder of the second image volume are merged with non-zero values of the image buffer.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: October 21, 2008
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Abdelaziz Chihoub, Yuanhsi (Tony) Chen, Mariappan S. Nadar
  • Patent number: 7436414
    Abstract: The invention describes a method and system for use in occlusion culling of polygons in an interactive environment, such as a game. The invention employs a boundary box to simplify the testing of occludee polygons. Occluders and occludees are also transformed into non-interpenetrating, non-overlapping polygons. Winged-edges are employed to minimize a per occludee computational cost due to precision problems that may arise at non-overlapping edges. The invention then proceeds through an active edge list to identify edge discontinuities (e.g., where an edge is added or removed from the active edge list). Depth analysis is employed to determine whether an occluder occludes an occludee at the edge discontinuity. Moreover, the invention only performs depth analysis for those locations of a screen display where an occludee is determined to reside, thereby minimizing unnecessary computations.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: October 14, 2008
    Assignee: Valve Corporation
    Inventor: Brian Jacobson
  • Publication number: 20080247669
    Abstract: A high-resolution remote sensing image is processed through a true ortho-rectification. A totally new idea of H-buffer is provided to store heights of objects on the ground. The ortho-rectification includes a hidden analysis, a hidden detection and a hidden compensation. The process uses polygon patch of a building or a roadway as process unit. In the end, seam lines after hidden compensation are smoothed.
    Type: Application
    Filed: August 15, 2007
    Publication date: October 9, 2008
    Applicant: National Central University
    Inventors: Liang-Chien Chen, Shin-Hui Li, Jer-Jiunn Chen, Jiann-Yeou Rau
  • Publication number: 20080246764
    Abstract: Early Z scoreboard tracking systems and methods in accordance with the present invention are described. Multiple pixels are received and a pixel depth raster operation is performed on the pixels. The pixel depth raster operation comprises discarding a pixel that is occluded. In one exemplary implementation, the depth raster operation is done at a faster rate than a color raster operation. Pixels that pass the depth raster operation are checked for screen coincidence. Pixels with screen coincidence are stalled and pixels without screen coincidence are forwarded to lower stages of the pipeline. The lower stages of the pipeline are programmable and pixel flight time can vary (e.g., can include multiple passes through the lower stages). Execution through the lower stages is directed by a program sequencer which also directs notification to the pixel flight tracking when a pixel is done processing.
    Type: Application
    Filed: December 17, 2007
    Publication date: October 9, 2008
    Inventors: Brian Cabral, Edward A. Hutchins, Christopher Donham
  • Publication number: 20080225049
    Abstract: Based on a driver programmable stencil reference value command, stencil reference value logic produces a plurality of stencil reference values for a corresponding plurality of pixels or pixel samples. At least one of the plurality of stencil reference values has a different value than at least one other of the plurality of stencil reference values. The driver programmable stencil reference value command may include a reference to instruction data or instruction data itself such that the graphics processing logic produces the plurality of stencil reference values based on the instruction data. Stencil logic performs a stencil test on the produced plurality of stencil reference values with respect to or without reference to a previously produced plurality of stencil values. Stencil logic performs stencil operations based on the result of the stencil test.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 18, 2008
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mark Fowler, Christopher J. Brennan
  • Patent number: 7425967
    Abstract: The present invention relates to a device and method for processing pixel rasterization in 3-Dimensional graphic engine. According to an embodiment of the present invention, a method of processing pixel rasterizaton in 3-Dimensional graphic engine comprises the steps of: receiving a plurality of fragment informations; verifying whether the coordinate of the fragment informations are adjacent to X axis or not; detecting depth values of old fragment; comparing the depth values of the old fragment; storing depth values of the newly inputted fragment after comparison; and storing color values, which are performed alpha blending, in a color cache. The apparatus for pixel rasterization processing in 3-Dimensional graphic engine includes a depth readout unit, a depth test unit, a depth entry unit, a color readout unit, an alpha blending unit, a color entry unit, a depth cache, a color cache and a frame memory.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: September 16, 2008
    Assignee: Core Logic Inc.
    Inventor: Jong Chul Jeong
  • Patent number: 7423642
    Abstract: A method for capturing images includes associating the pixels with tiles. An input data sequence representing respective current values of the pixels of a currently-captured image frame is accepted. Within each of at least some of the tiles, the current values are compared with respective reference values of the pixels of a reference frame stored in a frame buffer in order to detect variations between the current and reference values. When a variation is detected at a given pixel, the current value is written into the frame buffer in place of a corresponding reference value, and the tile is marked as a changed tile. Subsequent pixel values belonging to the changed tile are written into the frame buffer without comparing the current values of the subsequent pixels to the respective reference values, thereby replacing the reference frame with the currently-captured image frame.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: September 9, 2008
    Assignee: Winbond Electronics Corporation
    Inventors: Joram Peer, Yoel Hayon
  • Publication number: 20080211810
    Abstract: A method for rendering a three dimensional scene on a displaying screen comprises: generating for a tile of a current scene a hierarchical z-buffer which comprises a plurality of levels organized according to depth values; calculating a minimum depth value d of a submitted primitive; calculating an intersection area associated with said primitive with respect to said tile; providing a multiplicity of aligned regions each associated with a level of the hierarchical z-buffer so that the exact area calculated is suitable to be covered, at least entirely, by the union of such aligned regions; comparing the minimum depth value d of the submitted primitive with corresponding maximum depth values v1, v2, . . . , vN each read from the levels of the hierarchical z-buffer; discarding said primitive whether the minimum depth value d is bigger than all maximum depth values v1, v2, . . . , vN.
    Type: Application
    Filed: January 11, 2008
    Publication date: September 4, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventor: Mirko Falchetto
  • Publication number: 20080211811
    Abstract: A drawing apparatus which can display image data about a plurality of objects including opaque objects and semitransparent objects, each having information about a depth direction, on a computer display screen.
    Type: Application
    Filed: April 30, 2008
    Publication date: September 4, 2008
    Inventors: Haruo Komooka, Kazuhiko Hasegawa
  • Patent number: 7420568
    Abstract: A tiled graphics memory permits graphics data to be stored in different tile formats. One application is selecting a tile format optimized for the data generated for particular graphical surfaces in different rendering modes. Consequently, the tile format can be selected to optimize memory access efficiency and/or packing efficiency. In one embodiment a first tile format stores pixel data in a format storing two different types of pixel data whereas a second tile format stores one type of pixel data. In one implementation, a z-only tile format is provided to store only z data but no stencil data. At least one other tile format is provided to store both z data and stencil data. In one implementation, z data and stencil data are stored in different portions of a tile to facilitate separate memory accesses of z and stencil data.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: September 2, 2008
    Assignee: Nvidia Corporation
    Inventors: Donald A. Bittel, David Kirk McAllister, Steven E. Molnar
  • Patent number: 7414624
    Abstract: A method and apparatus for a frustum culling algorithm suitable for hardware implementation. In one embodiment, the method includes the separation of coordinates of a normal vector of each frustum plane of a frustum view into positive normal coordinates and negative normal coordinates. In one embodiment, the separation of the coordinates of each normal vector of the frustum planes enables implicit selection of the coordinates of a negative vertex (N-vertex) of an axis-aligned bounded box (AABB). Once implicitly selected, it is determined whether the N-vertex of the AABB is outside at least one frustum plane. In one embodiment, a determination that the N-vertex of the AABB is outside at least one of the frustum planes provides a trivial reject of objects enclosed by the AABB that are therefore is excluded from the rendering process. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventor: Alexander V. Reshetov
  • Patent number: 7408549
    Abstract: A graphics system including a frame buffer and a processing unit. The frame buffer contains N slots per pixel. Slots are used to store fragments. Suppose the N slots for a given pixel are occupied. In response to having received (or generated) a new fragment for the pixel, the processing unit may (a) blend the two backmost slots to liberate space for the new fragment, (b) blend the new fragment with the backmost slot in a first order, or, (c) blend the new fragment and the backmost slot in a second order. The choice of (a), (b) or (c) depends on the relationship of the new fragment's z value to the z values of the two backmost slots. The processing unit may be programmably configured to perform multi-pass order independent transparency in either front-to-back order or back-to-front order.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: August 5, 2008
    Assignee: Sun Microsystems,, Inc.
    Inventors: Justin M. Mahan, Michael A. Wasserman, Kevin C. Rushforth
  • Patent number: 7400325
    Abstract: The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within of a numerical range limit. This limit reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit culls many primitives despite its limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with previously computed culling information. This increases the VPC unit throughput by reducing the number of memory accesses and culling operations to be performed. The setup unit performs culling operations on any general primitive that cannot be culled by the VPC unit. By performing a first series of culling operations in the VPC unit, the processing burden on the setup unit is decreased.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: July 15, 2008
    Assignee: NVIDIA Corporation
    Inventors: Robert W. Gimby, Henry Packard Moreton, Thomas M. Ogletree, David C. Tannenbaum, Andrew D. Bowen, Christopher J. Goodman, Vimal Parikh, Craig M. Wittenbrink
  • Patent number: 7397478
    Abstract: A method, apparatus, and system are described in which a signal is generated to inhibit the execution of flip commands that cause a flip between buffers of a frame buffer. One or more of the flip commands and their associated instruction pointers may be preloaded into a frame buffer flip queue prior to removing the signal inhibiting the execution of the flip commands.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: July 8, 2008
    Assignee: Intel Corporation
    Inventor: Hong Jiang
  • Publication number: 20080143716
    Abstract: The invention discloses a method for the transforming of a 2D image into a 3D image. The method comprises the steps of: (a) selecting an object of 2D image; (b) setting a base line in the 2D image; (c) base on the base line, judging whether the object is located on the foreground or background of the 2D image; (d) offering a displacement to the object; (e) moving the object with the displacement to generate a plurality of continuous images; and (f) sequentially outputting each of the continuous images to generate the 3D image. Accordingly, after the user selects an object of 2D image, the method of the invention will automatically transform the 2D image into the 3D image.
    Type: Application
    Filed: July 24, 2007
    Publication date: June 19, 2008
    Inventors: Tung-Lin Hsieh, Wan-Ching Lee, I-Ming Huang
  • Publication number: 20080143715
    Abstract: The present invention relates to computer production of images. Three-dimensional graphics data (D3D) is automatically rendered by means of a GPU (330), which is adapted to receive two-dimensional image data. This data contains a number of image points, which each is associated with color information (r, g, b), transparency information (a), and depth buffer data (Z) that for each of the image points specifies a distance between a projection plane and a point of a reproduced object in the scene. A buffer unit (320) storing the image data is directly accessible by the GPU (330). The GPU (330), in turn, includes a texture module (331), a vertex module (332) and a fragment module (333). The texture module (331) receives the color information (r, g, b) and based thereon generates texture data (T) for at least one synthetic object in the synthetic three-dimensional model (V).
    Type: Application
    Filed: June 8, 2005
    Publication date: June 19, 2008
    Applicant: SAAB AB
    Inventors: Anders Moden, Lisa Johansson
  • Patent number: 7388583
    Abstract: A method of scaling a three-dimensional input model (200-208) into a scaled three-dimensional output model (210-224) is disclosed. The method comprises determining for portions of the three-dimensional input model respective probabilities that the corresponding portions of the scaled three-dimensional output model are visible in a two-dimensional view of the scaled three-dimensional output model and geometrically transforming portions of the three-dimensional input model into the respective portions of the scaled three-dimensional output model on basis of the respective probabilities. The determining of probability of visibility is based on a projection of the three-dimensional input model in a viewing direction. By taking into account that some portions are not visible, no depth-range is wasted.
    Type: Grant
    Filed: July 5, 2004
    Date of Patent: June 17, 2008
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Peter-André Redert
  • Patent number: 7388582
    Abstract: A method is disclosed for culling an object database in a graphics processing system. In one embodiment, the method comprises encoding per-object parameters and culling parameters. The per-object parameters are encoded in texture format thereby creating at least one per-object texture containing the encoded per-object parameters. Next, a fragment program used in a fragment processor of the GPU is optionally updated. The updated fragment program embodies a culling operation. A polygon is then rendered, wherein the rendering step includes per-fragment operations. During the per-fragment operations, the updated fragment program is executed. The culling operation embodied therein (i) accesses the culling parameter, (ii) samples the per-object textures, and (iii) produces cull results for a set of database objects. In this fashion, the fragment processor in the GPU is leveraged to perform computationally intensive culling operations.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: June 17, 2008
    Assignee: Silicon Graphics, Inc.
    Inventor: Paolo Farinelli
  • Patent number: 7388589
    Abstract: A system, device and method are disclosed for predicting the opacity of primitives used to produce an image using one or more equations, prior to producing an image. More specifically, the present invention relates to a 3D device adapted to produce an image comprising an opacity estimate predictor adapted to predict opacity of at least one primitive using at least one first equation and further adapted to reject the primitive if the predicted opacity is equal to a minimum value.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: June 17, 2008
    Assignee: Broadcom Corporation
    Inventor: Charles Monahan
  • Patent number: 7385608
    Abstract: Redundant changes of tracked state issued by an application are filtered out by comparing the new state value with the old value, and if they are the same, no update is made. State changes are collected in on-chip memory and added to the bin if the state vector associated with the bin is out of date. State changes within a bin are done incrementally in temporal order, and a bin is only brought up to date prior to adding in a new primitive if the state has changed since the last primitive was added to it.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: June 10, 2008
    Assignee: 3DLabs Inc. Ltd.
    Inventor: David R. Baldwin
  • Patent number: 7382377
    Abstract: Method and apparatus for processing one or more fragment data. In one embodiment, the method includes processing one or more fragment data to generate one or more texture map addresses for one or more texels, determining relevance information that correspond to the texture map addresses, and translating the relevance information into a rendering constraint data structure.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: June 3, 2008
    Assignee: NVIDIA Corporation
    Inventors: Cass W. Everitt, William P. Newhall, Jr., David B. Glasco
  • Patent number: 7382368
    Abstract: A z buffer stores compressed z data represented in a planar format for one or more tiles. The compressed format includes a set of tile specific coefficients defining a plane equation for each z tested primitive intersecting the tile. The z buffer stores a maximum number of sets of tile specific coefficients for each tile, and when the maximum number of sets is exceeded for a particular tile, an uncompressed format is used to store the z data for the particular tile.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: June 3, 2008
    Assignee: NVIDIA Corporation
    Inventors: Steven E. Molnar, Mark J. French, John S. Montrym, Bengt-Olaf Schneider, Daniel P. Wilde
  • Patent number: 7375727
    Abstract: Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e.g., in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: May 20, 2008
    Assignee: NVIDIA Corporation
    Inventors: Edward Colton Greene, Patrick Matthew Hanrahan
  • Patent number: 7372471
    Abstract: A graphics system has a mode of operation in which primitive coverage information is generated for real sample locations and virtual sample locations for use in anti-aliasing pixels. An individual pixel has a single real sample with color information and at least one virtual sample. In one implementation each virtual sample within a pixel is a pointer that identifies whether the virtual sample belongs to the single real sample within the pixel or to a proximate neighboring pixel. The virtual sample information permits a blending weight to be determined for blending color values of a partially covered pixel with color values of neighboring pixels.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 13, 2008
    Assignee: Nvidia Corporation
    Inventor: Edward A. Hutchins
  • Patent number: 7369139
    Abstract: An apparatus includes a rendering engine to render a foreground of an image. The apparatus also includes a logic, separate from the rendering engine, to merge at least one background color with the foreground of the image.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: May 6, 2008
    Assignee: Honeywell International, Inc.
    Inventors: William R. Hancock, Robert J. Quirk, Panagiotis Papadatos