Abstract: Disclosed is an HDR film source playing method. The method includes following operations: determining state information of a color temperature control switch according to an application that is currently opened; playing an HDR film source on the application according to a color temperature of a display screen when the state information is on; and playing the HDR film source according to a color temperature corresponding to the application when the state information is off. Further disclosed are an HDR film source playing device and a computer-readable storage medium.

Abstract: An information processing method, device, and storage medium are provided. The method includes: a screen-transmission sending end, in response to a first operation acting on characters, displaying the characters in an input box in response to a first operation acting on the characters; determining a target screen-transmission code according to input characters; displaying the target screen-transmission code in the input box; parsing the target screen-transmission code and obtaining an IP address of a screen-transmission receiving end; establishing a connection with the screen-transmission receiving end according to the IP address; sending the target screen-transmission code to the screen-transmission receiving end to obtain a check result of the target screen-transmission code; and if the check result is that a check is passed, sending screen transmission data to the screen-transmission receiving end.

Abstract: A method including rendering graphics for an application using graphics processing units (GPUs). Responsibility for rendering of geometry is divided between GPUs based on screen regions, each GPU having a corresponding division of the responsibility which is known. First pieces of geometry are rendered at the GPUs during a rendering phase of a previous image frame. Statistics are generated for the rendering of the previous image frame. Second pieces of geometry of a current image frame are assigned based on the statistics to the GPUs for geometry testing. Geometry testing at a current image frame on the second pieces of geometry is performed to generate information regarding each piece of geometry and its relation to each screen region, the geometry testing performed at each of the GPUs based on the assigning. The information generated for the second pieces of geometry is used when rendering the geometry at the GPUs.

Abstract: An electronic device includes a display including a plurality of regions, a display driver integrated circuit configured to drive a first region of the display at a first driving frequency and drive a second region of the display at a second driving frequency according to a configuration of the display, and a processor configured to provide display data to the display driver integrated circuit. The processor identifies a driving frequency of a first screen to be output on the display in response to reception of a first input; and controls the display to output at least a portion of the first screen on a region, of the plurality of regions, driven at a driving frequency corresponding to the driving frequency of the first screen. The display optimizes driving frequency, thus reducing heating problems and resource waste in the electronic device.

Abstract: In methods and apparatuses for reducing latency in graphics processing inputs are received and a first set of frames is generated and stored. Once all of the frames in the first set of frames have been produced, they may be delivered to a GPU thread. Each frame is then rendered by the GPU. Starting processing of frames after one or more of the frames have been stored increases a likelihood that the GPU thread will produce rendered frames without stalling. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Abstract: A method includes determining an eye focus depth and determining a focus point relative to a viewing location in a virtual environment based on the eye focus depth, wherein the virtual environment includes a computer-generated object. The method also includes, upon determining that the focus point is located within a threshold distance from the computer-generated object, activating a function of a computer-executable code development interface relative to the computer-generated object.

Abstract: A display apparatus configured to adjust a driving frequency of a display panel by including a driving controller configured to: determine a low driving frequency corresponding to input image data; determine a plurality of compensation frequencies greater than the low driving frequency; and insert a plurality of compensation frequency frames having the compensation frequencies prior to a low driving frequency frame having the low driving frequency in a low frequency driving mode.

Abstract: A mobile terminal according to one embodiment is characterized by comprising: a display panel including active areas from which images are output; a first driver for controlling an image output from a first active area among the active areas; a second driver for controlling an image output from a second active area among the active areas; first data lines connected to the first driver to apply an image signal to the first active area; and second data lines connected to the second driver to apply an image signal to the second active area, wherein the first data lines and the second data lines may be provided in the active areas alternately in at least one area.

Abstract: A video transmitting circuit and a signal delay compensation method thereof are provided. The video transmitting circuit transmits a specific signal through a first transmission path and a second transmission path to a video receiver during a calibration mode. In the calibration mode, a return detection circuit of the video transmitting circuit detects whether or not a first return signal transmitted through the first transmission path and a second return signal transmitted through the second transmission path have been received by the video transmitting circuit. The video transmitting circuit sets delay circuits serially connected in the first or second transmission path according to a detection result of the return detection circuit, such that the first return signal transmitted through the first transmission path and the second return signal transmitted through the second transmission path can synchronously arrive at the video receiver.

Abstract: A visualization request to visualize data is received. System parameters responsive to the visualization request are obtained. Predicted performance metrics are generated with a machine learning model using the system parameters. A workload server is obtained using a workload server profile selected using the predicted performance metrics, the workload server executing a visualization workload to generate a visualization. The visualization of the data is streamed, from the workload server to the client device, responsive to the visualization request.

Abstract: A Secured Keyboard Video and Mouse (SKVM) system for selectively controlling a plurality of individual computers by a single set comprising a keyboard, a pointing device and at least one video monitor (in some cases, can be controlled also by computer), the SKVM comprising separate electrical circuits for transmitting the display sources, the pointing device and keyboard communications.

Abstract: A method for controlling an information terminal causes a computer of the information terminal to receive, from a case retrieval system, a plurality of similar medical images having a feature quantity of a region of interest and a certain degree of similarity in accordance with the region of interest included in a target medical image, displays a display screen displaying the plurality of received similar medical images on a touch panel display, the display screen including a display region in which at least some of the plurality of received similar medical images are displayed, displays, if selection of a first similar medical image from among the at least some of the plurality of received similar medical images displayed in the display region is detected, the first similar medical image across the display region, and displays, if a swipe operation performed on the first similar medical image is detected, a second similar medical image, which has second highest similarity next to the first similar medical im

Abstract: A system and a method for detecting baseboard management controller (BMC) includes the BMC and a CPLD. The BMC includes a GPIO and configured to drive the GPIO to output a first signal. The CPLD is connected to the GPIO and is configured to determine a status of the BMC by detecting whether the GPIO outputs the first signal. When the CPLD detects that the GPIO is not outputting the first signal, the CPLD determines that the BMC is in an abnormal status; when the CPLD detects that the GPIO is outputting the first signal and a level status of the first signal is switched in a predetermined time, the CPLD determines that the BMC is in a normal status.

Abstract: A disclosed electronic device includes a housing having an opening, a roll mounted in the housing, a flexible display wound on the roll and being extendable and retractable through the opening based on a rotation direction of the roll, and a roll guide configured to guide the roll to move in a direction capable of constantly maintaining a proceeding direction of the flexible display toward the opening in the housing, based on a variation in a wound length of the flexible display on the roll.

Abstract: A processing-in-memory (PIM) controller includes a read/arithmetic queue logic circuit, a write queue logic circuit, and a scheduling logic circuit. The read/arithmetic queue logic circuit stores read queues and arithmetic queues, generates an arithmetic mode signal when an arithmetic queue exists in the read/arithmetic queue logic circuit, and outputs the arithmetic queue in response to an arithmetic mode enablement signal. The write queue logic circuit stores write queues, generates an arithmetic write signal when an arithmetic write queue exists in the write queue logic circuit, and outputs the write queue in response to an arithmetic write enablement signal. The scheduling logic circuit transmits the arithmetic mode enablement signal to the read/arithmetic queue logic circuit in response to the arithmetic mode signal and transmits the arithmetic write enablement signal to the write queue logic circuit in response to the arithmetic write signal.

Abstract: Technology for a display source controller is described. The display source controller can receive display pixel data from a display source. The display source controller can convert the display pixel data to display symbol data that includes a plurality of 32-bit double words (DWords). The display source controller can divide the display symbol data that includes the plurality of 32-bit DWords for a number of unidirectional serial data channels. The display source controller can process, for each unidirectional serial data channel, the display symbol data at a 32-bit DWord granularity level. The display source controller can send the display symbol data for each of the unidirectional serial data channels over a physical serial link to a display panel.

Abstract: Disclosed are aspects of interference-aware virtual machine assignment for systems that include graphics processing units (GPUs) that are virtual GPU (vGPU) enabled. In some examples, an interference function is used to predict interference for assignment of a workload to a graphics processing unit (GPU). The interference function outputs a predicted interference to place the workload on the GPU. The workload is assigned to the GPU based on a comparison of the predicted interference to a plurality of predicted interferences for the workload on various GPUs.

Abstract: An image sticking compensation device includes: a deterioration calculator which calculates deterioration data of a current frame based on input image data and sensing frequency information which are received from a timing controller; an accumulator which accumulates the deterioration data and generates age data in which the deterioration data is accumulated; and a compensator which determines a grayscale compensation value corresponding to the age data and an input grayscale value of the input image data, and outputs age compensation data by applying the grayscale compensation value to the input image data. The sensing frequency information includes a frequency of the current frame, and the deterioration data varies in accordance with the frequency of the current frame.

Abstract: A method including rendering graphics for an application using graphics processing units (GPUs). Responsibility for rendering of geometry is divided between GPUs based on screen regions, each GPU having a corresponding division of the responsibility which is known. First pieces of geometry are rendered at the GPUs during a rendering phase of a previous image frame. Statistics are generated for the rendering of the previous image frame. Second pieces of geometry of a current image frame are assigned based on the statistics to the GPUs for geometry testing. Geometry testing at a current image frame on the second pieces of geometry is performed to generate information regarding each piece of geometry and its relation to each screen region, the geometry testing performed at each of the GPUs based on the assigning. The information generated for the second pieces of geometry is used when rendering the geometry at the GPUs.

Abstract: An organic light-emitting diode (OLED) display device includes a display panel including a plurality of pixels, the plurality of pixels being grouped into a plurality of pixel blocks, a nonvolatile memory configured to store previous accumulated block degradation information for the plurality of pixel blocks up to a previous driving period, a controller configured to calculate current block degradation information for the plurality of pixel blocks in a current driving period, to calculate current accumulated block degradation information for the plurality of pixel blocks up to the current driving period by adding the current block degradation information to the previous accumulated block degradation information in response to a power control signal indicating a power-off, and to determine whether a sensing operation for each of the plurality of pixel blocks is to be performed by comparing the current accumulated block degradation information for each of the plurality of pixel blocks with a sensing reference d

Abstract: A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.

Abstract: Particular embodiments described herein provide for an electronic device that includes a display and is configured enabling a low power refresh during a semi-active workload. The electronic device includes a display engine, where the display engine generates a video stream with a frame rate, a display, where the display includes an image viewable by a user and the image is refreshed at a first refresh rate, and a timing controller located in the display, where the timing control receives an indicator from the display engine and uses the indicator to determine that the first refresh rate can be lowered to a second refresh rate without the frame rate of the video stream from the display engine being changed. In an example, the indicator is frame with no image data at the start of the frame. In another example, the indicator is an implicit indictor sent by the display engine.

Abstract: A process display system includes a display terminal including a first processor and a process management system that includes a second processor and that communicates with the display terminal. The first processor or the second processor performs control of whether to update display of process information regarding a process. The process information is displayed by the display terminal. The control is performed on a basis of a change level of the process information on the display terminal.

Abstract: The present disclosure is directed to systems and methods of transferring bulk data, such as OLED compensation mask data, generated by a source device to a sink device using a high-bandwidth embedded DisplayPort (eDP) connection contemporaneous with an ENABLED Panel Self-Refresh (PSR) mode. Upon ENABLING the PSR mode, the source control circuitry causes the source transmitter circuitry, the sink receiver circuitry, and the eDP high-bandwidth communication link to remain active rather than inactive. The source control circuitry generates one or more data transport units (DTUs) having a header portion that contains data indicative of the presence of a bulk data payload and the non-display status of the bulk data payload carried by the DTUs.

Abstract: A computing device for dimensioning an object includes: a dimensioning subsystem configured to execute a default dimensioning method and a backup dimensioning method; a memory storing quality evaluation rules; a processor connected with the dimensioning subsystem and the memory, the processor configured to: control the dimensioning subsystem to execute a default dimensioning method to obtain default dimensioning data; compare a quality metric for the default dimensioning data to a threshold condition defined in the quality evaluation rules; when the quality metric exceeds the threshold condition, compute dimensions of the object based on the default dimensioning data; and when the quality metric does not exceed the threshold condition, control the dimensioning subsystem to execute the backup dimensioning method to obtain backup dimensioning data and compute the dimensions of the object based on the backup dimensioning data.

Abstract: A display device according to an embodiment includes a display panel including a plurality of pixels, and an image sticking compensator configured to generate a second image data by reflecting an age data accumulated in a first image data input from an external source. The image sticking compensator generates the age data by accumulating a deterioration data generated by reflecting a frequency weight corresponding to a determined frequency of a previous frame to an image data of the previous frame after the image data of the previous frame is stored.

Abstract: A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

Abstract: Technologies for efficiently accessing data columns and rows in a memory include a device with circuitry configured to receive a request to access memory in which each bit of a logical column of bits is located in a different physical row and a different physical column than any other bit in the logical column. The circuitry is additionally configured to access, in response to the request, the memory. In accessing the memory, the circuitry rotates one or more bit positions in a data set read from or written to the memory.

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

Abstract: A method for use in a computing system having a central processing unit (CPU) and a graphics processing unit (GPU), the method comprising: assigning a first memory portion and a second memory portion to: a worker thread of a work-stealing scheduler and an execution unit that is part of the GPU; retrieving a task from a queue associated with the worker thread; detecting, by the worker thread, whether a cutoff condition for the task is satisfied; when the cutoff condition is not satisfied, dividing the task into two or more additional tasks and adding the two or more additional tasks to the queue; when the cutoff condition is satisfied, storing first data corresponding to the task in the second memory portion, the first data being stored in the second memory portion by the worker thread; issuing a memory fence acquire instruction; and storing a first value in the first memory portion.

Abstract: Provided herein is a probe for treating an eye of a patient. In one or more embodiments, the probe includes a body, and a tubular element having a main lumen extending from the body, the tubular element comprising a distal end. The probe further includes a visualization optical fiber within the main lumen, the visualization optical fiber adapted to emit an illumination provided by at least one of a plurality of light sources connected to the visualization optical fiber. In some embodiments, the probe further includes an optical switching system (e.g., a time-division multiplexor) operable with the plurality of light sources, wherein the optical switching system is adapted to independently control each of the plurality of light sources. By providing time-division multiplexing between different surgical light sources, quasi-simultaneous illumination delivery through the same optical path may be achieved.

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: A display apparatus includes a plurality of display panels, a mounting frame, and a central control circuit. The mounting frame includes a side ridge electrically coupled to each of the plurality of display panels. The central control circuit is arranged inside the side ridge. The plurality of display panels are arranged such that a side edge of each of the plurality of display panels is attached to the side ridge to thereby allow the each of the plurality of display panels to be flipped open or close along the side ridge. The central control circuit is electrically coupled to each of the plurality of display panels, and is configured to control a display state of each of the plurality of display panels upon receiving a control signal from a user.

Abstract: An electronic panel comprises a base substrate which comprises a front surface comprising a hole area and a display area surrounding the hole area and a rear surface and comprises a module hole located in the hole area and a plurality of recess patterns located in the hole area, a plurality of pixels, an encapsulation layer covering the pixels and comprising a first inorganic layer, a second inorganic layer, and an organic layer, and a protective pattern located in the hole area and spaced apart from the organic layer when viewed in a plan view. The recess patterns comprise a filled recess pattern filled with at least one of the organic layer or the protective pattern, and an exposed recess pattern exposed from the organic layer and the protective pattern.

Abstract: An image display device includes: a signal input unit to which a first signal or a second signal is supplied using a signal cable in accordance with prescribed setting information, the signal cable having a plurality of transmission lines of prescribed transmission characteristics; a transmission line control unit configured to change a destination to which a signal is supplied using the plurality of transmission lines, in accordance with a transmission line setting for setting at least a portion of the plurality of transmission lines as transmission lines which transmit the first signal; an image control unit configured to generate an image signal from the first signal supplied using the transmission lines in accordance with a transmission format setting for designating a format for transmitting the first signal using the transmission lines; and a setting control unit configured to change the transmission line setting and the transmission format setting.

Abstract: An automated test equipment for testing devices under test is configured to combine different output signals from multiple pins of a single device under test or from pins of a plurality of devices under test to obtain a combined signal; and to extract individual signals or properties of the individual signals from the combined signal.

Abstract: Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.

Abstract: An information processing apparatus capable of providing address information of a line desired by a user. The information processing apparatus causes the user to select a line corresponding to the address information to be set in the near field wireless communication information, and sets the address information of the selected line in the near field wireless communication information, so as to transmit the near field wireless communication information, in which the address information of the line desired by the user is set, by near field wireless communication.

Abstract: Embodiments provide methods and systems for facilitating online shopping while watching multimedia content on an electronic device. The method includes receiving an input, from a controller, from a user interested in purchasing at least one item using a machine-readable code displayed in a scene of the multimedia content. The scene comprising the machine-readable code. The machine-readable code comprising payment information for purchasing the item. The method further includes capturing at least one screenshot of the scene comprising the machine-readable code without interrupting display of the multimedia content. The method also includes identifying the at least one machine-readable code in the at least one screenshot of the scene. Upon identifying the at least one machine-readable code the method includes extracting the at least one machine-readable code from the at least screenshot of the scene for processing a payment based on payment information present in the machine-readable code.

Abstract: An application runs at a first operating frequency if the application is designed for a current version of a system and runs at a second operating frequency if the application is designed for a prior version of the system that operates at a lower frequency than the first operating frequency. The second operating frequency may be higher than the operating frequency of the prior version of the system to account for differences in latency, throughput or other processing characteristics between the two systems. Software readable cycle counters are based on a spoof clock running at the operating frequency of the prior version of the system, rather than the true operating frequency. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Disclosed are aspects of interference-aware virtual machine assignment for systems that include graphics processing units (GPUs) that are virtual GPU (vGPU) enabled. In some examples, a plurality of workloads are executed alone and co-located with other workloads in a virtual graphics processing unit (vGPU)-enabled system to determine baseline parameters and measured interferences. A machine learning model is trained to predict interference based on the measured interferences and the baseline parameters. A workload is assigned and executed on a particular GPU associated with a minimum predicted interference with the workload based on currently-assigned workloads of the particular GPU.

Abstract: A method for controlling an information terminal causes a computer of the information terminal to receive, from a case retrieval system, a plurality of similar medical images having a feature quantity of a region of interest and a certain degree of similarity in accordance with the region of interest included in a target medical image, displays a display screen displaying the plurality of received similar medical images on a touch panel display, the display screen including a display region in which at least some of the plurality of received similar medical images are displayed, displays, if selection of a first similar medical image from among the at least some of the plurality of received similar medical images displayed in the display region is detected, the first similar medical image across the display region, and displays, if a swipe operation performed on the first similar medical image is detected, a second similar medical image, which has second highest similarity next to the first similar medical im

Abstract: A system and a method provide a memory-access technique that effectively parallelizes DRAM operations and coherency operations to reduce memory-access latency. The system may include a memory controller, an interconnect and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller through a first path and a second path in which the first path is through the interconnect and the second path bypasses the interconnect. The processor may be configured to send substantially concurrently a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path so that the DRAM access operations appear to be masked, or hidden by the coherency operations.

Abstract: A mobile communication system based on digital content including images and video that may be acquired, processed, and displayed using a plurality of mobile devices, smartphones, tablet computers, stationary computers, intelligent electronic glasses, and servers.

Abstract: A module structure includes a support film layer. The support film layer includes a film layer body and a stress relief gap disposed in the film layer body. The stress relief gap includes a layer gap, and the film layer body is divided into stacked sub-layers by the layer gap. In the module structure according to the embodiments of the present application, the stress relief gap is disposed in the film layer body of the support film layer.

Abstract: A system-on-a-chip (SoC) comprises a power supply circuit coupled to an energy harvesting transducer and configured to operate using energy from the energy harvesting transducer; a microcontroller coupled to a system bus of the SoC; an interface configured to communicate with the microcontroller via the system bus of the SoC, the interface configured to generate data upon occurrence of an event; and a computation accelerator configured to establish, based on an energy consumption level of the SoC, a data path between the interface and the computation accelerator that at least partially bypasses the system bus such that the data is transmitted to the computation accelerator via the data path.

Abstract: A processing unit includes a processor core that implements a physical function that supports multiple virtual functions. The processing unit includes a bus interface that supports communication between an external bus and the physical and virtual functions implemented using the processor core. During a reset of the processing unit, power is interrupted to the processor core power to the bus interface is maintained. The bus interface responds to requests for the physical and virtual functions received over the external bus concurrently with the power interruption. The bus interface responds based on state information associated with the virtual function. Power is restored to the processor core in response to the reinitialization of the GPU. The bus interface stops responding to requests for the physical and virtual functions received over the bus interface in response to restoring the power to the processor core and forwards requests received over the external bus from the bus interface to the processor core.

Abstract: An exemplary embodiment of the disclosure provides a memory management method for a rewritable non-volatile memory module. The method includes: receiving a first type command from a host system and temporarily storing the first type command to a first command queue; after receiving the first type command, receiving a second type command from the host system and temporarily storing the second type command to a second command queue; if the first command queue meets a preset condition, performing a programming operation for programming the rewritable non-volatile memory module according to the first type command in the first command queue; and after performing the programming operation, transmitting a response message corresponding to the second type command in the second command queue to the host system.

Abstract: Given a local distance metric for geospatial features, a binning is produced that is guaranteed to label features within a given distance threshold with the same bin, while labeling a minimum number of features separated by a distance that is greater than the threshold with the same bin.