Abstract: A data processing system comprises a processor that generates data elements of an array of data and stores the data elements in the one or more local buffers. When a set of data elements that corresponds to less than an entire region of plural separate regions that the array of data is divided into is to be written from the one or more local buffers to memory, the processor may encode the set of data elements so as to produce an encoded block of data and store the encoded block of data in memory by: writing body data to one of a first body buffer and a second body buffer, wherein the set of data elements is encoded using a first encoding for which header information descriptive of the body data will be independent of the values of the data elements being encoded.

Abstract: Systems and methods related to priority-based and performance-based selection of a render mode, such as a two-level binning mode, in which to execute workloads with a graphics processing unit (GPU) of a system are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) configures low and medium priority workloads to be executed in a two-level binning mode and selects a binning mode for high priority workloads based on whether performance heuristics indicate that one or more binning conditions or override conditions have been met. High priority workloads are maintained in a high priority queue, while low and medium priority workloads are maintained in a low/medium priority queue, such that execution of low and medium priority workloads at the GPU can be preempted in favor of executing high priority workloads.

Abstract: Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

Abstract: A display device includes a display panel divided into panel blocks including pixels, and a display panel driver which drives the display panel, sets a time point to which a set time elapses from a time point when input image data is determined to be a still image as an operation time point, decreases a luminance gain from the operation time point, determines the set time based on accumulated deterioration amounts of the panel blocks, and applies the luminance gain to the input image data.

Abstract: Apparatuses, systems, and techniques including APIs to enable one or more fifth generation new radio (5G-NR) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. For example, a processor comprising one or more circuits to perform an application programming interface (API) to cause fifth generation new radio (5G-NR) packaging, synchronization, or management information to be indicated to one or more accelerators.

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may obtain a first indication of a first image including a set of first image sections with a plurality of first subsections and a second indication of a second image including a set of second image sections with a plurality of second subsections. The apparatus may also compare one first image section with one second image section. Further, the apparatus may calculate a magnitude of difference between one first subsection and each of the multiple second subsections. The apparatus may also output a third indication of at least one of: (1) a lowest magnitude of difference between the one first subsection and each of the multiple second subsections or (2) a set of coordinates for a second subsection that corresponds to the lowest magnitude of difference.

Abstract: Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.

Abstract: A software library for providing a uniform framework for various applications or third-party applications access to sensor data. The system further includes a sensor control module and a remote management module. The sensor control module includes logic for communicating with the sensors and receiving sensor data and to communicate that sensor data to the remote management module or various applications. The sensor control module may include a user interface that may display a banner containing numerous components. The content of the banner may differ depending on the host application. The system may further include a host application that incorporates the banner.

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Abstract: Provided are systems, methods, and apparatuses for managing memory. The method can include: establishing a connection via an interface, between a host device and a storage device; and transferring data, via the interface, between first memory associated with the host device and second memory associated with the storage device by performing a data operation on the second memory by an application executed by the host, where the storage device includes a processing element that accelerates the data operation by performing at least one offload function on the data operation.

Abstract: In a digital contents receiver for receiving transmitted digital contents, the digital contents include at least component information indicating an element which constitutes a program of the contents. When the component information indicates that the received digital contents are a 3D component, it is determined whether a display part corresponds to display of the 3D component. If the display part corresponds to display of the 3D component, the received digital contents are displayed in 3D.

Abstract: Systems and techniques are disclosed for testing the functional equivalence of a legacy system, such as mainframe system, and an adapted system, such as a cloud version of the mainframe system. The same input can be provided to both the legacy system and the adapted system, such that the legacy system and the adapted system can both operate separately on copies of the same input. Results produced by the legacy system and the adapted system based on the same input can accordingly be compared. If results produced by the legacy system and the adapted system over time are determined to be functionally equivalent, the adapted system can be determined to be functionally equivalent to the legacy system.

Abstract: Discussed are an image display device and an operating method therefor. An image display device can include a display panel that includes a plurality of pixels; a backlight unit that irradiates light to the display panel; and a control unit, wherein the control unit may determine a screen refresh rate for an image outputted through the display panel, determine a vertical blanking period for each frame in response to the determined refresh rate, calculate a pixel clock frequency corresponding to the determined vertical blanking period, and control, according to the determined pixel clock frequency, an operation of a plurality of driving elements disposed on the display panel which correspond to the plurality of pixels, respectively.

Abstract: A system and method for rendering vector graphics using precomputed textures, includes receiving a vector image, the vector image including a plurality of instructions, each instruction for rendering at least a geometric primitive; detecting in the plurality of instructions an instruction for generating a first Bezier curve; selecting a first precomputed curve in a texture map to match the first Bezier curve; and generating a raster image based at least on the first precomputed curve. In an embodiment selecting the first precomputed curve includes computing a transformation matrix between the first precomputed curve and target coordinates, wherein the target coordinates are coordinates of a display; computing texture coordinates based on the computed transformation matrix and the texture map; and rendering an adapted precomputed curve, based on the texture map and the computed texture coordinates.

Abstract: One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

Abstract: A multi-user application system environment engine has an application system that, in turn, includes a simulation engine and a virtualized software environment. The simulation engine runs on top of the virtualized software environment and includes a declaration processor, a scene tree object manager, a persistence processor in communication with the scene tree object manager, a visual editor, an editor broadcaster, an editor listener, and a rendering processor, coupled to the virtualized software environment, to requisition hardware resources to cause physical manifestation of an instantiated scene tree of objects.

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Abstract: One embodiment provides for a machine-learning accelerator device a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream. The compute unit includes compute logic configured to execute a single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the compute logic to scale the input tensor to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type.

Abstract: An image rendering method for rendering a pixel at a viewpoint including: for a first element of a virtual scene, having a predetermined surface at a position within that scene, providing the position and a direction based on the viewpoint to a machine learning system previously trained to predict a factor that, when combined with a distribution function that characterises an interaction of light with the predetermined surface, generates a pixel value corresponding to the first element of the virtual scene as illuminated at the position, combining the predicted factor from the machine learning system with the distribution function to generate the pixel value corresponding to the illuminated first element of the virtual scene at the position, and incorporating the pixel value into a rendered image for display.

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

Abstract: The maximum capacity of a very fast memory in a system that requires very fast memory access times is increased by adding a memory with remote access times that are slower than required, and then moving infrequently accessed data from the memory with the very fast access times to the memory with the slow access times.

Abstract: Described herein is a computer implemented method for processing a set of operations including one or more vector type operations. The method includes processing the set of operations to generate one or more corresponding page elements for an editable document by: calculating an expanded bounding box for each vector type operation in the set of operations; associating each vector type operation with a subgroup, wherein a given subgroup is associated with one or more vector type operations which have collectively overlapping expanded bounding boxes; and processing each subgroup to generate a corresponding page element, wherein the page element corresponding to a given subgroup comprises drawing data based on each vector type operation associated with the given subgroup.

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to convert elements of a floating-point tensor to convert the floating-point tensor into a fixed-point tensor.

Abstract: An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

Abstract: Various implementations disclosed herein include devices, systems, and methods that use an analytic approach to determine signed distance field (SDF) representations that represent one or more curves (e.g., glyphs that represent text) and cache the SDF representations for reuse in rendering the curves in similar rendering conditions. For example, the SDF representation may be re-used, based on determining that text is going to occupy a similar-sized portion of the device's display in multiple views. An SDF representation is recalculated if different conditions (e.g., substantial zooming in on the text) occur in different views.

Abstract: Disclosed embodiments relate to atomic memory operations. In one example, a method of executing an instruction atomically and with weak order includes: fetching, by fetch circuitry, the instruction from code storage, the instruction including an opcode, a source identifier, and a destination identifier, decoding, by decode circuitry, the fetched instruction, selecting, by a scheduling circuit, an execution circuit among multiple circuits in a system, scheduling, by the scheduling circuit, execution of the decoded instruction out of order with respect to other instructions, with an order selected to optimize at least one of latency, throughput, power, and performance, and executing the decoded instruction, by the execution circuit, to: atomically read a datum from a location identified by the destination identifier, perform an operation on the datum as specified by the opcode, the operation to use a source operand identified by the source identifier, and write a result back to the location.

Abstract: Embodiments relate to extracting features from images, such as by identifying keypoints and generating keypoint descriptors of the keypoints. An apparatus includes a pyramid image generator circuit, a keypoint descriptor generator circuit, and a pyramid image buffer. The pyramid image generator circuit generates an image pyramid from an input image. The keypoint descriptor generator circuit processes the pyramid images for keypoint descriptor generation. The pyramid image buffer stores different portions of the pyramid images generated by the pyramid image generator circuit at different times and provides the stored portions of the pyramid images to the keypoint descriptor generator circuit for keypoint descriptor generation. When first portions of the pyramid images are no longer needed for the keypoint descriptor generation, the first portions are removed from the pyramid image buffer to provide space for second portions of the pyramid images that are needed for the keypoint descriptor generation.

Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

Abstract: An autonomous vehicle is described herein. The autonomous vehicle comprises a first sensor and a second sensor having limited fields of view, an articulation system, and a computing system. The computing system determines a first region and a second region external to the autonomous vehicle based on a sensor prioritization scheme comprising a ranking of regions surrounding the autonomous vehicle. The computing system then causes the articulation system to orient the first sensor towards the first region and the second region towards the second region. Responsive to receiving a sensor signal from the first sensor indicating that an object has entered a field of view of the first sensor, the computing system determines a third region having a higher ranking than the second region within the sensor prioritization scheme. The computing system then causes the articulation system to orient the second sensor towards the third region.

Abstract: An electronic device may include a display, a communication circuit, a processor operatively connected to the display and the communication circuit, and a memory operatively connected to the processor, wherein the memory may store instructions which, when executed, cause the processor to: receive information relating to at least one application installed in an external electronic device from the external electronic device through the communication circuit; configure, on the basis of the received information, the at least one application as a remote control application controlled by the electronic device; receive a notification message related to the remote control application from the external electronic device through the communication circuit; and display, on the display, a first object indicating reception of the notification message. Various other embodiments are also possible.

Abstract: A method for operating an electronic device having a display panel is provided. The display panel has a first region and a second region, in which the first region is out of a case, and the second region is capable of being shielded by the case. First, a first image is displayed in the first region. Then, a second image is displayed in the second region at a first time point when the second region is shielded by the case. After that, the second region out of the case is moved at a second time point, in which the first time point is not later than the second time point.

Abstract: A method, apparatus and system for social networking is provided. In an embodiment, the system comprises a plurality of mobile devices that can directly connect to each other via a peer-to-peer connection. The devices can additionally connect to a server. The server maintains a profile schema which can be used to generate profiles for users for each of the mobile devices. Electronic devices are paired based on a shared key maintained in an application loaded on the first electronic device and the second electronic device.

Abstract: A system and method for an on-demand shuttle, bus, or taxi service able to operate on private and public roads provides situational awareness and confidence displays. The shuttle may include ISO 26262 Level 4 or Level 5 functionality and can vary the route dynamically on-demand, and/or follow a predefined route or virtual rail. The shuttle is able to stop at any predetermined station along the route. The system allows passengers to request rides and interact with the system via a variety of interfaces, including without limitation a mobile device, desktop computer, or kiosks. Each shuttle preferably includes an in-vehicle controller, which preferably is an AI Supercomputer designed and optimized for autonomous vehicle functionality, with computer vision, deep learning, and real time ray tracing accelerators. An AI Dispatcher performs AI simulations to optimize system performance according to operator-specified system parameters.

Abstract: On an electronic device which includes a display device comprising a display driving circuit, a processor, and a memory a method for changing a refresh rate of the display device includes: changing at least one of a first parameter, a second parameter, or a third parameter in response to identifying the occurrence of at least one of a scan rate change request or a change in scan rate change restriction, and applying the changed parameter among the first parameter, the second parameter, and the third parameter. The first parameter is the frequency of a first synchronization signal generated in the display driving circuit, the second parameter is the increase or decrease in a blank area to substitute for a portion of active video area in frame information, and the third parameter is the frequency of a second synchronization signal for rendering.

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

Abstract: An object of the present invention is to achieve both suppression of data amount of an image processing system that learns a collation image to be used for image identification using a discriminator and improvement of identification performance of the discriminator. In order to achieve the above object, there is proposed an image processing system including a discriminator that identifies an image using a collation image, the image processing system further including a machine learning engine that performs machine learning of collation image data required for image identification. The machine learning engine searches for a successfully identified image using an image for which identification has been failed, and adds information, obtained based on a partial image of the image for which identification has been failed and which has been selected by an input device to the successfully identified image obtained by the search to generate corrected collation image data.

Abstract: In a digital contents receiver for receiving transmitted digital contents, the digital contents include at least component information indicating an element which constitutes a program of the contents. When the component information indicates that the received digital contents are a 3D component, it is determined whether a display part corresponds to display of the 3D component. If the display part corresponds to display of the 3D component, the received digital contents are displayed in 3D.

Abstract: A multi-channel voltage sensing circuit for pixel compensation includes a plurality of channel circuits arranged for multiple channels; and a first dummy channel circuit and a second dummy channel circuit disposed among the plurality of channel circuits with some channel circuits interposed therebetween, wherein the first dummy channel circuit and the second dummy channel circuit receive a first reference voltage of a fixed level, and provide electrical coupling to adjacent channel circuits.

Abstract: The disclosure provides a display equipment, a brightness compensation device, and a brightness compensation method. The brightness compensation device includes a variable refresh rate (VRR) detection circuit and a control circuit. The VRR detection circuit and the control circuit receive a video stream from a video source device, and the video stream includes a VRR video frame. The VRR detection circuit detects a blanking period of the VRR video frame and generates a detection result. The control circuit outputs the frame data of the VRR video frame to the display device during the valid data period of the VRR video frame. The control circuit repeatedly outputs the frame data of the VRR video frame to the display device during the blanking period of the VRR video frame according to the detection result until the blanking period ends.

Abstract: A computer-implemented method, a computer system and a computer program product annotate media files with convenient pause points. The method includes acquiring a text file version of an audio narration file. The text file version includes a pause point history of a plurality of prior users. The method also includes generating a list of pause points based on the pause point history. In addition, the method includes determining a tone of voice being used by a speaker at each pause point using natural language processing algorithms. The method further includes determining a set of convenient pause points based on the list of pause points and the determined tone of voice. Lastly, the method includes inserting the determined set of convenient pause points into the audio narration file.

Abstract: Techniques are described for expanding and/or improving the Advanced Television Systems Committee (ATSC) 3.0 television protocol in robustly delivering the next generation broadcast television services. Multiple memory buffers are used to manage broadcast packet repair and presentation or storage.

Abstract: A processing system includes a graphics pipeline that executes a first shader of a first type and a second shader of a second type. In some cases, the first shader is a geometry shader and the second shader is a pixel shader. The processing system also includes buffers that hold primitives generated by the first shader and provide the primitives to the second shader. The processing system also includes a primitive hub that monitors fullness of the buffers. Launching of waves from the first shader is throttled based on the fullness of the buffers. A shader processor input (SPI) selectively throttles the waves launched by the geometry shader based on a signal from the primitive hub indicating the fullness, an indication of relative resource usage of geometry waves and pixel waves in the graphics pipeline, or an indication of lifetimes of the geometry waves.

Abstract: Systems, methods, and apparatuses disclose an electronic greeting card application for creating, editing, distributing, and viewing electronic greeting cards on a portable computing device, wherein the electronic greeting card displays animations and permits users to customize the card by way of adding a message, signature, photo, and sound recording.

Abstract: Example methods, apparatuses and systems are disclosed for providing a device for capturing a barcode image within an augmented reality environment. An example method includes detecting a target object within a field of view of an augmented reality viewing device. The method further includes rendering an image of a scanning device within the field of view of the augmented reality viewing device, and rendering a scanning area within the field of view of the augmented reality viewing device. Further, a camera associated with the augmented reality viewing device captures an image of a barcode located on the target object. Corresponding apparatuses, systems, and computer program products are also provided.

Abstract: An apparatus for, by inputting data to a hierarchical neural network and performing operation processing in each layer of the network, calculating a feature plane in the layer, comprises an operation unit, a feature plane holding unit including at least one memory that holds a feature plane to be processed, a unit configured to control to arrange the feature plane in the memory based on network information as information about each layer undergoing the operation processing and to manage reading/writing from/in the memory, and a processor configured to access, via a bus, the feature plane holding unit which is address-mapped in a memory space. The processor calculates, based on the network information, an address address-mapped in the memory space, reads out the feature plane, and processes the feature plane.

Abstract: Systems and methods are provided for efficiently performing processing intensive operations, such as those involving large volumes of data, that enable accelerated processing time of these operations. In at least one embodiment, a system includes a graphics processor unit (GPU) including a memory and a plurality of cores. The plurality of cores perform a plurality of data analytics operations on a respectively allocated portion of a dataset, each of the plurality of cores using only the memory to store data input for each of the plurality of data analytics operations performed by the plurality of cores. The data storage for the plurality of data analytics operations performed by the plurality of cores is also provided solely by the memory.

Abstract: In various examples, a signal processing pipeline is dynamically generated or instantiated for a signal processing request. To generate the pipeline, a graph topology—including nodes and edges—may be created to represent features, functionality, and characteristics of a signal processing system. The nodes, representing processing tasks, may be connected via edges having associated costs for performing, by a node, a processing task on an output of a prior or edge-connected node. For a given signal processing request, the nodes or processing tasks to be included may be selected and, using a graph routing algorithm and the costs between and among the determined nodes, a path through the nodes may be determined—thereby defining, at least in part, the signal processing pipeline.

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to quantize elements of a floating-point tensor to convert the floating-point tensor into a dynamic fixed-point tensor.

Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.