Computer Graphic Processing System Patents (Class 345/501)
  • Patent number: 10893253
    Abstract: Method, apparatus and computer readable media for receiving a multiprogram program transport service that includes one or more compressed video services and one or more 3D-2D conversion options, generating an uncompressed video signal by performing a decoding portion of a transcoding operation for one of the one or more of the video services, determining from the 3D-2D conversion option whether a 3D-2D conversion is to be performed, performing a scale conversion on the uncompressed video according to a specified type of 3D-2D conversion, generating a compressed video service by performing an encoding portion of a transcoding operation on the uncompressed video that has been scale converted, and generating a second multiprogram program transport service that includes the compressed video signal that has been 3D-2D converted.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 12, 2021
    Assignee: Google Technology Holdings LLC
    Inventors: Mark L. Schaffer, Siu-Wai Wu
  • Patent number: 10884772
    Abstract: A method for emulating an image processing system on an emulator may include pre-processing of image files that comprises converting each of the image files to a file of low-level image data packets; when emulating the image processing system on the emulator, loading each of the files of low-level image data packets to a memory of the emulator; reading the loaded file from the memory and streaming that file of said files of low-level image data packets to the emulated image processing system.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: January 5, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yafit Snir, Roi Sakat, Sanjay Kumar, Abhay Srivastava
  • Patent number: 10872458
    Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to access one or more entries in a set of multiple translation entries for pages of the surface space (where the translation entries are stored using addresses in a virtual space and map pages of the surface space to the virtual space) and translate address information for the surface space to address information in the virtual space based on one or more of the translation entries.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Apple Inc.
    Inventors: Anthony P. DeLaurier, Michael J. Swift, Michal Valient, Robert S. Hartog, Tyson J. Bergland, Gokhan Avkarogullari
  • Patent number: 10867433
    Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 15, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Jonathan Redshaw
  • Patent number: 10866915
    Abstract: A method for increasing compatibility of DisplayPort includes: providing a first source device, a second source device, a controller, and a sink device, wherein the first source device is connected to the controller; the first source device transmitting a first image signal to the sink device via a main link for displaying the first image signal on the sink device; causing the controller to disconnect from the first source device and connect to the second source device; executing a simulation process to generate a DC level variation on an auxiliary channel between the controller and the sink device; the second source device transmitting auxiliary data to the sink device; the sink device transmitting link data back to the second source device; and the second source device transmitting a second image signal to the sink device via a second main link for displaying the second image signal on the sink device.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 15, 2020
    Assignee: ATEN International Co., Ltd.
    Inventors: Kai-Jui Chan, Ting-Ju Tsai
  • Patent number: 10862830
    Abstract: A system and method for real-time data transfer on a system-on-chip (SoC) allows MIPI-CSI (camera serial interface) data received on a first interface to be output on another MIPI-CSI interface without using system memory or delaying the loopback path. The system includes a CSI receiver, a loopback buffer, and a CSI transmitter. The loopback buffer is used for the data transfer between the CSI receiver and the CSI transmitter. The CSI transmitter receives a payload included in a data packet from the CSI receiver by way of the loopback buffer. The CSI receiver communicates a packet header of the data packet to the CSI transmitter. The CSI transmitter reads the payload from the loopback buffer based on the packet header and at least one of a buffer threshold capacity and payload size.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 8, 2020
    Assignee: NXP USA, INC.
    Inventors: Naveen Kumar Jain, Joachim Fader, Shreya Singh, Nishant Jain, Anshul Goel
  • Patent number: 10854533
    Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung Hao Chen, Chin-Cheng Kuo
  • Patent number: 10846041
    Abstract: An example electronic device includes: an audio and video (AV) processor, a computer subsystem, a control mechanism, and a media playing device. The AV processor includes an AV input port to receive external AV signals from an external media source. The computer subsystem is to provide internal AV signals to the AV processor. The control mechanism is to control the AV processor to select between the external AV signals and the internal AV signals, and enable the AV processor to transmit selected AV signals to the media playing device. The media playing device is to play the selected AV signals.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: November 24, 2020
    Assignee: Hewlett-Packard Development Comany, L.P.
    Inventors: Tao-Sheng Chu, Maureen Min-Chaun Lu, Yl-Ling Lo, Victor Lee, Chan-Liang Lin, Candy Wu
  • Patent number: 10848568
    Abstract: Disclosed are systems and methods for computer power management. In one aspect, a method comprises determining whether a frame rate at a client device is greater than a predetermined threshold value, determining whether the frame rate has remained constant, when the frame rate is greater than the predetermined threshold value and when the frame rate has remained constant, activating a poll mode at the client device, otherwise: activating a push mode at the client device to preserve power at the server, and executing reception of content for display at the client device from the server according to the activated mode.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 24, 2020
    Assignee: Parallels International GmbH
    Inventors: Denis Ozerov, Stanislav Zinukhov, Nikolay Dobrovolskiy, Serguei Beloussov
  • Patent number: 10839476
    Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a graphics processor comprising a compute unit to execute multiple concurrent threads and a memory coupled with and on a same package as the compute unit. The memory can store thread state for a suspended thread and the compute unit can detect that multiple concurrent threads of the compute unit are blocked from execution. Upon detection, the compute unit can select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and select an additional thread to be executed. The compute unit can then replace the victim thread with an additional thread to be executed. The additional thread to be executed can be based on a blocking event for the additional thread.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Patent number: 10832465
    Abstract: A technique for executing pixel shader programs is provided. The pixel shader programs are executed in workgroups, which allows access by work-items to a local data store and also allows program synchronization at barrier points. Utilizing workgroups allows for more flexible and efficient execution than previous implementations in the pixel shader stage. Several techniques for assigning fragments to wavefronts and workgroups are also provided. The techniques differ in the degree of geometric locality of fragments within wavefronts and/or workgroups. In some techniques, a greater degree of locality is enforced, which reduces processing unit occupancy but also reduces program complexity. In other techniques, a lower degree of locality is enforced, which increases processing unit occupancy.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 10, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Skyler Jonathon Saleh
  • Patent number: 10831738
    Abstract: Apparatuses and Methods for sorting a data set. A data storage is divided into a plurality of buckets that is each associated with a respective key value. A plurality of stripes is identified in each bucket. A plurality of data stripe sets is defined that has one stripe within each respective bucket. A first and a second in-place partial bucket radix sort are performed on data items contained within the first and second data stripe sets, respectively, using an initial radix. Incorrectly sorted data items in the first bucket are grouped by a first processor and incorrectly sorted data items in the second bucket are grouped by a second processor into a respective incorrect data item group within each bucket. A radix sort is then performed using the initial radix on the items within the respective incorrect data item group. A first level sorted output is produced.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rajesh Bordawekar, Daniel Brand, Minsik Cho, Ulrich Finkler, Ruchir Puri
  • Patent number: 10804501
    Abstract: A display device includes a light shielding layer having an opening. A fingerprint sensor is disposed within or overlapping the opening of the light shielding layer. A light path control layer is disposed on the fingerprint sensor and the light shielding layer. The light path control layer covers the opening of the light shielding layer. A display panel is disposed on the light path control layer and includes a plurality of display elements. A window panel is disposed on the display panel.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yun Ho Kim, Go Woon Kang
  • Patent number: 10795997
    Abstract: Techniques and computing devices for mitigating return-oriented programming (ROP) attacks are described. A hardened stack and an unhardened stack are provided. The hardened stack can include indications of return addresses while the unhardened stack can include all other memory allocations. A stack hardening instruction can be inserted before unhardened instructions (e.g., instructions that are themselves not authorized to access the hardened stack). The stack hardening instruction determines whether the unhardened instruction accessed memory outside the unhardened stack and generates a fault based on the determination. A register can be provided to include an indication of an address span of the unsafe stack. The stack hardening instruction can determine whether the unhardened instruction accessed a memory location outside the address range specified in the register and generate a fault accordingly.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: October 6, 2020
    Assignee: INTEL CORPORATION
    Inventor: Michael Lemay
  • Patent number: 10795434
    Abstract: Interface-based modeling and design of three dimensional spaces using two dimensional representations are provided herein. An example method includes converting a three dimensional space into a two dimensional space using a map projection schema, where the two dimensional space is bounded by ergonomic limits of a human, and the two dimensional space is provided as an ergonomic user interface, receiving an anchor position within the ergonomic user interface that defines a placement of an asset relative to the three dimensional space when the two dimensional space is re-converted back to a three dimensional space, and re-converting the two dimensional space back into the three dimensional space for display along with the asset, within an optical display system.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 6, 2020
    Assignee: RPX CORPORATION
    Inventor: Sterling Crispin
  • Patent number: 10798162
    Abstract: A fail-safe system for a cluster application is disclosed. The system includes a first subsystem comprising a graphic processing unit (GPU) that executes a high-level operating system renders a first set of parameter data, and a second subsystem that executes a real-time operating system and renders a second set of parameter data. The system also includes a controller area network connected to a parameter data source input and to the first subsystem and the second subsystem. The system further includes a quality of service (QoS) switch executing a QoS monitor module that decides to display the first set of parameter data being rendered by the first subsystem or the second set of parameter data being rendered by the second subsystem depending on an availability and load of the first subsystem as determined by a lag and a stability threshold. The system further includes a display connected to the QoS switch.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 6, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nikhil Nandkishor Devshatwar, Shravan Karthik, Santhana Bharathi N, Subhajit Paul
  • Patent number: 10765889
    Abstract: At each step of a workflow performed by an operator that involves a plurality of input mechanisms in a radiation therapy system, the operator is assisted in the process of selecting the next input mechanism in a way that greatly reduces the number of possible input mechanisms that can be chosen. A first subset of input mechanisms is made visually prominent via a first visual technique and a second subset of the input mechanisms is made visually prominent via a second visual technique. The first subset includes input mechanisms that are available for selection at that particular step in the workflow and the second subset includes recommended input mechanisms that are the most likely to be the next input mechanism that should be actuated by the operator at that particular step in the workflow.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 8, 2020
    Assignee: VARIAN MEDICAL SYSTEMS, INC.
    Inventors: Susan Koehl, Ross Hannibal
  • Patent number: 10755375
    Abstract: Disclosed are methods, systems, devices, apparatus, media, and other implementations, including a method that includes obtaining input visual data comprising a sequence of symbols, selected from a symbol set, with each of the symbols associated with a glyph representation. The method also includes obtaining a code message comprising code message symbols, and modifying at least one of the symbols of the input visual data to a different glyph representation associated with a respective at least one of the code message symbols to generate, at a first time instance, a resultant coded visual data.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 25, 2020
    Inventors: Changxi Zheng, Chang Xiao, Cheng Zhang
  • Patent number: 10747585
    Abstract: Methods and apparatus to perform data migration in a distributed cloud management automater are disclosed. An example apparatus includes a source data generator to generate a migration package corresponding to a source cloud management automater; a target cloud management automater migrator to migrate data of the migration package into a target cloud management automater; and performing a schema upgrade of a target database of the target cloud management automater; and a target service upgrader to upgrade service components at the target cloud management automater based on the migration package.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: August 18, 2020
    Assignee: VMware Inc.
    Inventors: Bryan Halter, Alexey Grunkov, Paul Howes, Miroslav Mitevski, Madhavi Koganti
  • Patent number: 10726607
    Abstract: To determine whether a first n-bit binary data value and a second n-bit binary data value in a data processing system, such as texel position coordinates in a graphics processing system, are the same or differ from each other by exactly one, it is determined whether the first and second data values excluding the least significant bits of the data values are the same as each other, and the least significant bits of the data values are compared. A mask value that is generated for each data value using an XOR operation and a thermometer scanning operation is used to generate an output value for the two data values, based on whether the mask values for a bit position for the first and second data values are both set or not, and a comparison of the bit values of the first and second data values for that bit position.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventor: Antonio Garcia Guirado
  • Patent number: 10725929
    Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jianfang Zhu, Cristiano J. Ferreira, Bo Qiu, Ajit Krisshna Nandyal Lakshman, Nikhil Talpallikar, Deepak Gandiga Shivakumar, Brandt M. Guttridge, Kim Pallister, Frank J. Soqui, Anand Srivatsa, Travis T. Schluessler, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Altug Koker, Jonathan Kennedy
  • Patent number: 10706724
    Abstract: An autonomous vehicle is described herein. The autonomous vehicle comprises a first sensor and a second sensor having limited fields of view, an articulation system, and a computing system. The computing system determines a first region and a second region external to the autonomous vehicle based on a sensor prioritization scheme comprising a ranking of regions surrounding the autonomous vehicle. The computing system then causes the articulation system to orient the first sensor towards the first region and the second region towards the second region. Responsive to receiving a sensor signal from the first sensor indicating that an object has entered a field of view of the first sensor, the computing system determines a third region having a higher ranking than the second region within the sensor prioritization scheme. The computing system then causes the articulation system to orient the second sensor towards the third region.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 7, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Elliot Branson, Eric Lujan, Benjamin Earle Weinstein-Raun
  • Patent number: 10699364
    Abstract: Aspects described herein are directed to leveraging multiple graphics processors, by a virtual GPU manager, to optimize the rendering of graphics in either a desktop or virtual desktop environment. The virtual GPU manager may enumerate all available physical GPUs, query performance variables including processing capacity of each of the available physical GPUs, and classify each of the physical GPUs based on the queried performance variables. Further, the virtual GPU manager may generate a logical GPU corresponding to one or more of the available physical GPUs. The virtual GPU manager may distribute graphics rendering requests across each of the plurality of available physical GPUs by way of the logical GPU.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 30, 2020
    Assignee: Citrix Systems, Inc.
    Inventor: Ashwin Suresh
  • Patent number: 10699369
    Abstract: Methods and apparatus relating to techniques for intelligent memory DVFS (Dynamic Voltage and Frequency Scaling) scheme exploiting graphics inter-frame level correlation are described. In an embodiment, collection logic collects bandwidth usage information by a system agent during performance of one or more operations associated with a first graphics workload. Memory stores the collected bandwidth usage information. The selection logic causes selection of an operating frequency for the system agent to perform a plurality of operations associated with one or more graphics workloads based at least on the stored collected bandwidth usage information. The one or more graphics workloads occur after the first graphics workload. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventor: Jaymin B. Jasoliya
  • Patent number: 10692173
    Abstract: Technologies for utilizing a bowl-shaped image include a computing device to receive a first fisheye image capturing a first scene and a second fisheye image capturing a second scene overlapping with the first scene at an overlapping region. The computing device generates a combined image of the first fisheye image and the second fisheye image, performs object classification on a region of interest of at least one of the first fisheye image or the second fisheye image to classify an object within the region of interest, and generates a portion of a bowl-shaped image based on the combined image.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Kay-Ulrich Scholl, Koba Natroshvili
  • Patent number: 10691838
    Abstract: Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode. Caches in XIP interfaces provide seamless access to multiple memories, or multiple portions of a single memory. The cryptography block is configured to encrypt and decrypt XIP data transfers to and from a first external memory device in the XIP mode, and to encrypt and decrypt MMIO data transfers to and from a second external memory device in the MMIO mode.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 23, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hans Van Antwerpen, Jan-Willem Van de Waerdt
  • Patent number: 10692270
    Abstract: Various approaches to performing non-divergent parallel traversal operations for a bounding volume hierarchy (“BVH”) during ray tracing are presented. For example, a computer system has a processing unit with threads that, collectively, perform ray tracing for a group of rays in parallel in a computer-represented environment, which includes geometric objects (such as triangles) enclosed in the BVH. Each of the threads receives parameters for a given ray and traverses the BVH to determine an intersection, if any, between the given ray and one of the geometric objects. The order of traversal of the BVH is synchronized between threads for the rays of the group, for example, using a cross-group operation such as a ballot operation. In this way, the overall speed of the BVH traversal can be improved in many cases, while avoiding code divergence and data divergence in extra-wide single-instruction, multiple data (“SIMD”) graphics processing unit (“GPU”) architectures.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: June 23, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: James D. Stanard, Ivan Nevraev
  • Patent number: 10692418
    Abstract: The present invention discloses a low power driving system and timing controller for a display apparatus. The low power driving system may include: a timing controller configured to divide a display pattern into a static pattern and a dynamic pattern based on a difference between previous line data and current line data, and transmit a packet into which one of first option information corresponding to the static pattern and second option information corresponding to the dynamic pattern is applied; and a source driver configured to receive the packet, and perform a low power mode corresponding to the static pattern according to the first option information or perform adaptive charge sharing corresponding to the dynamic pattern according to the second option information.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 23, 2020
    Assignee: Silicon Works Co., Ltd.
    Inventors: Nam Seok Seo, Young Kwang Kim, Young Bok Kim, Hyun Mo Yang, Hae Won Lee, Ju Ho Lee
  • Patent number: 10677817
    Abstract: A method for oscilloscope 3D mapping in scan mode. The input signal is acquired using a real-time sampling rate which is Dr times higher, thus more sampling points, i.e. Dr acquired data can be obtained during the time interval between two consecutive horizontal pixels. The Dr acquired data are mapped into a same column of the screen to implement fluorescent waveform display. In addition, to realize the scanning display, a flag X is introduced into the three-dimensional database, when the screen refresh signal arrives, the first Ds acquired data are read out from the unread acquired data in FIFO memory. The three-dimensional database is updated from the flag X, which make the leftmost waveform always be the oldest waveform, the rightmost waveform always be the newest waveform. Thus the 3D mapping is realized in scan mode, letting the DSO have a fluorescent waveform display at slow time-base.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 9, 2020
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Kuojun Yang, Wuhuang Huang, Peng Ye, Qinchuan Zhang, Hao Zeng, Duyu Qiu, Jun Jiang, Huiqing Pan, Lianping Guo, Feng Tan
  • Patent number: 10672175
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Devan Burke, Adam T. Lake, Jeffery S. Boles, John H. Feit, Karthik Vaidyanathan, Abhishek R. Appu, Joydeep Ray, Subramaniam Maiyuran, Altug Koker, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Eric J. Hoekstra, Gabor Liktor, Jonathan Kennedy, Slawomir Grajewski, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 10665142
    Abstract: A screen calibration method includes acquiring a full screen image displayed on a screen by a camera, acquiring first optical data of a first region of the screen by a sensor, adjusting the first optical data of the first region of the screen according to first calibration parameters for calibrating colors of the first region to approach target optical data, generating second optical data of a second region of the screen according to the full screen image and the first optical data of the first region, generating second calibration parameters according to the target optical data and the second optical data, and adjusting the second optical data of the second region of the screen according to the second calibration parameters for calibrating colors of the second region to approach the target optical data.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 26, 2020
    Assignee: BenQ Corporation
    Inventors: Hsin-Nan Lin, Chung-Yu Huang
  • Patent number: 10659783
    Abstract: Approaches to robust encoding and decoding of escape-coded pixels in a palette mode are described. For example, sample values of escape-coded pixels in palette mode are encoded/decoded using a binarization process that depends on a constant value of quantization parameter (“QP”) for the sample values. Or, as another example, sample values of escape-coded pixels in palette mode are encoded/decoded using a binarization process that depends on sample depth for the sample values. Or, as still another example, sample values of escape-coded pixels in palette mode are encoded/decoding using a binarization process that depends on some other fixed rule. In example implementations, these approaches avoid dependencies on unit-level QP values when parsing the sample values of escape-coded pixels, which can make encoding/decoding more robust to data loss.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: May 19, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bin Li, Jizheng Xu
  • Patent number: 10650485
    Abstract: An electronic apparatus includes a locking unit to selectively lock a physical connection with an external apparatus and a control unit to control an operation mode of the electronic apparatus, according to a connection state with the external apparatus, in which the control unit controls the locking unit to lock the connection with the external apparatus, when the electronic apparatus is in an operation mode of using a graphic processing unit of the external apparatus.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ja-goun Koo
  • Patent number: 10650484
    Abstract: Methods, systems, and computer-readable media for dynamic and application-specific virtualized graphics processing are disclosed. Execution of an application is initiated on a virtual compute instance. The virtual compute instance is implemented using a server. One or more graphics processing unit (GPU) requirements associated with the execution of the application are determined. A physical GPU resource is selected from a pool of available physical GPU resources based at least in part on the one or more GPU requirements. A virtual GPU is attached to the virtual compute instance based at least in part on initiation of the execution of the application. The virtual GPU is implemented using the physical GPU resource selected from the pool and accessible to the server over a network.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: May 12, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Malcolm Featonby, Yuxuan Liu, Umesh Chandani, John Merrill Phillips, Jr., Nicholas Patrick Wilt, Adithya Bhat, Douglas Cotton Kurtz, Mihir Sadruddin Surani
  • Patent number: 10649700
    Abstract: An image generation-output control apparatus for controlling an image generation and output operation based on an instruction received from a server in an image processing system. The server includes a first memory to store first image processing data applicable to an image processing for outputting a target image, first circuitry to generate first image drawing information based on output target image information and the first image processing data when performing an image forming operation. The image generation-output control apparatus includes second circuitry, having one or more capabilities compatible with one or more capabilities of the first circuitry of the server. The second circuitry generates second image drawing information based on the output target image information and the first image processing data acquired from the server, and instructs an image forming apparatus to perform an image forming operation based on the generated second image drawing information.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: May 12, 2020
    Assignee: RICOH COMPANY, LTD.
    Inventor: Takuya Yamakawa
  • Patent number: 10643525
    Abstract: Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Vishal Sinha, Paul Diefenbaugh, Todd Witter, Jason Tanner, Arthur Runyan, Nausheen Ansari, Kathy Bui, Yifan Li
  • Patent number: 10628910
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Tomasz Bujewski, Radoslaw Drabinski, Subramaniam Maiyuran, Jorge Garcia Pabon, Raghavendra Miyar, Rajarshi Bajpayee
  • Patent number: 10628907
    Abstract: Systems, apparatuses, and methods may provide for technology to process multi-resolution images by identifying pixels at a boundary between pixels of different resolutions, and selectively smoothing the identified pixels.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski
  • Patent number: 10628911
    Abstract: A graphics processing unit (GPU) is provided. The GPU includes a command stream parser (CSP) including a profiling unit used to provide performance statistics data for the GPU to determine a rendering mode of the GPU, wherein the rendering mode includes a first rendering mode and a second rendering mode for performing a graphics rendering pipeline for graphics processing. The profiling unit calculates drawing time of frames and the number of objects in the frames when the GPU operates in the first rendering mode, and determines whether the operation of the GPU is switched to the second rendering mode according to the calculated drawing time and the number of objects; when determining that the calculated drawing time and the number of objects are less than their respective thresholds, the CSP causes the operation of the GPU to switch from the first rendering mode to the second rendering mode.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 21, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Ying Wang, Fengxia Wu, Deming Gu, Yi Zhou, Jiakuan Hu
  • Patent number: 10629045
    Abstract: Techniques are described for distributing, to a distributed network of central stations, alarm events detected in monitoring system data collected by sensors included in monitoring systems located at monitored properties. A system receives monitoring system data collected by sensors included in monitoring systems located at monitored properties, tracks alarm events detected within the monitoring system data, and generates, for central station servers in a distributed network of central stations, load profiles that reflect a volume of alarm events being handled at each of the central station servers at a particular period of time. The system determines capacities to handle additional alarm events for the central station servers, determines relative priorities for the central station remote servers based on the determined capacities, and directs subsequent alarm events to the central station servers based on the relative priorities.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: April 21, 2020
    Assignee: Alarm.com Incorporated
    Inventor: Stephen Scott Trundle
  • Patent number: 10614610
    Abstract: A texture filtering unit includes a datapath block and a control block. The datapath block includes one or more parallel computation pipelines, each containing at least one hardware logic component configured to receive a plurality of inputs and generate an output value as part of a texture filtering operation. The control block includes a plurality of sequencers and an arbiter. Each sequencer executes a micro-program that defines a sequence of operations to be performed by the one or more pipelines in the datapath block as part of a texture filtering operation and the arbiter controls access, by the sequencers, to the one or more pipelines in the datapath based on predefined prioritization rules.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 7, 2020
    Assignee: Imagination Technolgies Limited
    Inventor: Casper Van Benthem
  • Patent number: 10607400
    Abstract: A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. Vertex shading circuitry then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further, to generate, inter alia, a single vertex shaded attribute value for the set of plural views.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 31, 2020
    Assignee: Arm Limited
    Inventors: Sandeep Kakarlapudi, Jorn Nystad, Andreas Due-Engh Halstvedt
  • Patent number: 10607576
    Abstract: To achieve prompt display of image data to be displayed as well as seamless display of consecutive image data, a host (10) of a display device (1) includes an image generation section (11) configured to generate image data and an image transferring section (12) configured to transfer the image data to a display control section. The image generation section is configured to: start generating, in a case where generation of image data was completed within less than a single unit period, image data for a subsequent frame after the single unit period has passed since the generation of the image data; and start generating, in a case where the generation of the image data was not completed within less than the single unit period, image data for a subsequent frame any time after completion of the generation of the image data.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 31, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Takuya Okamoto
  • Patent number: 10600229
    Abstract: In various embodiments, a parallel processor implements a graphics processing pipeline that generates rendered images via a shading program. In operation, the parallel processor causes a first set of execution threads to execute the shading program on a first portion of the input mesh to generate first geometry stored in an on-chip memory. The parallel processor also causes a second set of execution threads to execute the mesh shading program on a second portion of the input mesh to generate second geometry stored in the on-chip memory. Subsequently, the parallel processor reads the first geometry and the second geometry from the on-chip memory, and performs operations on the first geometry and the second geometry to generate a rendered image derived from the input mesh. Advantageously, unlike conventional graphics processing pipelines, the performance of the graphics processing pipeline is not limited by a primitive distributor.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: March 24, 2020
    Assignee: NVIDIA Corporation
    Inventors: Ziyad Hakura, Yury Uralsky, Christoph Kubisch, Pierre Boudier, Henry Moreton
  • Patent number: 10593017
    Abstract: An information processing apparatus, connectable with an image output apparatus, includes circuitry to receive image data of an image from a memory, acquire information of an image placement region of the image output apparatus, the image placement region being variable depending on a type of the image output apparatus, and the image is to be output on the image placement region of the image output apparatus, generate an output image by placing the image within the image placement region based on the image data of the image to be output, and the image placement region of the image output apparatus, and transmit the generated output image to the image output apparatus.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: March 17, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Tomoyuki Takahira, Akio Ishida
  • Patent number: 10586303
    Abstract: Technologies related to intermediary graphics rendition are generally described. In some examples, an intermediary computing device may store graphics models in a model store. A server computing device may generate and send a compositing flow to the intermediary computing device. The compositing flow may comprise model identifiers and model rendering information. The intermediary computing device may retrieve models identified in the compositing flow from the model store, and provide the identified models and model rendering information to a Graphics Processing Unit (GPU) for rendering. The GPU may render graphics for delivery via a network to a client device.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: March 10, 2020
    Assignee: Empire Technology Development LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 10579388
    Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 3, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Scott Hartog, Mark Leather, Michael Mantor, Rex McCrary, Sebastien Nussbaum, Philip J. Rogers, Ralph Clay Taylor, Thomas Woller
  • Patent number: 10580200
    Abstract: An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Brent E. Insko, Prasoonkumar Surti
  • Patent number: 10578868
    Abstract: The present invention discloses a head-mounted display and a video data processing method thereof. The head-mounted display comprises: a video input module, a distortion processing module and a video output module. The head-mounted display divides each image frame in a video into a plurality of image blocks of symmetry according to a graphic correspondence of a distorted image after a distortion processing, performs a distortion processing of any one of the image blocks, and obtains data of the current image frame after the distortion processing according to the graphic correspondence.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: March 3, 2020
    Assignee: BEIJING PICO TECHNOLOGY CO., LTD.
    Inventors: Wen hui Zhao, Jin bo Ma, Chuan guo Fan, Chong Wang
  • Patent number: 10571993
    Abstract: A microcontroller unit includes: a first arithmetic processing unit, which is able to access a data bus; a second arithmetic processing unit, which includes a processor capable of accessing the data bus, and a memory. The microcontroller unit performs a data transmitting process between peripheral circuits connected to the data bus; a first arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the data bus; and a second arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the memory. The memory stores arithmetic processing sequences in association with event signals transmitted from the peripheral circuits, and in response to input of the event signals, the processor executes the arithmetic processing sequences corresponding to the event signals.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: February 25, 2020
    Assignee: Sanken Electric Co., LTD.
    Inventors: Takanaga Yamazaki, Kazuhiro Mima