Abstract: This communication device has a phase-modulation spatial light modulator; and a control unit which causes, during one frame time interval, the phase-modulation spatial light modulator to operate with first and second operation patterns. In a predetermined period within the one frame time interval, the first operation pattern includes a first light transmittable interval during which first signal light can be output, and a first pause interval during which the first signal light cannot be output whereas the second operation pattern includes a second light transmittable interval during which second signal light can be output, and a second pause interval during which the second signal light cannot be output. The first and second light transmittable intervals are each longer than a half of the predetermined period. The second pause interval is present within the first light transmittable interval, and the first pause interval is present within the second light transmittable interval.

Abstract: Control information for controlling a method of using data is generated by a reception side, the data being wirelessly transmitted and received by the reception side, and the control information is added to data to generate data-with-control-information. A method of using data is controlled on the basis of control information included in data-with-control-information for controlling the method of using data, the data-with-control-information being acquired by adding the control information to data, the data-with-control-information being wirelessly transmitted, and data whose use method is controlled is output on the basis of the control information.

Abstract: Systems, methods and/or devices are used to enable using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of I/O requests to access data of size less than a predefined small-size threshold during a predetermined time period, (b) determining whether the region has a history of sequential write requests during the predetermined time period, and (c) if both determinations are true, coalescing subsequent write requests to the region.

Abstract: Provided are systems and methods for displaying web content. An example method includes receiving web content comprising an area to be displayed, segmenting the area into tile areas, generating raw tiles corresponding to the tile areas, storing the raw tiles in a first memory space allocated for storing raw tiles, encoding the raw tiles to generate encoded tiles corresponding to the tile areas, storing the encoded tiles in a second memory space allocated for storing encoded tiles, releasing the portion of the memory space storing the raw tiles, combining two or more of the encoded tiles to generate combined tiles, storing the combined tiles in a third memory space allocated for storing combined tiles, releasing the portion of the second memory space storing the encoded tiles, combining two or more of the combined tiles to generate an image, storing the image in a fourth memory space, and releasing the portion of the third memory space storing the combined tiles.

Abstract: Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.

Abstract: Systems, computer readable media, and methods for hardware accelerated blits of multisampled textures on graphics processing units (GPUs) are disclosed. For multisampled surfaces, texture-to-buffer blits cannot be trivially implemented because most GPUs do not support writing multisampled surfaces with a linear memory layout. Moreover, GPUs often have a maximum limit for row stride (i.e., the number of bytes from one row of pixels in memory to the next) and/or texture size. When the destination buffer for the blit of a multisampled texture is too large to be aliased by an equivalent non-multisampled texture view, the stride of the view has no spatial relationship with the destination buffer. Thus, to access the source texture correctly, a ‘remapping’ may be performed to determine the linear sample index of a fragment within the view, and the destination buffer stride may be used to compute the texture coordinates used to sample the source texture.

Abstract: Provided is a data processing apparatus of an organic light emitting display device, which performs encoding and decoding through different schemes according to frequency components and data components, thereby preventing loss of a high frequency component included in data.

Abstract: In a method for storing packets in a network device, a processor and a plurality of memory banks for storing packet data during processing of packets by the processor are provided on an integrated circuit device. Each memory bank has a separate channel for transferring data. A plurality of buffers are defined such that each buffer in the plurality of buffers includes a respective memory space in more than one memory bank and less than all memory banks. A buffer of the plurality of buffers is allocated for storing a single packet or a portion of a single packet. The single packet or the portion of the single packet in the allocated buffer.

Abstract: Systems and methods for adaptive compression mode selection for memory buffers such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD a first compression mode is selected for a buffer and the buffer is formatted to the first compression mode. Any access to the buffer by a component of the PCD, core of the PCD or software application running on the PCD is monitored. Based on the amount and/or type of access to the buffer, a second compression mode for the buffer is selected. The buffer is formatted to the second compression mode, providing a cost effective ability to adaptively format buffers based on the component(s), cores(s), and/or software application(s) accessing the buffers, and allowing for improving or optimizing bandwidth, memory footprint, resource conflict, power consumption, latency, and/or performance of component(s), core(s), or software application(s) accessing buffers as desired.

Abstract: An electronic apparatus includes a graphic processor to generate each of a plurality of images as a different signal, an incorporation unit to incorporate the plurality of generated images into one image, and a display to display the incorporated image.

Abstract: A multi-display apparatus includes a first body mounted with a first display, a second body mounted with a second display, a hinge connecting the first body and the second body, a first frame buffer corresponding to a first display, a second frame buffer corresponding to a second display, and a controller which manages the first and second frame buffers with a separate storing method which separately manages the first and second frame buffers and stores data or a united storing method which manages the first and second frame buffers as one virtual united frame buffer and stores data. The controller stores data on the first and second frame buffers by converting the managing method according to data features displayed on the first and second displays, and the first and second displays display the data stored in the first and second frame buffers respectively.

Abstract: A system for raster to block conversion in a compressed domain may include a raster to block encoder, a raster to block decoder, and a memory partitioned into a number of memory stripes having widths of a number of bits. The raster to block encoder may be configured to receive image information associated with pixels of an image in raster order, compress the image information associated with the pixels of the image to generate compressed bits that correspond to at least one of memory stripes, and write the compressed bits to the at least one of the memory stripes. The raster to block decoder may be configured to read, from at least one of the memory stripes of the memory, a number of the compressed bits that correspond to at least one block, and decode the number of the compressed bits to generate the at least one block.

Abstract: Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

Abstract: A method includes calculating a Fourier transform of an image, extracting a plurality of arrays, from the Fourier transform utilizing, for each of the plurality of arrays, one of a plurality of templates each of said templates corresponding to a texture orientation, calculating a maximum value for each of the plurality of arrays, identifying each of the plurality of arrays having a calculated maximum value greater than a predetermined threshold and determining, for each of the plurality of identified arrays, the texture orientation of the template utilized to extract the identified one of the plurality of arrays.

Abstract: A data array 20 to be stored is first divided into a plurality of blocks 21. Each block 21 is further sub-divided into a set of sub-blocks 22, and a set of data for each sub-block 22 is then stored in a body data buffer 30. A header data block 23 is stored for each block 21 at a predictable memory address within a header buffer 24. Each header data block contains pointer data indicating the position within the body buffer 30 where the data for the sub-blocks for the block 21 that that header data block 23 relates to is stored, and data indicating the size of the stored data for each respective sub-block 22.

Abstract: An image signal processor includes a buffer and a buffer controller configured to divide the buffer into a plurality of slots. The buffer controller is configured to store image data necessary for image distortion correction to the buffer. The buffer controller is configured to not store image data unnecessary for image distortion correction to the buffer.

Abstract: A device, system and method are provided for managing memory for rendering webpages and other structured documents that contain multiple regions. A backing store is created in memory for storing rendered document content. A main region of the structured document is rendered for display, divided into a set of tiles, and stored in the backing store. A subregion of the document is rendered and stored as tiles in the same backing store as well. At least a portion of the tiles for the main region and subregion intersecting with corresponding viewports are outputted to a display. When an active one of the viewports is changed and additional content of the document is to be rendered for display, tiles in the backing store used to store rendered but undisplayed data for the inactive viewport are released to store new rendered content for the active viewport.

Abstract: When a display target determination unit determines image data to be displayed, a reproduction control unit identifies the type of the image data to be displayed. The reproduction control unit divides the region of a display buffer according to the identified type. While an image display control unit displays an image, on a display device, by using image data stored in a spare buffer, a decoding execution unit decodes said image data and stores the decoded image data in a divided region of the display buffer.

Abstract: A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes receiving vertex data for a primitive to be rendered; generating pixel data in response to the vertex data; determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions; and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines.

Abstract: Sequential write operations to a unit of compressed memory, known as a compression tile, are examined to see if the same compression tile is being written. If the same compression tile is being written, the sequential write operations are coalesced into a single write operation and the entire compression tile is overwritten with the new data. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.

Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Abstract: A non-buffered video line memory eliminates the need for double buffering video data during processing. While most double buffering systems double the amount of memory necessary to store video data, a non-buffered approach reduces the hardware memory costs substantially. A set of write and read pointers coupled with write and read incrementors allows data to be stored in raster order and removed in block order from a non-buffered memory device. The incrementors, in conjunction with a set of write and read pointers generate a base address for data to be written to and read from the non-buffered memory at substantially the same time. Encoding systems benefit substantially by being able to read and write information into a common memory rather than continuously switching between two different memories, by reducing complexity and cost.

Abstract: Provided are a mapping method and a video system for mapping pixel data included in the same pixel group to the same bank of a memory, A method for mapping the position of pixel data of a picture to an address of a memory comprises a pixel group dividing operation and an address mapping operation. The pixel group dividing operation divides the pixels of the picture into at least one pixel group. The address mapping operation maps pixel data of pixels included in the same pixel group to the same bank of the memory.

Abstract: An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.

Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.

Abstract: A method and apparatus for sorting data into spatial bins or buckets using a graphics processing unit (GPU). The method takes unsorted point data as input and scatters the points, in sorted order, into a set of bins. This key operation enables construction of a spatial data structure that is useful for applications such as particle simulation or collision detection. The disclosed method achieves better performance scaling than previous methods by exploiting geometry shaders to progressively trim the size of a working set. The method also leverages predicated rendering functionality to allow early termination without CPU/GPU synchronization. Furthermore, unlike previous techniques, the method can guarantee sorted output without requiring sorted input. This allows the method to be used to implement a form of bucket sort using the GPU.

Abstract: An image processing system includes a memory, a data slicer and an image processor. The data slicer divides each of current image data and adjacent image data into a first portion and a second portion to be stored into the memory. The image processor reads from the memory the first portion and the second portion of the current image data and the first portion of the adjacent image data for image processing.

Abstract: A graphic processing apparatus includes a chunk assignment unit which assigns a block in which a maximum N number of polygons are located, out of a plurality of polygons drawn in a frame buffer which is divided into a plurality of blocks, to a maximum M number of chunk buffers; a chunk generation unit which generates pixel data of a polygon located in a block assigned to the chunk buffer, out of the N number of polygons, and writes the pixel data to the chunk buffer; and a chunk writing unit which writes the pixel data written in the chunk buffer to the frame buffer, wherein a processing phase, including processing by the chunk assignment unit, processing by the chunk generation unit, and processing by the chunk writing unit, is repeatedly executed for the plurality of polygons.

Abstract: Systems, methods and computer-readable storage media are disclosed for accelerating bitmap remoting by extracting non-grid tiles from source bitmaps. A server takes a source image, identifies possibly repetitive features, and tiles the image. For each tile that contains part of a possibly repetitive feature, the server replaces that part with the dominant color of the tile. The system then sends to a client a combination of new tiles and features, and indications to tiles and features that the client has previously received and stored, along with an indication of how to recreate the image based on the tiles and features.

Abstract: The present invention relates to a display device for a glass cockpit of an aircraft, intended to provide video streams to a plurality of viewing screens of said glass cockpit, said aircraft being partitioned into a secured area, a so-called avionic world (AW), and a non-secured area, a so-called open world (OW), said system comprising at least one first port intended to receive first data to be displayed from a system (210, 310, 410) belonging to the avionic area and at least one second port intended to receive second data to be displayed from a system (220, 320, 420) belonging to the open world, the display device comprising: predetermined hardware resources allocated to the processing of the second data; a processor (241, 341, 441), belonging to the avionic area, adapted to controlling the hardware resources used by said processing and interrupting this processing if said hardware resources used exceed said allocated resources.

Abstract: A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.

Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.

Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.

Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Abstract: For improving the brightness decay of a display due to its aging, a non-volatile memory such as Flash can be used to store a brightness accumulation value of each point of the display, and each point can be compensated for its brightness accordingly. However, the non-volatile memory suffers from incorrect write-in data or temporary power disconnection, and thus the error will exist all the time to make the display non-even. Hence, the present invention uses a multiple data backups and CRC error detection, plus new/old data comparison to protect data the non-volatile memory from incorrect brightness compensation value so as to uniform the brightness of the display.

Abstract: An apparatus that communicates with a screen display apparatus: a generation unit configured to generate image data to be displayed on a screen; an identification unit configured to identify an overlapping area that overlaps with the image data for each of a plurality of divided areas into which the screen is divided, respectively; a division unit configured to divide respective partial image data belonging to the respective overlapping areas in a vertical direction or a horizontal direction of the screen; a data compression processor configured to compress respective divided image data belonging to the respective divided areas by using dictionary data obtained based on a predetermined amount of divided image data compressed in the past belonging to the respective divided areas; and a data transmission unit configured to transmit respective compressed image data belonging to the respective divided areas in an order defined according to a rule given in advance.

Abstract: A user can share (show) multimedia information while simultaneously communicating (telling) with one or more other users over a network. Multimedia information is received from at least one source. The multimedia information may be manually and/or automatically annotated and shared with other users. The multimedia information may be displayed in an integrated live view simultaneously with other modes of communication, such as video, voice, or text. A simultaneous sharing communication interface provides an immersive experience that lets a user communicate via text, voice, video, sounds, music, or the like, with one or more other users while also simultaneously sharing media such as photos, videos, movies, images, graphics, illustrations, animations, presentations, narratives, music, sounds, applications, files, and the like. The simultaneous sharing interface enables a user to experience a higher level of intimacy in their communication with others over a network.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: A method of controlling micromirrors of reset groups of a spatial light modulator (SLM) digital micromirror array is disclosed. In a first reset operation, the positions of a first subgroup of micromirrors of a reset group are set based on a first portion of a first bitplane and the positions of a second subgroup of micromirrors of the same reset group are set based on a first portion of a second bitplane. Then, in a second reset operation, the positions of the first subgroup are set based on a second portion of the second bitplane and the positions of the second subgroup are set based on a second portion of a first bitplane. In one example, subsets of alternating rows of micromirrors of the same reset group are successively set according to alternating data corresponding to different ones of first and second bitplanes.

Abstract: A method for storing information may include determining whether a received data object fits inside a particular one of a plurality of free blocks in a memory bitmap. Each of the plurality of free blocks may include a column of the memory bitmap with a top margin, a bottom margin, and a predetermined width. If the received data object fits, the received data object may be stored in the particular one of the plurality of free blocks, starting at the top margin of the particular one of the plurality of free blocks. The particular one of the plurality of data blocks may be resized by moving the top margin to start below the stored received data object. The determining may include, for each of the plurality of free blocks, a height of the received data object may be compared with a height of each of the free data blocks.

Abstract: A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: A system for compressed data transfer across a graphics bus in a computer system. The system includes a bridge, a system memory coupled to the bridge, and a graphics bus coupled to the bridge. A graphics processor is coupled to the graphics bus. The graphics processor is configured to compress graphics data and transfer compressed graphics data across the graphics bus to the bridge for subsequent storage in the system memory.

Abstract: A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: The present invention provides a digital TV. The digital TV comprises a memory, a signal processing module, and a processor. The memory is for storing a regular program code. The signal processing module is for receiving and processing a data signal, and for generating an interruption signal. The processor coupled to the memory and the signal processing module is for receiving the interruption signal and reading the regular program code from the memory, and for executing the regular program code to realize functions of the digital TV. The memory is divided into a plurality of blocks, and the processor accesses the memory by block. Each block includes a first sub-block storing a specific program code. When the processor receives the interruption signal, the processor reads the specific program code of the first sub-block of the currently-accessed block and executes the specific program code.

Abstract: For improving the drawback of brightness decay of a display due to aging, a memory can be used to store the usage time of each pixel of the display, then based upon the usage time the brightness decay of each pixel of the display can be compensated and accordingly the value for the compensation can be stored in a volatile memory and a non-volatile memory. However, the usage of the non-volatile memory is limited. Hence, the present invention discloses a new approach for storing the data so as to decrease write-in sequence per unit area for the non-volatile memory rather than increasing its storing capacity proportionally.