Abstract: A method and apparatus for managing texture mapping data in a computer graphics system, the computer graphics system including a host computer, primitive rendering hardware and a primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes primitives to be rendered by the system to the primitive rendering hardware over the primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the primitives to be rendered. When a primitive passed to the primitive rendering hardware is to be rendered, a determination is made as to whether its corresponding texture mapping data is in the local texture memory.

Abstract: A method and apparatus for managing blocks of data in a data processing system, the data processing system including a host computer and data processing hardware, the host computer having a main memory that stores blocks of data to be processed by the data processing hardware, the data processing hardware including a local memory that locally stores a subset of the blocks of data to be processed by the data processing hardware. When a portion of one of the blocks of data is to be processed by the data processing hardware, a determination is made as to whether the block of data is in the local memory. When the block of data is in the local memory, the portion of the block of data to be processed is read from the local memory. When the block of data is not in the local memory, it is downloaded from the host computer main memory to the data processing hardware. The data processing hardware may generate an interrupt to the host computer with a request to download data.

Abstract: A method and apparatus are disclosed for achieving improved mipmapped texture mapping performance in computer graphics systems. Page residence indicators obviate the need for address comparisons during texel accessing. A mipmap page number is generated for texture data of interest. A page residence bit is then selected responsive to the mipmap page number. If the page residence bit is in a first state, then the texture data is retrieved from a memory located within the graphics subsystem; but if the page residence bit is in a second state, then the texture data is retrieved from system memory. System-wide texture offset addressing obviates the constraints associated with fixed relative addressing schemes.

Abstract: An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.

Abstract: A circuit arrangement (40) and display apparatus are described for use in 3-D graphics, where 2-D texture maps stored at different resolutions in a pyramidal array are indexed by a pair of texture coordinates and an associated level coordinate (L). In order to introduce depth cues to the 2-D transformed image of the 3-D environment, a focus depth (F) for the image is specified and those image components having a depth (z) other than the focus depth have their texture blurred to direct the viewer's eye to the depth of interest. The texture blurring is introduced by applying an offset (FS) to the level coordinate (L) indexing the pyramidal array in an amount determined by the distance to the focus depth.

Abstract: The invention provides for cache organization of texture information and a method and apparatus for accessing cached texture information and an index for cached information. Texels are represented in two dimensions and stored in groups referred to as tiles. Cache is configured to contain multiple tiles of texture image data, each tile being stored as a line in the cache. A cache line can be multidimensional (e.g., two or three or more dimensions) and may be viewed as an identifiable storage element in the cache. Memory may consist of a plurality of cache lines. Direct mapped cache may be utilized wherein each DRAM location maps to a single cache line. A tag table contains the tag information for all tiles currently stored in cache. A portion of the texel information may be utilized as an index assigned to a specific cache line. Another portion of the tag information identifies the tile currently stored in cache.

Abstract: A method of providing text data for display in a processor controlled apparatus comprised of storing data defining a text character in a memory, in packed monochrome bit map form, addressing the memory to read the text character data, providing the text character to a graphics processor circuit, performing a bitblt operation on each bit of the text character while providing a color attribute, and storing the packed text character having a color attribute for subsequent display.

Abstract: Texture coordinates and LOD (Level of Detail) values are computed on a pixel-by-pixel basis from object data, and based on the texture coordinates and LOD values, a filtering domain of texels read from a texture memory is determined, and a weighted average is acquired depending on the size of the determined filtering domain, to create the texture color to be adhered to the polygon.

Abstract: A bump image for a three-dimensional model of an object is stored and modified as well as a texture image in a rendering stage. A reverse mapping address to the texture image and the bump image is stored in a rendering memory to obtain a drawing object address for the texture image according to the address in the rendering memory.

Abstract: A graphic pattern processing apparatus using a raster scan type CRT is disclosed. The graphic pattern processing apparatus can update one-pixel data, translate a logical address to physical address and transfer data in a display memory, at a high speed.

Abstract: A process and implementing computer system for graphics applications in which information files such as texture maps (TMs) are prioritized and stored in a local relatively fast RDRAM memory. The method of prioritization includes initially sorting the information files by order of the frequency with which corresponding graphics primitive elements are called by the application. The priority is adjusted such that the smaller TMs get an increase in their priority so that more TMs may be placed in faster graphics memory. Thereafter among similarly prioritized groups of information files, the larger of the files are first stored in the fast graphics memory and the remaining files are marked for storage in the system memory after the fast local memory has been fully utilized.

Abstract: A process and implementing computer system for graphics applications in which information files such as texture maps (TMs) are prioritized and stored in a local relatively fast RDRAM memory. The method of prioritization includes initially sorting the information files by order of the frequency with which corresponding graphics primitive elements are called by the application. The priority is adjusted such that the smaller TMs get an increase in their priority so that more TMs may be placed in faster graphics memory. Thereafter among similarly prioritized groups of information files, the larger of the files are first stored in the fast graphics memory and the remaining files are marked for storage in the system memory after the fast local memory has been fully utilized.

Abstract: A three dimensional image is textured for display on a screen by firstly receiving data comprising the location of each elementary area (pixel) of the screen and associated image data for that pixel. Texture image data is retrieved from a memory means in dependence on the image data and an appropriate portion of that texture image data is mapped onto the pixel. The number of pixels which share the same associated image data is determined and an incremental change in the mapping of the texture data onto pixels corresponding to a one pixel increment is also determined. For each pixel sharing the same image data as an adjacent pixel the previously derived texture image data for that adjacent pixel is combined with the incremental change in texture image data to thereby derive texture image data for that pixel.

Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Abstract: A method of a computer graphics system recirculates texture cache misses into a graphics pipeline without stalling the graphics pipeline, increasing the processing speed of the computer graphics system. The method reads data from a texture cache memory by a read request placed in the graphics pipeline sequence, then reads the data from the texture cache memory if the data is stored in the texture cache memory and places the data in the pipeline sequence. If the data is not stored in the texture cache memory, the method recirculates the read request in the pipeline sequence by indicating in the pipeline sequence that the data is not stored in the texture cache memory, placing the read request at a subsequent, determined place in the pipeline sequence, reading the data into the texture cache memory from a main memory, and executing the read request from the subsequent, determined place and after the data has been read into the texture cache memory.

Abstract: A method and apparatus for blending textures and other operands in a video graphics system using a single blend unit is accomplished through the following steps. A first set of control information is received. A first portion of the first set of control information is sued to select a first blend operand, which is preferably a texture in a graphics processing system. A second blend operand is selected based on a second portion of the first set of control information. The first and second blend operands are combined using an operation selected by a third portion of the first set of control information. The combination of the first and second blend operands produces a first combination result. A second set of control information is received, and a first portion of the second set of control information selects a third blend operand. The first combination result is then selected as a fourth blend operand using a second portion of the second set of control information.

Abstract: A method for storing mip map series in a multi-bank texture memory is disclosed. Each mip map has a different size and represents a different resolution version of a texture map image that is to be mapped onto a three dimensional object comprising one or more polygons. To prevent page faults when accessing corresponding texels in consecutive mip maps, each mip map is divided in two halves. The halves are stored in different banks of the multi-bank texture memory. The banks used are alternated so that corresponding texels in consecutive mip maps are stored in different memory banks. Mip maps may be categorized as large or small, with all small mip maps after the first being stored in their entirety in one memory bank. Small mip maps are those that are equal to or smaller than the page size of the multi-bank texture memory. A computer system, graphics subsystem, and software program capable to efficiently store mip map series in a multi-bank texture memories are also disclosed.