Abstract: A precharge method for a data driver includes steps of: outputting a display data to a plurality of output terminals of the data driver; outputting a second precharge voltage to an output terminal among the plurality of output terminals prior to outputting the display data to the output terminal, to precharge the output terminal to a voltage level closer to an output voltage; and outputting a first precharge voltage to the output terminal prior to outputting the second precharge voltage. The first precharge voltage provides a faster voltage transition on the output terminal than the second precharge voltage.

Abstract: The disclosure discloses a reconfigurable hardware acceleration method and system for Gaussian pyramid construction and belongs to the field of hardware accelerator design. The system provided by the disclosure includes a static random access memory (SRAM) bank, a first in first out (FIFO) group, a switch network, a shift register array, an adder tree module, a demultiplexer, a reconfigurable PE array, and a Gaussian difference module. In the disclosure, according to the requirements of different scenarios and different tasks for the system, reconfigurable PE array resources can be configured to realize convolution calculations of different scales. The disclosure includes methods of fast and slow dual clock domain design, dynamic edge padding design, and input image partial sum reusing design.

Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Abstract: An information processing apparatus includes a drawing resource acquisition unit that segments a common drawing resource in a first memory into drawing resource segments, successively acquires the drawing resource segments from the first memory, and stores the drawing resource segments in a second memory, a drawing data generating unit that generates the drawing data in a format supported by an image forming apparatus, using the drawing resource segments stored in the second memory, and a memory area releasing unit that releases part or whole of a memory area of one drawing resource segment, after the drawing data generating unit has generated the drawing data using the one drawing resource segment and before the drawing resource acquisition unit stores in the second memory another drawing resource segment acquired subsequent to the one drawing resource segment.

Abstract: A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

Abstract: A serial interface includes a select node, a clock node, a first bidirectional data port, a second bidirectional data port, and shift register circuitry coupled to both data ports such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift or transfer data.

Abstract: A video game device calculates a difference vector extending from a predetermined reference position on the screen to an input position. Moreover, the video game device calculates movement parameter data used for moving, with respect to a fixed point in the virtual space uniquely determined based on a position of the controlled object, the point of sight to a position that is determined by a direction in the virtual space based on a direction of the difference vector and a distance in the virtual space based on a magnitude of the difference vector. The point of sight is moved based on the movement parameter data. The video game device produces an image based on a virtual camera, which has been moved according to the movement of the point of sight, and displays the image on the screen of a display device.

Abstract: A programmable controller for homes and/or buildings and their related grounds, such as thermostat, that has a display and an external interface. The external interface may be use for uploading electronic images and/or other information from an external data source, and may use the uploaded electronic images and/or other information for programming and/or updating the controller and/or for viewing the electronic images and/or other information on the display of the controller.

Abstract: A device is provided for use in a portable computer. The device includes a wireless graphics card that includes a connector for coupling to an expansion slot of the portable computer and for receiving a plurality of signals from the portable computer, the plurality of signals including video, audio, and data signals and an ultra wideband (UWB) chipset coupled to the connector for processing the plurality of signals and for generating an OFDM modulated signal that includes at least the video signal, where the OFDM modulated signal including the video signal is wirelessly transmitted over an UWB link to a monitor for display.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: In systems and methods for graphic reproduction of an image including textural information, multiple rows or blocks of texture data can be retrieved from system memory in response to the single read command. In this manner, efficient use of system bus is achieved, and an increase in the texture cache hit ratio is realized, leading to more efficient system operation, and reduced system bus usage for texture data retrieval.

Abstract: A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a read address generation unit and addresses input from an external bus, the address which is supplied to a local memory (LM) is selected in accordance with configuration information supplied by a configuration information storage unit. Addresses correspond to ports. Lower bits thereof instruct the storage region inside the LM, and upper bits instruct the LM to be accessed. The read data to be output to a port is selected from among the read data of a plurality of LMs in accordance with the upper bits of this address.

Abstract: An exemplary method detects an update to data representing a portion of a render target, according to one embodiment of the invention. Also, this method forms a copy of the portion configured to be overwritten with data for a subsequent update when that portion of the render target is selected to receive subsequent updates. Lastly, the data representing the portion can be designated as texture.

Abstract: A priority control device comprises a clock generator for generating a clock signal, a time interval generating unit having a plurality of signal routes and each of the signal routes has a different signal passing time respectively, and a logic control unit coupled to the outputs of the signal routes. The time interval generating unit determines the timing of receiving input signals according to the clock signal. The logic control unit receives the output signals of the signal routes for generating the control signals.

Abstract: An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.

Abstract: An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or more different types of processors. The scheduler schedules operations on the different types of processors.

Abstract: An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises an integral bounded video signature analyzer, a hardware cursor apparatus supporting dual scanned displays, programmatic support for multiple disparate display types, multi-mode programmable hardware blinking, programmable multiple color depth digital display interface, and programmable matrix controlled grayscale generation.

Abstract: A pseudo random number generator that generates a plurality of intermediate values, where each successive intermediate value is based, at least in part, on one of the succeeding intermediate values, where a final value based on a subset of the plurality of intermediate values. In application, the final value is based on performing a logical operation on the penultimate and last generated intermediate values.

Abstract: An EPG extraction portion extracts EPG information; a program type decision portion decides the type of broadcast program using the extracted EPG information, and outputs a ratio modification signal to change the ratio of the image display interval to the black display interval according to the program type; a driving pulse generation portion generates a gate driver control signal which changes the write timing of a frequency-doubled image signal and frequency-doubled black display signal in one field interval, according to the ratio modification signal; and, a gate driver changes the write timing of the frequency-doubled image signal and frequency-doubled black display signal according to the gate driver control signal, to change the ratio of the image display interval to the black display interval.

Abstract: A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles.

Abstract: The present invention discloses a portable digital graphic processing device having the required graphic processing capability by adopting the advanced multi-chip packaging technology and intelligent stick memory card packaging technology to integrate the graphic processing function into an intelligent stick for the portable purpose and integrate a portable device such as a PDA or a smart phone to enhance the digital graphic processing capability of portable devices.

Abstract: A FIFO section having a FIFO memory is provided between a memory control section and a CPU_I/F section in a path through which image data outputted from a CPU is written into the video memory. Data necessary for writing the image data is stored into the FIFO section and, based on the data stored in the FIFO section, the image data is stored into the video memory under the control of the memory control section. With this configuration, the CPU can output the image data without a wait time until the FIFO memory becomes full, and thus there is provided a liquid crystal display control device that does not lower the operation efficiency of the CPU.

Abstract: A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of Accelerated Graphics Port (AGP) buses. Each of the plurality of AGP buses have the same logical bus number. The core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each AGP device connected to the plurality of AGP physical buses. Each of the plurality of AGP buses has its own read and write queues to provide transaction concurrency of AGP devices on different ones of the plurality of AGP buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each AGP device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used. If no match is found then weak ordering may be used to improve transaction latency times.

Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: An image generating apparatus which includes a frame buffer having a drawing port and a display port for display and including a drawing area containing a graphic image data and a base picture area containing a base picture data, and a graphics drawing circuit, wherein the graphics drawing circuit generates a read address for reading reference data during a blanking period of a video signal, the reference background data is read out from the drawing area in the frame buffer, and the reference base picture data is read from the base picture area in the same buffer, both of which are outputted from the display port during the above blanking period are then transferred to the graphics drawing circuit which uses the above reference data for processing in translucent graphics drawing process.

Abstract: A computer system having an optimized display controller is disclosed. The computer system has a central processing unit connected to a system bus. Within the computer system, both a system memory and a video memory are connected in parallel to the system bus. In addition, the computer system also includes a display controller that is connected only between the system bus and a video display.

Abstract: A system which utilizes two buffers of dual-port memory to seamlessly display video frames on a raster scanned video display device. Dual port memory is organized into two alternate memory banks, each having sufficient capacity to buffer a full frame of video data. As long as the display memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using alternate banks of memory for each frame. When the write and read addresses are closer than a predetermined number of lines, the video data already stored in a given bank of memory is re-read. After the write and read addresses are again sufficiently separated, video data is again written and read using alternate banks of memory.

Abstract: A data processing device and a method by which image data inputted line by line can be distributed as image data of the plural lines, and processing of the image data and converting the image data to a multiple beam image data can be performed by use of separate memories.

Abstract: In a rendering processing system having a rendering memory for storing rendering pixel data generated by a rendering operation circuit and a display memory for storing the image data of a current frame read out from the rendering memory, the display memory stores only the pixel data read out from the rendering memory with prescribed information excluded therefrom. Thus, it is possible to decrease the storage capacity of the display memory and also reduce the time required for writing data into the display memory.

Abstract: An image control device for use in a computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed.