Abstract: Method and system aspects for increasing storage capacity in a digital image capture device are described. Compression levels of saved image files are utilized to increase storage capacity by identifying a level of compression of a saved image file in the digital image capture device. The identified level of compression is compared with a predetermined level of compression, and the saved image file is compressed to the predetermined level of compression when the identified level of compression does not match the predetermined level of compression to free storage space in the digital image capture device.

Abstract: A memory apparatus of a digital video signal for storing color compressed video data is disclosed, the color compressed video data being compressed video data that represents components of three primary colors, the memory apparatus comprising a memory portion for storing the color compressed video data and a color restoring portion for restoring the color compressed video data into original video data, wherein said color restoring portion is disposed on a semiconductor substrate that is used in common with said memory portion.

Abstract: A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES decryption and to demultiplex them. The compressed data streams may include in-band and out-of-band MPEG Transport streams. The video and graphics system processes the PES into digital audio, MPEG video and message data. A core transport processor includes a PCR recovery module for extracting PCRs contained in the compressed data streams and for providing the extracted PCRs to a video transport processor and an audio decode processor. The PCR recovery module has a direct load capability for receiving user defined PCRs and outputting them instead of outputting the extracted PCRs. The PCR recovery module extracts PCRs from both MPEG Transport streams and DIRECTV transport streams.

Abstract: A frame buffer memory is disclosed which provides accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system. One embodiment of the disclosed memory comprises a memory array, a pixel buffer, a plurality of pixel arithmetic-logic units, an input data formatter, an output data formatter, a read data formatter, a write data formatter and an address and control input bus.

Abstract: A method and graphics system configured to perform real-time morphing of three-dimensional (3D) objects that have been compressed into one or more streams of 3D graphics data using geometry compression techniques. In one embodiment, the graphics system has one or more decompression units, each configured to receive and decompress the graphics data. The decompression units are configured to convey the decompressed data corresponding to the morphs to a graphics processor that is configured to apply weighting factors to the graphics data. The weighted results are combined to yield a morphed object that is rendered to generate one or more frames of a morphing sequence. The weighting factors may be adjusted and reapplied to yield additional frames for the morphing sequence. A method for encoding 3D graphics data to allow morphing decompression is also disclosed.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: A system is disclosed providing accurate compression, storage, transmission and reconstruction of both simulated and empirical data representing terrain and other physical or hypothetical signals or surfaces, in one or multiple dimensions. In one embodiment, a gradient of an original surface is generated, and the data representing that gradient is compressed, then stored and/or transmitted. Reconstruction of the gradient yields an accurate representation of the original gradient. An alternative embodiment includes taking a second gradient of the original surface before compression, in which case reconstruction yields the second gradient, from which the first gradient can also be recovered.

Abstract: An immersive video display system is configured to display an immersive video formed by a plurality of compressed environment maps. The immersive video display system includes a decompression unit to partially decompress each compressed environment map to create a partially decompressed environment map. A texture rendering unit creates an image for a view window for each of the compressed environment maps by texture mapping the visible portion of a texture projection using the partially decompressed environment map. By decompressing only a portion of the compressed environment map, the immersive video display system requires less processing time to generate the contents of the view window.

Abstract: An image display apparatus comprises a line buffer unit which stores binary image data, the binary image data being divided into a plurality of line portion data, each line portion data having a fixed length. Pattern matching units are connected in parallel with the line buffer unit and receives the line portion data respectively, each pattern matching unit determining whether an input pattern of a related line portion data matches with one of reference patterns. When the match occurs each pattern matching unit outputs a truth signal indicating the value one, and otherwise each pattern matching unit outputs a falseness signal indicating the value zero.

Abstract: A cache for AGP based computer systems is provided. The graphics cache is included as part of a memory bridge between a processor, a system memory and a graphics processor. A cache controller within the memory bridge detects requests by the processor to store graphics data in the system memory. The cache controller stores the data for these requests in the graphics cache and in the system memory. The cache controller searches the graphics cache each time it receives a request from the graphics controller. If the a cache hit occurs, the cache controller returns the data stored in the graphics cache. Otherwise the request is performed using the system memory. In this way the graphics cache reduces the traffic between the system memory and the memory bridge, overcoming an important performance bottleneck for many graphics systems.

Abstract: An apparatus and method for pixel block compression during rendering in computer graphics is proposed. The method is to divide the image frame into a plurality of blocks and compute those blocks covered by a rendering triangle. If a block is not totally covered by the triangle, the method will read in and decompress the block for reference. Then, the system will render the blocks covered by the triangle and compress each block. At last, the system stores the compressed data stream into memory. The compression method is first to compute a plurality of initial seed colors for clustering the block of pixels. Then, each pixel within the block will be classified into groups with the corresponding initial seed colors. Those pixels with the same initial seed color are averaged to become a new final seed color. Therefore, the coded data comprise the index table and the final seed colors.

Abstract: A graphics processing system which employs one or more frame buffer memory devices is disclosed which system provides accelerated rendering of two-dimensional and three-dimensional images. One embodiment of the disclosed system comprises a rendering controller, an interface, a frame buffer memory, a rendering bus and an address and control bus.

Abstract: A method and apparatus for managing compressed Z information in a video graphics system is described. Pixels in a display frame are grouped into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. When possible, the Z information corresponding to the plurality of pixels in a pixel block is compressed and stored in a Z buffer in a compressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates a level of compression of the Z information for each of the pixel blocks. When Z information for a pixel block is required for processing operations, a cache is first examined to determine if the Z information for the pixel block is included in the cache. If the Z information is not included in the cache, the Z mask memory is consulted to determine the level of compression of the Z information for the particular pixel block.

Abstract: A graphic output unit receives and processes an input signal to provide an image on a display in response to the input signal. The graphic output unit includes a bit stream decoder, a graphic controller, a graphic chip and an interface controller. The interface controller receives the input signal and provides a received signal indicative thereof, and determines the type of data within the input signal. If said input signal includes compressed data the interface controller routes the received signal to the bit stream decoder which decompresses the compressed data within said received signal and provides uncompressed pixel graphic data to the graphic chip. If the input signal includes pixel graphic data the interface controlled routes the received signal to the graphic chip.

Abstract: A method and system for concurrent processing of slices of a bitstream in a multiprocessor (MP) system is disclosed. The MP system includes a number of identical processors and a common memory. The memory is for receiving a plurality of bitstreams (preferably MPEG2 bitstreams) as a plurality of slices. The method and system comprises accessing a semaphore register by one of the plurality of processors and searching for an associated slice within the memory by the one processor. The method and system further comprises processing the associated slice by the one processor. Finally, the method and system comprises updating a memory location which holds the last address of the associated slice by the one processor; wherein subsequent processors search for each of the plurality of slices from the updated last address in the register. A system and method in accordance with the present invention provides for intercommunication between the plurality of processors within a multiprocessing system.

Abstract: A graphics controller which performs display list-based video refresh operations that enable objects with independent frame rates to be efficiently assembled is disclosed. The graphics controller maintains a virtual display refresh list (VDRL) comprising a plurality of pointers to scan line segments in memory. The graphics controller also creates, maintains, and deletes draw display lists (DDLs) that comprise pointers to object display list subroutines (ODLs) that independently draw objects in memory. The ODLs may allocated one or more buffers in memory into which different frames of the objects are drawn. When an ODL has completed executing, the corresponding pointer in the DDL may be updated to point to the buffer location in memory that stores the newly completed object frame. The VDRL is maintained independently (and may be doubled-buffered) and is updated using the DDLs.

Abstract: When an OSD data storage area for storing OSD data needs to be reserved, an area of a frame storage apparatus that should store macroblocks corresponding to an invisible area on a screen is allocated as the OSD data storage area. There is no degradation in picture quality. When doing so, the data reduction control unit 64 receives an instruction to reserve the OSD data storage area and discards the corresponding macroblocks. The OSD data access unit 63 writes the OSD data into an area of the frame storage apparatus that was assigned to store the discarded macroblocks.

Abstract: A method and apparatus for storing data for a plurality of data blocks in a compressed format in memory is presented where the compression scheme used for compressing the data blocks may vary. For each data block included in the plurality of data blocks, the data block is compressed using a compression scheme that is included in a set of predetermined compression schemes. The resulting compressed data set is of a size included in a set of predetermined sizes that correspond to the particular compression scheme utilized. The compressed data set for each block is then stored in a compressed data set memory, where the compressed data sets are stored in groups. A descriptor data set corresponding to each group is then stored in a descriptor memory, where the descriptor data set includes an encoded compression descriptor for each data block included in the group. The data descriptor set also stores a base address that corresponds to a starting location for that group in the compressed data set memory.

Abstract: In the method of converting-to-array according to the present invention, array configuration data is created by classifying the patterns congruent with a master pattern, which is a reference graphic for repetition, in the patterns arranged as mask patterns of a LSI, so that the number of the repetitions of the congruent pattern is the largest one when the congruent pattern is arranged repeatedly with a predetermined repetition pitch.

Abstract: A color image signal input from a CCD or the like is processed to generate a color image signal containing a color subimage portion or a monochrome image signal containing a monochrome subimage portion and to record the image signals directly or after the image signals are JPEG compressed. For JPEG color recording, a color image signal supplied from a CCD and A/D converter is input to a selector, and to a 10/16 converting circuit and a first FIFO, and thereafter a color image and its color subimage are generated by a video processing circuit and compressed by a JPEG circuit, and output from a second FIFO and bus I/F to be recorded. For JPEG monochrome recording, an input color image signal is supplied to the 10/16 converting circuit and clamp circuit, multiplied at the first FIFO by a predetermined coefficient to generate a monochrome image containing a subimage. For RAW color or monochrome recording, JPEG compression is not performed.

Abstract: A display method and apparatus for navigation system for displaying information necessary for guiding a driver of a vehicle. The navigation system is designed to promote safe driving by producing different display forms and contents depending on whether the vehicle is in motion or stationary. When the vehicle is stationary, the navigation system can perform all of the functions. However, when the vehicle is in motion, the navigation system provides simplified and limited functions to ease the operations. The number of key strokes required for operating the navigation system is reduced when the vehicle is in motion.

Abstract: A method and apparatus for managing compressed Z information in a video graphics system that supports anti-aliasing is described. Each pixel in the display frame is represented with a primary Z value, a secondary Z value, a first and second color, and a pixel mask that indicates how the Z values and colors apply to the samples of the pixel. The primary Z values for the pixels in a pixel block are then compressed using a compression algorithm and stored in a Z buffer in a compressed format. A secondary mask that indicates which pixels in the pixel block have valid secondary Z values is also stored in the Z buffer, along with the secondary Z values and the pixel masks in an uncompressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates the level of compression of the Z information the corresponding pixel block.

Abstract: A data processing apparatus improves speed and efficiency of transfer of bit data, especially, multivalue data bit plane. For this purpose, a memory 50 holds four 8-bit multivalue data per 1 word, and bit plane coding processing is made by 4×4 (=16) multivalue data (processing block). In a memory area 51, the most significant bit (bit 7) of respective multivalue data (data 0 to 15 in FIG. 5) is collected in the order of multivalue data, and stored in one position (hatched portions in FIG. 5). Similarly, bit 6 is collected from the respective multivalue data and stored in one position.

Abstract: A virtual frame buffer controller in a computer's display system manages accesses to a display image stored in discrete compressed and uncompressed blocks distributed in physical memory. The controller maps conventional linear pixel addresses of a virtual frame buffer to pixel locations within blocks stored at arbitrary places in physical memory. The virtual frame buffer controller maintains a data structure, called a pointer list, to keep track of the physical memory location and compression state of each block of pixels in the virtual frame buffer. The virtual frame buffer controller initiates a decompression process to decompress a block when a pixel request maps to a pixel in a compressed block. The block remains decompressed until physical memory needs to be reclaimed to free up memory.

Abstract: In an image-processing apparatus, a digital image signal is stored in a memory, and a memory access control part entirely manages all accesses to the memory with respect to the digital image signal. An image processing part converts the digital image signal stored in the memory into an output image signal to be supplied to an imaging unit outputting a visible image based on the output image signal so that a pixel density of the output image signal is higher than a pixel density of the digital image signal read from the memory and an amount of the output image signal is less than an amount of the digital image signal stored in the memory. Accordingly, the central controlled memory is shared by a plurality of functions so as to effectively use the memory, and a high-quality image can be produced by carrying out a density conversion so as to match the pixel density.

Abstract: A data compression apparatus and method of displaying graphics in a computer system employs a full frame buffer and compressed frame buffer wherein pixel data is sent to a display device and concurrently compressed and captured in parallel so that subsequent unchanged frames are regenerated directly from the compressed frame buffer.

Abstract: There are provided an image encoding apparatus and method, which can achieve a low-cost, real-time encoding process by controlling a memory line controller and memory access controller to asynchronously and independently execute a typical prediction discrimination process and adaptive arithmetic coding process by a TP discriminator for reading out image data stored in a line memory for storing input image data, and making typical prediction discrimination in JBIG encoding for the input image data, and an adaptive arithmetic encoder for reading out image data stored in the line memory, and making adaptive arithmetic coding.

Abstract: An MPEG decoder and an MPEG decoding method with two memory controllers is capable of separately controlling compressed data and decoded data. An MPEG decoder decodes a compressed input data formatted in an MPEG type. The MPEG decoder comprises a compressed data memory controller and a decoded data memory controller. The compressed data memory controller is coupled to a compressed data memory and controls the compressed data. The decoded data memory controller is coupled to a decoded data memory, and controls the decoded data. Since the compressed data flow and the decoded data flow are divided, the memory transfer rate is increased, and also the memory control is simple. In addition, the compressed data are able to be stored within the MPEG decoder. Therefore, the high-performance of the MPEG decoder and the high quality of the image are possible.

Abstract: An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably uses a lossless data compression and decompression scheme. Data transfers to and from the integrated memory controller of the present invention can thus be in either two formats, these being compressed or normal (non-compressed). The IMC also preferably includes microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data from system I/O peripherals such as the hard drive, floppy drive, or local area network (LAN) are decompressed in the IMC and stored into system memory or saved in the system memory in compressed format.

Abstract: A bus compression apparatus for compressing data is provided to suppress an EMI signal and to simplify a data bus structure. In the apparatus, the voltage levels of the digital output signals are summed in accordance with the resistance values of the data compression circuit to produce a compressed analog signal. The compressed analog signal is transmitted through a bus lines to a data decompressor which reproduces the digital data in response to the voltage levels of the compressed analog signal.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: An image data displaying system in which compressed image data is transmitted to an image displaying apparatus via an information transmission facility and is decompressed into an original image using an image decompressing section provided in the image displaying apparatus so as to display the original image. The image data displaying system includes image data for one screen received via said information transmission facility, said image data in a mixture of progressive driving parts and interlacing scanning parts in groups of n-pieces of lines.

Abstract: An improved technique for processing a color or gray scale pixel map representing a document is disclosed. The pixel map is decomposed into a three-plane representation, a reduced-resolution “upper” plane, a reduced-resolution “lower” plane, and a high-resolution binary selector plane. The “upper” and “lower” planes contain the color or gray scale for the page as well as the continuous tone pictures that are contained on the page. The selector plane stores information for selecting from either the foreground plane or background plane during decompression. Information contained in the selector plane is first used to pre-process the upper and lower planes to reduce the amount of data on each of the other two planes that will be subjected to further processing. Each of the pre-processed planes is compressed using a compression technique optimal for the type of data that resides upon it.

Abstract: An improved technique for processing a color or gray scale pixel map representing a document is disclosed. The pixel map is decomposed into a three-plane representation, a reduced-resolution “upper” plane, a reduced-resolution “lower” plane, and a high-resolution binary selector plane. The “upper” and “lower” planes contain the color or gray scale for the page as well as the continuous tone pictures that are contained on the page. The selector plane stores information for selecting from either the foreground plane or background plane during decompression. Information contained in the selector plane is first used to pre-process the upper and lower planes to reduce the amount of data on each of the other two planes that will be subjected to further processing. Each of the pre-processed planes is compressed using a compression technique optimal for the type of data that resides upon it.

Abstract: A method and apparatus for compressing a mixed raster content image that represents a color or gray scale a document is disclosed. The pixel map is decomposed into a three-plane representation—a reduced-resolution “upper” plane, a reduced-resolution “lower” plane, and a high-resolution binary selector plane. An iterative smoothing technique is then used to pre-process the upper and lower planes using the information contained in the selector plane, thereby reducing the amount of data that will be subjected to further processing.