Abstract: A method for efficiently processing graphics data for graphics primitives, the graphics data including vertex coordinate information and vertex attribute data. Coordinate information, in the form of homogeneous coordinates, of the graphics primitive determines whether the graphics primitive is to be rendered. If the primitive is to be rendered, then attribute data associated with the location information is retrieved. However, if the data is not to be rendered, then the location information is discarded. By only retrieving parameters for a primitive that is rendered, performance is increased. In one embodiment, the attribute data is fetched before it is known whether or not the graphics primitive is to be rendered, and if not, the prefetch is aborted, and new location information is fetched.

Abstract: A method of deferring evaluation of a transform, in accordance with one embodiment of the present invention, includes buffering a plurality of vertex data. The method also includes receiving a draw command, accessing a given vertex data corresponding to the draw command and an associated transform indicator bit. The given vertex data is transformed if the associated indicator bit is cleared. After performing the transform, the vertex data is overwritten with the transformed vertex data and the associated transform indicator bit is set.

Abstract: Disclosed herein are a portable information terminal apparatus, an information processing method, a computer-program storage medium, and a computer-program. In a portable information terminal apparatus capable of managing a schedule list, the apparatus includes acquiring means for acquiring program information; displaying means for displaying the program information acquired by the acquiring means; establishing means for establishing preset information for presetting a program for unattended recording based on an operation input by a user referring to the program information displayed by the displaying means; and writing means for writing to the schedule list the preset information established by the establishing means. In the apparatus, the displaying means further displays the schedule list including the preset information written by the writing means.

Abstract: On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics.

Abstract: In order to efficiently conduct the display processing of a GUI screen by suppressing the drawing of unnecessary objects, the objects are, first, searched from the front toward the rear according to a reverse painter's algorithm while tracing a z-order for processing the drawing. In this step, flags necessary for the drawing may be raised instead of drawing the objects, and a z-buffer needs not be provided. The objects can be really drawn from the rear toward the front according to a painter's algorithm.

Abstract: In order to efficiently conduct the display processing of a GUI screen by suppressing the drawing of unnecessary objects, the objects are, first, searched from the front toward the rear according to a reverse painter's algorithm while tracing a z-order for processing the drawing. In this step, flags necessary for the drawing may be raised instead of drawing the objects, and a z-buffer needs not be provided. The objects can be really drawn from the rear toward the front according to a painter's algorithm.

Abstract: A method and apparatus for automatically tuning the output line rate thereof and a display controller provided with the same. The display controller of the present invention provides a display controller having a line buffer, an input means, an output means, a status detector, and an auto-tune control means. The input means is employed to write line data into the line buffer at an input line rate, and the output means is employed to read the written line data from the line buffer at an output line rate. The status detector is coupled to the input means and the output means for generating a status signal indicating whether the input line rate and the output line rate are unbalanced. The auto-tune control means is used to adjust the output line rate in response to the status signal so as to balance the input line rate and the output line rate.

Abstract: A method of representing a color image comprises selecting a region of the image, selecting one or more colors as representative colors for the region and, for a region having two or more representative colors, calculating two parameters for each representative color including the variance of the color distribution of the image and the color space value and using these parameters to derive descriptors for the image region.

Abstract: A system, method and computer program product are provided for branching during programmable processing utilizing a graphics application program interface in conjunction with a hardware graphics pipeline. Initially, a first instruction defined by the graphics application program interface is identified. A first operation is performed on graphics data based on the first instruction utilizing the hardware graphics pipeline. Any some point, the present technique may involve branching to an additional instruction defined by the graphics application program interface other than a subsequent sequential instruction. Next, another operation is performed on the graphics data based on the additional instruction utilizing the hardware graphics pipeline.

Abstract: A sort middle graphics architecture comprising a host interface for receiving raw primitive data from a graphics application; a geometry processing module coupled to the host interface for receiving the raw primitive data from the host interface and generating sort middle traffic data, said geometry processing module a having a built-in compression module for compressing the sort middle traffic data; and a rasterization module coupled to the host interface for receiving the compressed sort middle traffic data and rasterizing the data, said rasterization module having a built-in decompression module for decompressing the sort middle traffic data before it is rasterized.

Abstract: A control device, which is capable of suppressing an increase in a load of a data transfer for an increase of an amount of data is provided. The control device includes a compressed data generation unit for generating a compressed data based on a set-up value inputted, and a controller for outputting a frame rate information to the compressed data generation unit, and for making compressed data to be outputted from a memory for use in storing a compressed data to an image display device in accordance with the frame rate.

Abstract: A memory device and an image processing apparatus able to achieve an increase in speed of a region growing algorithm which conventionally involved a long processing time and thereby enabling real time operation, including a memory array comprised of a matrix of a plurality of memory units each having two memory cells adjacent to each other in the same row, one flag cell, and two transfer gates for transferring flag data of the flag cell to the flag cells of the memory units adjacent in a row direction and a column direction in accordance with the stored data of each memory cell and including a region growing circuit for writing correlation data as results of operation of correlation of adjacent pixels into all memory cells, starting the region growing processing from a designated position (address) to extract an object, and outputting the same to an image combining unit.

Abstract: In a graphics processing circuit, up to N sets of state data are stored in a buffer such that a total length of the N sets of state data does not exceed the total length of the buffer. When a length of additional state data would exceed a length of available space in the buffer, storage of the additional set of state data in the buffer is delayed until at least M of the N sets of state data are no longer being used to process graphics primitives, wherein M is less than or equal to N. The buffer is preferably implemented as a ring buffer, thereby minimizing the impact of state data updates. To further prevent corruption of state data, additional sets of state data are prohibited from being added to the buffer if a maximum number of allowed states is already stored in the buffer.

Abstract: A system and method for rendering a graphics primitive. A two pass method is employed where, in the first pass, for each block affected by the primitive, whether the pixels of the affected block intersect the front and/or back layers of the block is determined. If there are intersected pixels in the block, a flag is set indicating that the z-buffer must be read to determine the visibility of the affected pixels in the block. On a second pass, the blocks affected by the graphics primitive are again examined. If the flag is not set, then the visible pixels are rendered to the frame buffer based on the front and back layers of the block. If the flag is set, then for each sub-block affected by the primitive, the z-buffer is read and the visible pixels are rendered to the frame buffer based on the reading of the z-buffer.

Abstract: A method of eliminating stale information from a computer graphics buffer. The method facilitates switching from a fast clear mode to a non fast clear mode during the lifetime of a region of interest such as a window: A clear count value associated with a pixel is read and compared with a current clear count. If the counts are not equal, a replacement value is written into the pixel. The process may be repeated for each pixel in the region. Block transfer hardware and fast clear hardware may be used together to perform the procedure in a high-performance manner: A source region and a destination region for the block transfer operation are both set to the region of interest. As the block transfer proceeds, each pixel is written either with its own value or with a replacement value depending on whether the clear count for the pixel is current.

Abstract: In order to efficiently conduct the display processing of a GUI screen by suppressing the drawing of unnecessary objects, the objects are, first, searched from the front toward the rear according to a reverse painter's algorithm while tracing a z-order for processing the drawing. In this step, flags necessary for the drawing may be raised instead of drawing the objects, and a z-buffer needs not be provided. The objects can be really drawn from the rear toward the front according to a painter's algorithm.

Abstract: A CPU 200 displays on the display screen of a display device 20 the image data of an image received file via a memory card MC or a connecting cable CV. The CPU 200 displays color-correction parameters entered via an input device 240, as well as image data that reflect the color-space parameters, on the display screen of the display device 20 together with the original image data. When it is detected that a request has been issued for application of the set color-space parameters and color-correction parameters, the CPU 200 adds the set color-space parameters and color-correction parameters to the image file as image processing control information.

Abstract: A method and system for synchronizing data streams and transferring control of resources between two processes in a graphics processor is described. The method allows for completion of pending operations of a first process in a manner that ensures the first process may be restarted without loss of data or process sequence. The processing pipeline is allowed to complete normal execution of all process operations required to reach a first process step that may be interrupted. The second process is initiated when the interruption of the first process is verified. Upon completion of the second process, the first process is reactivated at the next process step in sequence.

Abstract: A system and method for controlling graphics rendering pipelines. The pipeline is unstalled in response to a display interval complete signal which allows pipeline processing to proceed even at the beginning of a tolerance interval. A stall controller unstalls processing of the graphics data in the graphics rendering pipeline when a display interval complete signal has been generated. A stall token installer inserts stall tokens in between frames of the graphics data. A queue stores frame complete markers in an order matching the order of stall tokens inserted in between frames of graphics data.

Abstract: A method and apparatus for providing a computer system having a plurality of logical partitions with a virtual operator panel is disclosed. The method and apparatus include displaying a plurality of operator panels on a single console corresponding to each of the logical partitions, and providing a buffer for each logical partition. The status codes from each of the logical partitions are then written directly to the corresponding buffer. To display the status codes of one of the logical partitions, the status code from the buffer corresponding the logical partition is read and sent to the corresponding operator panel for display.

Abstract: A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: A method and apparatus in a data processing system for processing graphics data in a processing element. A command is received. A determination is then made as to whether the command affects processing of current graphics data within the processing element. The command is sent to a subsequent processing element if the processing element is unaffected by the command. The command is held without affecting the processing element if the command affects processing of the current graphics data within the processing element until processing of the current graphics data has completed.

Abstract: A graphic accelerator interface device for a computer is provided. The accelerator has a host data path that includes a plurality of comparators, each assigned to permit os/application access to a different “surface” which is defined by an address range corresponding to a block of data in a frame buffer. Unlike the prior art, an access flag register is associated with the host data path such that each surface assigned to a comparator has associated read and write flags. Whenever a read or a write occurs to one of the assigned surfaces via the host data path, the corresponding flag is set. Preferably, for os/application access, the surfaces contain data in an untiled format which the graphic accelerator uses in a tiled format. The invention affords more efficient, i.e.

Abstract: A system and method are provided for executing a cellular automata program in a hardware graphics pipeline. Initially, cell values are received in a hardware graphics pipeline. Next, the cell values are rendered to generate a condition value utilizing the hardware graphics pipeline. A cell value result for the subsequent generation is read from a rule map according to the condition value utilizing the hardware graphics pipeline. Still yet, additional cell values are stored based on the rule map value.

Abstract: The present invention provides a mechanism to track and manage graphics state with hardware state-binning logic for use with the tile-based zone rendering method of generating graphical images. Only the current values of the dynamic state variables are maintained in hardware. Dynamic includes, but is not limited to, state variables that are considered likely to change between primitives. The set of dynamic state variables is subdivided into subgroups. Each state group is associated with a per-bin array of tracking bits. Whenever a state change is encountered, the tracking bit corresponding to the associated state group is set for all bins. Prior to placing a primitive in a bin, the tracking bits associated with that bin are examined, and the current state corresponding to set tracking bits is inserted in the bin before the primitive. Then the tracking bits for that bin are cleared.

Abstract: The present invention provides an image output device which can periodically update display of image data as well as update the display images immediately and with minimum data transfer. A data transfer request control circuit 107 including a frame rate register 108 for deciding a data transfer request issue cycle and a data transfer request issuing unit 109 is provided in a video processing unit 104 of the image output device. When an update flag is set in the frame rate register 108, the data transfer request is issued in the next transfer section, regardless of the periodic transfer cycle, and the image data stored in the frame memory 106 are update.

Abstract: A method and apparatus for reducing latency in pipelined circuits that process dependent operations is presented. In order to reduce latency for dependent operations, a pre-accumulation register is included in an operation pipeline between a first operation unit and a second operation unit. The pre-accumulation register stores a first result produced by the first operation unit during a first operation. When the first operation unit completes a second operation to produce a second result, the first result stored in the pre-accumulation register is presented to the second operation unit along with the second result as input operands.

Abstract: The present invention provides a mechanism for implementing z-compression in a manner that is transparent to the user. Blocks of z-data are associated with storage locations in a z-data buffer in cleared, compressed, or uncompressed data states. Operations to the z-data buffer are monitored for selected operations. These operations may include clear or lock operations. If a selected operation is detected, a modified version of the selected operation is implemented to mask differences between the storage states of the data blocks.

Abstract: The invention provides basic 1-to-1 character case mapping information for Unicode characters while using only small amount of memory and at a reasonable speed. The presently preferred embodiment of the invention provides a technique that encodes the case mapping into a sequential list of <Minimum, Size, Gap, Offset> quadruple. Every quadruple represents a range of characters. The Minimum and Size values represent the boundary of the range. The Gap represents which characters in the range have the valid mapping. Thus, if the character Minimum is a multiple of the Gap, then the character has a mapping in the quadruple. Otherwise, the character does not have a mapping. If the character has a mapping, then the mapped value is the character plus the Offset.

Abstract: An apparatus and method are disclosed for synchronization of command processing from multiple command queues. Various embodiments employ a condition code register that indicates which queues should have processing suspended until a specified event condition occurs. Upon satisfaction of the specified condition, processing of commands from the suspended queue is resumed.

Abstract: A method and apparatus for generation of pixel lookahead information in a cached computer graphics system is provided. For each pixel-based memory operation, several data items may be generated, such as numerical values representing a coordinate point in an image coordinate space or display coordinate space and characteristic data representing a color value or depth value for the pixel. In addition, lookahead data correlated with the coordinate data is generated. The pixel operation is then issued with the characteristic data, the coordinate data, and the lookahead data. The lookahead data may contain a lookahead vector, which specifies a lookahead vector direction and a lookahead vector length, and a lookahead valid flag, which indicates whether associated lookahead data is valid for the pixel operation.

Abstract: An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. Similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels.

Abstract: A telecom mask testing zoom function draws mask. pixels into a raster memory. In this way, the mask is treated as a waveform. Comparison of the mask pixels and waveform pixels to detect collision between a waveform pixel and a mask pixel (i.e., a mask violation) is performed substantially in real time, as the pixels are being composited into the raster memory by the rasterizer. The mask is scalable and repositionable by the rasterizer under control of a controller, because it is treated as a waveform. The mask is lockable to the waveform because both are stored in pixel form in raster memory by the rasterizer under control of the controller.

Abstract: A polygon rendering system for receiving geometric data defining a polygon in an image being generated. The polygon rendering system renders the geometric data as pixel data. The pixel data defines pixels used to display the image. The system comprises a first memory buffer for storing the pixel data. It also comprises a second memory buffer for storing additional pixel data used to render edge pixels at a higher resolution than pixels that are not the edge pixels. Edge pixels are pixels that are located on an edge of the polygon in the image. The system also comprises a display controller for outputting the pixel data in the first memory buffer to output circuitry. The polygon rendering system identifies which of the pixels are the edge pixels and the display controller updates contents of the first buffer with data based on contents of the second buffer.

Abstract: A program controlled machine wherein signals produced in response to execution of programs control operation of machine devices includes a control for storage, retrieval and presentation of audio/video information. The control includes devices for presentation of audio/video information and stored programs including programs for enabling storage of audio/video information files while the machine is in a manual mode of operation and programs for controlling the presentation by the audio/video presentation devices of selected audio/video information from the stored files. The control provides facilities for recording audio/video information and for manually controlled presentation of audio/video information as well as for automatic presentation of audio/video information in response to detection of occurrence of a particular event.

Abstract: A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.

Abstract: A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operations. A plurality of addresses are then identified in memory based on the mode bits. Such addresses are then accessed in the memory for retrieving code segments which each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed within a transform or lighting module for processing vertex data.

Abstract: Compressed graphic image data files, such as Compressed ARC (Arc-second Raster Chart/map) Digitized Raster Graphics (CADRG) map files for a region of interest, are stored in blocks of memory (nodes) preferably arranged as a linked list. Portions of files containing data for an area of interest including an image of interest are decompressed before the data are sent to a frame buffer for display. Nodes that do not contain requested data are flagged as unused, but not deallocated, making the data in such nodes available for use or replacement.

Abstract: A memory device and an image processing apparatus able to achieve an increase in speed of a region growing algorithm which conventionally involved a long processing time and thereby enabling real time operation, including a memory array comprised of a matrix of a plurality of memory units each having two memory cells adjacent to each other in the same row, one flag cell, and two transfer gates for transferring flag data of the flag cell to the flag cells of the memory units adjacent in a row direction and a column direction in accordance with the stored data of each memory cell and including a region growing circuit for writing correlation data as results of operation of correlation of adjacent pixels into all memory cells, starting the region growing processing from a designated position (address) to extract an object, and outputting the same to an image combining unit.

Abstract: A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

Abstract: A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES decryption and to demultiplex them. The compressed data streams may include in-band and out-of-band MPEG Transport streams. The video and graphics system processes the PES into digital audio, MPEG video and message data. A core transport processor includes a PCR recovery module for extracting PCRs contained in the compressed data streams and for providing the extracted PCRs to a video transport processor and an audio decode processor. The PCR recovery module has a direct load capability for receiving user defined PCRs and outputting them instead of outputting the extracted PCRs. The PCR recovery module extracts PCRs from both MPEG Transport streams and DIRECTV transport streams.

Abstract: A method, computer program product and system for allocating the memory space in a frame buffer. A Device Dependent Layer (DDX) of an X-server may read command line options or alternatively an option selected by a user. If the command line options or alternatively the user selectable option indicates to allocate the memory space in the frame buffer to support a particular type of stereo, e.g., double buffered stereo, single buffered stereo, then the DDX may allocate the memory space in the frame buffer accordingly. If the memory space of the frame buffer is allocated for single buffered stereo, then the extra memory space in the frame buffer from not supporting double buffered stereo may be allocated for texture and/or off screen caching.

Abstract: An image decoding and display device includes a frame memory interface (3) and a frame memory (5). The frame memory (5) has a bank 0, a bank 1, a bank 2. The bank 2 is made up of plural sectors (sector 0, . . . , and sector N). Under a dynamic mapping mode, the frame memory interface (3) refers a sector information table (32) including sector use information in order to search and fetch an unused sector. The frame memory interface (3) allocates the unused sector in the bank 2 when decoded image data are written into the bank 2, and release the used sector when the decoded image data are read from the bank 2.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A buffer and table structure for reordering out-of-order evictions from a write-combine buffer. In a preferred embodiment, a first-in first-out (FIFO) buffer is used.

Abstract: In an image processing system or method, an image element memorizing device memorizes image elements which are image data that are subjects of process. An image element processing state memorizing device memorizes present processing states of the image elements in the image element memorizing device. A detecting device detects, in response to the present processing states, a pointer of one of the image elements that is capable of being processed by the image processing system. A temporary pointer memorizing device memorizes the pointer from the detecting device. A calculating device reads the pointer from the temporary pointer memorizing device to process an image in response to the image element of the pointer which is read.

Abstract: Apparatus and methods for storing and retrieving images for transmission to an output device are disclosed. A cache comprising one or more bitmaps is examined to determine whether the image to be transmitted generates a match with a bitmap already stored on the cache. If a match is found, the bitmap matching the image to be transmitted is retrieved from the cache. If no match is found, a bitmap representing the image is stored in the cache.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in the memory of the host computer system. Each packet descriptor includes a pointer to a region of memory known as a packet buffer. Each packet descriptor also includes a ready variable. To pass commands to the graphics processor, a graphics process selects a packet buffer. The packet buffer must have a ready variable that is set to the value false. After selection of the appropriate packet descriptor, the graphics process writes the desired commands into the packet descriptor associated with the selected packet descriptor. The graphics process then sets the ready variable included in the selected packet descriptor to true. The graphics processor traverses the queues of packet descriptors.