Abstract: In a 3D interactive computer graphics system such as a video game display system, polygon vertex data is fed to a 3D graphics processor/display engine via a vertex cache used to cache and organize indexed primitive vertex data streams. The vertex cache may be a small, low-latency cache memory local to the display engine hardware. Polygons can be represented as indexed arrays, e.g., indexed linear lists of data components representing some feature of a vertex (for example, positions, colors, surface normals, or texture coordinates). The vertex cache can fetch the relevant blocks of indexed vertex attribute data on an as-needed basis to make it available to the display processor—providing spatial locality for display processing without requiring the vertex data to be prestored in display order.

Abstract: Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing logic portion, and a control logic portion. These portions are preferably implemented as an extension of the internal architecture of the CPU. The CPU may be attached to the graphics system via a data cache and a write buffer portion. Data is read from the system memory and placed in the data cache so that subsequent accesses to the same location only require access to the cache. System memory data is written to a write buffer, so that the data written may be queued up and sent to the main memory at an appropriate time. The display refresh controller also reads the data from the system memory and converts the data to a signal for output to a display.

Abstract: A graphics geometry cache. The basic idea of one embodiment in accordance with the present invention is to utilize a graphics geometry cache together with a graphics pipeline. The graphics geometry cache is a relatively small cache (e.g., 128 entries) used for storing and maintaining vertex data. Specifically, the results of computations performed on vertices by the graphics pipeline (e.g., transformed vertices and attributes such as color) are cached within the graphics geometry cache. Furthermore, the cached entries are tagged by their corresponding vertex coordinates. Subsequently, when a particular vertex is specified for the graphics pipeline, a tag compare is executed through a hashing function to determine whether the graphics geometry data for that particular vertex is stored within the graphics geometry cache.

Abstract: A system and method are provided for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART). In the system and method, a translation look-aside buffer cache has a plurality of translation look-aside buffer entries. Each translation look-aside buffer entry is operable to buffer information which may be accessed for use in translating a virtual address into a physical address. A least recently used pointer circuit is operable to point to a translation look-aside buffer entry buffering information least recently used in the translation look-aside buffer cache. During operation, updates to the least recently used pointer circuit may be pipelined with corresponding accesses to the translation look-aside buffer cache.

Abstract: A graphics system in which the dedicated graphics memory is doubly virtualized: it can be paged into host physical memory, and also, beyond that, into host bulk storage. Portions of host physical memory which are needed to support the graphics memory management process can be locked down.

Abstract: A memory system includes a memory cache responsive to a single processing unit. The memory cache is arrangeable to include a first independently cached area assigned to store a first number of data packets based on a first processing unit context, and a second independently cached area assigned to store a second number of data packets based on a second processing unit context. A memory control system is coupled to the memory cache, and is configured to arrange the first independently cached area and the second independently cached area in such a manner that the first number of data packets and the second number of data packets coexist in the memory cache and are available for transfer between the memory cache and the single processing unit.

Abstract: The present invention relates to a system and method for accelerating graphics. The system includes a memory device for accelerating graphics operations within an electronic device. A memory controller is used for controlling pixel data transmitted to and from the memory device. A cache memory is electrically coupled to the memory and is dynamically configurable to a selected usable size to exchange an amount of pixel data having the selected usable size with the memory controller. The memory device may be an SDRAM. The cache memory may also comprise a plurality of usable memory areas or tiles.

Abstract: A first scanline of an input image is spatially transformed into a first pixel sequence of an output image. Holes in the first sequence are interpolated if magnifying the input image. Overlapping pixels in the first sequence are adjusted if minifying the input image. After transforming the first scanline, a second scanline of the source image is transformed into a second pixel sequence of the output image. Holes in the second sequence are interpolated if magnifying the input image. Overlapping pixels in the second sequence are adjusted if minifying the input image. Overlapping pixels across the first and second sequences are adjusted and holes between the first and second sequences are interpolated if rotating the input image.

Abstract: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

Abstract: A method and system of operating a remote terminal by a terminal server caches representation data of glyphs to be displayed on the remote terminal to reduce the amount of glyph data that have to be transmitted to the remote terminal through a network connection. The glyph caching is performed on a level of text fragments each of which includes a plurality of glyphs. The remote terminal stores a fragment cache for caching fragments and glyph caches for caching individual glyphs. Each entry in the fragment cache contains data indicating where the glyph data for the glyphs of the fragment are stored in the glyph caches. When the terminal server receives a request to display a text fragment on the remote terminal, it checks whether that fragment is cached at the remote terminal. If so, the terminal server sends a fragment index to the client identifying the entry in the fragment cache for that fragment.

Abstract: A method and apparatus for generation of pixel lookahead information in a cached computer graphics system is provided. For each pixel-based memory operation, several data items may be generated, such as numerical values representing a coordinate point in an image coordinate space or display coordinate space and characteristic data representing a color value or depth value for the pixel. In addition, lookahead data correlated with the coordinate data is generated. The pixel operation is then issued with the characteristic data, the coordinate data, and the lookahead data. The lookahead data may contain a lookahead vector, which specifies a lookahead vector direction and a lookahead vector length, and a lookahead valid flag, which indicates whether associated lookahead data is valid for the pixel operation.

Abstract: A method and system according to the present invention provide for sharing memory between applications running on one or more CPUs, and acceleration co-processors, such as graphics processors, of a computer system in which the memory may retain its optimal caching and access attributes favorable to the maximum performance of both CPU and graphics processor. The method involves a division of ownership within which the shared memory is made coherent with respect to the previous owner, prior to handing placing the shared memory in the view the next owner. This arbitration may involve interfaces within which ownership is transitioned from one client to another. Within such transition of ownership the memory may be changed from one view to another by actively altering the processor caching attributes of the shared memory as well as via the use of processor low-level cache control instructions, and/or graphics processor render flush algorithms which serve to enforce data coherency.

Abstract: A polygon rendering system for receiving geometric data defining a polygon in an image being generated. The polygon rendering system renders the geometric data as pixel data. The pixel data defines pixels used to display the image. The system comprises a first memory buffer for storing the pixel data. It also comprises a second memory buffer for storing additional pixel data used to render edge pixels at a higher resolution than pixels that are not the edge pixels. Edge pixels are pixels that are located on an edge of the polygon in the image. The system also comprises a display controller for outputting the pixel data in the first memory buffer to output circuitry. The polygon rendering system identifies which of the pixels are the edge pixels and the display controller updates contents of the first buffer with data based on contents of the second buffer.

Abstract: A method and apparatus for managing compressed Z information in a video graphics system is described. Pixels in a display frame are grouped into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. When possible, the Z information corresponding to the plurality of pixels in a pixel block is compressed and stored in a Z buffer in a compressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates a level of compression of the Z information for each of the pixel blocks. When Z information for a pixel block is required for processing operations, a cache is first examined to determine if the Z information for the pixel block is included in the cache. If the Z information is not included in the cache, the Z mask memory is consulted to determine the level of compression of the Z information for the particular pixel block.

Abstract: In one embodiment, the invention is a method. The method includes monitoring a data stream. The method also includes partitioning a cache into two sub-caches based on monitoring the data stream.

Abstract: A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines, each cache line addressable by a cache line address; a first plurality of storage elements coupled to a first address bus; and a second plurality of storage elements coupled to the first plurality of storage elements. The first plurality of storage elements holds a second number of cache line addresses, and the second plurality of storage elements holds a third number of cache line addresses.

Abstract: A two-way cache system for interfacing with a peripheral device and a method of operating a two-way cache system for carrying out data transmission between a peripheral device and a memory unit. The cache system has a two-way first-in first-out buffer region and a two-way cache controller. The two-way first-in first-out buffer region further has a first cache data region and a second cache data region. The first cache data region and the second cache data region are capable of holding a batch of first cache data and a batch of second cache data. The two-way cache controller receives a read request from the peripheral device. According to the read request, the requested data and data that ensues or comes after the requested data are retained by the two-way first-in first-out buffer (FIFO) region.

Abstract: A texture loading pipeline loads textures for use in rendering an object. A source texture has one or more levels of detail. Each level of detail (LOD) contains texture tiles for a particular area of a global coordinate space at a particular resolution. There are no mandatory relationships between the areas represented by, or the resolutions of, different levels of detail. An instance of the texture loading pipeline exists for each LOD in the source texture. The texture tiles of a LOD are stored in a texture storage, which can be local or remote from the texture loading pipeline. An asynchronous request queue (ARQ) retrieves texture tiles in a region of interest from the texture storage and stores the tiles in a tile cache. Toroidal roaming is used to page textures in the region of interest from the tile cache to a texture cache. The toroidal roaming performs the best possible update of the texture cache given a limited update time.

Abstract: A graphics processing chip which includes parallel texturing pipelines, with task allocation units which can bypass inoperative ones of said pipelines. Chips which have some but not all pipelines operative can still have full functionality, although performance is reduced.

Abstract: An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: A memory system comprises a memory, a memory controller and a cache. The memory stores a plurality of data packets, which are associated with a plurality of data types. The memory controller receives requests for data packets from a processing unit and passes requested data packets from the memory to the processing unit. The cache comprises a plurality of independently cached areas. The memory controller passes requested data packets from the memory to the cache. The memory controller passes requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller. The memory controller assigns each independently cached area in the cache to store data packets associated with one item type where an item type may be a texture, thread, task or process. Each independently cached area is associated with a data usage indicator.

Abstract: A memory interface controls read and write accesses to a memory device. The memory device includes a level-one cache, level-two cache and storage cell array. The memory interface includes a data request processor (DRP), a memory control processor (MCP) and a block cleansing unit (BCU). The MCP controls transfers between the storage cell array, the level-two cache and the level-one cache. In response to a read request with associated read clear indication, the DRP controls a read from a level-one cache block, updates bits in a corresponding dirty tag, and sets a mode indicator of the dirty tag to a the read clear mode. The modified dirty tag bits and mode indicator are signals to the BCU that the level-one cache block requires a source clear operation. The BCU commands the transfer of data from a color fill block in the level-one cache to the level-two cache.

Abstract: A method for enhanced fragment caching. The method can include identifying in at least one of first and second retrieved page fragments a variable object utilized by the fragment upon execution to produce dynamic content. Separate cache entries can be written for the first and second retrieved page fragments where the first and second retrieved page fragments differ in ways other than an evaluation of the variable object. Otherwise, a single cache entry can be written for both the first and second retrieved page fragments where the first and second retrieved page fragments differ only in the evaluation of the variable object.

Abstract: An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.

Abstract: A system and method is provided for mipmap texturing in which texture tiles are mapped into sets of a set-associative texture cache for use in displaying a graphic primitive. When a miss occurs, a new texture tile is called from main memory to replace a texture tile which is not shared between the segment being traversed and the next segment to be traversed and which is the “least recently used”. This is accomplished by maintaining a record for each cache line describing the texture tile it contains and replacing the texture tile which is the “least likely to be reused”.

Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

Abstract: A graphics processing unit in which the caching algorithm changes at the end of a line (or alternatively when the data from the beginning of the current line comes up for discard). This avoids the problem of continuous misses at the start of a new line, which can occur when the texture cache is not big enough to hold a full line's worth of data.

Abstract: The present invention discloses an apparatus and method for cache memory connection of texture mapping, applied in a computer graphic processing system by storing image texels in cache memories. The apparatus comprises a plurality of cache memories. An array of image texels are stored in a plurality of cache memories to reduce the area occupied by cache memories of the computer graphic processing system. Besides, the apparatus and method of the present invention can be applied in the well-known mapping methods: selecting the nearest point, bilinear filtering and trilinear filtering. A plurality of multiplexers are used to reorganize the plurality of cache memories so as to increase the utilization efficiency of the apparatus of the present invention.

Abstract: The cache memory is particularly suitable for processing images. The special configuration of a memory field, an allocation unit, a write queue, and a data conflict recognition unit enable a number of data items to be read out from the memory field simultaneously per cycle, in the form of line or column segments. The format of the screen windows that are read out can change from one cycle to another. With sufficient data locality, time-consuming reloading operations do not damage the data throughput since the access requests are pipelined.

Abstract: A method traces rays through graphical data. The method partitions the graphical data into a plurality of blocks according to a scheduling grid. For each block, a ray queue is generated. Each entry in the ray queue representing a ray to be traced through the block. The ray queues are ordered spatially and temporally using a dependency graph. The rays are traced through the blocks according to the ordered list.

Abstract: An intelligent caching data structure and mechanisms for storing visual information via objects and data representing graphics information. The data structure is generally associated with mechanisms that intelligently control how the visual information therein is populated and used. The cache data structure can be traversed for direct rendering, or traversed for pre-processing the visual information into an instruction stream for another entity. Much of the data typically has no external reference to it, thereby enabling more of the information stored in the data structure to be processed to conserve resources. A transaction/batching-like model for updating the data structure enables external modifications to the data structure without interrupting reading from the data structure, and such that changes received are atomically implemented. A method and mechanism are provided to call back to an application program in order to create or re-create portions of the data structure as needed, to conserve resources.

Abstract: The invention provides a method of generating cache indexes that reduces the likelihood that adjacent addresses will map to the same cache regions. The hashing process is optimized to be sensitive to small changes in the input data so that similar sets of input data will preferably not result in the same or even similar output data. Memory accesses of the sort performed when rendering graphical images may involve numerous accesses to relatively similar memory locations Therefore, hashing of the index values that determine where the information from the memory locations will be stored while that information is in cache decreases the likelihood of similar memory locations being stored at the same cache location. Consequently, cache efficiency and performance is improved.

Abstract: A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

Abstract: A frame buffer memory is disclosed which provides accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system. One embodiment of the disclosed memory comprises a memory array, a pixel buffer, a plurality of pixel arithmetic-logic units, an input data formatter, an output data formatter, a read data formatter, a write data formatter and an address and control input bus.

Abstract: Video processing apparatus and method, in which successive video processing operations are applied to images generate corresponding processing results in the form of images or data, for storing cached items and processing results associated with the video processing operations, and providing for deleting currently cached items to provide cache space for items to be newly cached, so that non-image processing results are retained in the cache for longer than processing results in the form of images.

Abstract: A cache for AGP based computer systems is provided. The graphics cache is included as part of a memory bridge between a processor, a system memory and a graphics processor. A cache controller within the memory bridge detects requests by the processor to store graphics data in the system memory. The cache controller stores the data for these requests in the graphics cache and in the system memory. The cache controller searches the graphics cache each time it receives a request from the graphics controller. If the a cache hit occurs, the cache controller returns the data stored in the graphics cache. Otherwise the request is performed using the system memory. In this way the graphics cache reduces the traffic between the system memory and the memory bridge, overcoming an important performance bottleneck for many graphics systems.

Abstract: To increase the cache hit ratio of a requested image and shorten the user's average waiting time, images of a CD-ROM changer are cached in an intermediate HDD having a high retrieval speed, and provided to the user. When a requested image is not cached in the intermediate HDD, the free volume of the intermediate HDD is checked. If the intermediate HDD is judged not to have a free volume, images of hierarchies having large volumes are erased from ones stored the intermediate HDD in the order from lower popuralities or older access dates.

Abstract: A graphics processing system which employs one or more frame buffer memory devices is disclosed which system provides accelerated rendering of two-dimensional and three-dimensional images. One embodiment of the disclosed system comprises a rendering controller, an interface, a frame buffer memory, a rendering bus and an address and control bus.

Abstract: A data processing system has main memory and one or more caches. Data from main memory is cached while mitigating the effects of address pattern dependency. Main memory physical addresses are translated into main memory virtual address under the control of an operating system. The translation occurs on a page-by-page basis such that some of the virtual address bits are the same as some of the physical address bits. A portion of the address bits that are the same are selected and cache offset values are generated from the selected portion. Data is written to the cache at offset positions derived from the cache offset values.

Abstract: A method and apparatus for managing compressed Z information in a video graphics system is described. Pixels in a display frame are grouped into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. When possible, the Z information corresponding to the plurality of pixels in a pixel block is compressed and stored in a Z buffer in a compressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates a level of compression of the Z information for each of the pixel blocks. When Z information for a pixel block is required for processing operations, a cache is first examined to determine if the Z information for the pixel block is included in the cache. If the Z information is not included in the cache, the Z mask memory is consulted to determine the level of compression of the Z information for the particular pixel block.

Abstract: A configurable buffer has two storage areas. Depending upon a state of a buffer control signal, the two storage areas are configured to buffer a single stream of data together or to buffer two streams of data separately. In an exemplary video graphics processing application, one stream of data includes pass-through values of fragments being rendered (e.g. color, location, and/or depth values) and the other stream of data includes corresponding displaced (or otherwise perturbed) texture coordinate pairs. Such a buffer may be used to reduce the amount of buffer storage needed to support both single-pass and multipass operations in a pixel pipeline.

Abstract: A system and method capable of super-sampling and performing super-sample convolution are disclosed. In one embodiment, the system may comprise a graphics processor, a frame buffer, a sample cache, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The frame buffer, which is coupled to the graphics processor, may be configured to store the samples in a sample buffer. The samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the frame buffer, copy the selected samples to a sample cache, and filter a set of the selected samples into an output pixel. The sample-to-pixel calculation unit retains those samples in the sample cache that will be reused in a subsequent pixel calculation and replaces those samples no longer required with new samples for another filter calculation.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

Abstract: In a computer system, main memory is accessed via a cache. Locations in a main memory are accessed by a process with reference to addresses. Each address comprises virtual bits and physical address bits. Selected bits of the physical address bits identify areas in the cache. Permutations of the selected bits are used to identify buffer alignments in main memory, in response to an identification of requirements for the process.

Abstract: A method and apparatus for efficiently managing texture memory in computer graphics systems is provided. Texture images are stored in discrete memory-aligned tiles to avoid fragmentation in the texture memory. Larger texture images are divided up into smaller tiles so that they will fit in any available tile region in texture memory. Small texture images usually fit into a single tile and therefore do not usually have to be divided up. Texture images that are larger than a tile region are split up into tile-sized images that are stored individually in any available tile region of texture memory. By dividing up the larger texture images this way, the texture memory is used more efficiently because any gaps that appear in the texture memory due to fragmentation may be filled by the tile-sized images.

Abstract: The present invention relates a texture mapping system which can access texture data in parallel. The texture mapping system includes: a memory controller; a main memory storing filtered texture images; a cache memory receiving data of the texture image from the main memory, and separately storing texture data in odd-number columns and even-number columns; a texture address converter converting an address from the memory controller, and generating a read/write address of the cache memory; and an interpolator interpolating the texture data outputted from the cache memory, and forming a pixel data. Accordingly, when the texture data is mapped according to a bi-linear filtering method and the like in the three-dimensional graphic system, the cache memory is accessed as many as a half of the number of the necessary texture data, thereby improving the graphic performance.

Abstract: A 3D graphics accelerator in which vertex data is locally cached, at individual rendering subsystems, in circular buffers which are NOT large enough to hold the maximum number of data fields for the maximum number of vertices which can be parallel-processed. Instead, the circular buffers are preferably made large enough to hold the maximum number of data fields for a minimum useful number of vertices; the same buffers can also be used to hold a smaller number of data fields for the maximum number of vertices.

Abstract: This disclosure provides a system for efficiently processing a data set. More particularly, image data such as volumetric data are stored in a spread memory fashion, with image data subsets occupying only a fraction of each page. Each memory page is sized to roughly map to processor cache size (or a section thereof), such that image data is always mapped to one or more predetermined fractions of processor cache. By keeping processing parameters (e.g., look-up tables and buffers) in the remainder of cache, the system effectively locks those parameters against overwrite by the image data. This system facilitates the use of conventional workstations, laptops and other machines not enhanced for processing large or complicated data sets. It also extends capabilities of both un-enhanced and enhance machines, permitting them to process data more efficiently.