Abstract: An apparatus comprising a display in which a plurality of pixels are arranged in an array, and a generator configured to, in a first frame, generate first data corresponding to a first region of the display to display a first image in the first region of the display and, in a second frame, generate second data corresponding to a second region of the display, which includes the first region and is larger than the first region, to display a second image in the second region of the display is provided. A region of the second region is defined as a third region, a resolution of the first image and a resolution of at least the third region in the second image are different from each other.

Abstract: A display driver includes image processing circuitry and drive circuitry. The image processing circuitry is configured to receive a foveal image, a full frame image, and coordinate data that specifies a position of the foveal image in the full frame image. The image processing circuitry is further configured to render a resulting image based on the full frame image independently of the foveal image in response to detection of a data error within the coordinate data. The drive circuitry is configured to drive a display panel based on the resulting image.

Abstract: An electronic device is provided. The electronic device includes a display and a processor, wherein the processor is configured to display a multi-window in the display region of the display, identify the position of a user input, receive an input related to the size change of the display region of the display, and change the size of the display region of the display and display a window corresponding to the identified position of the user input in the display region of the display.

Abstract: A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.

Abstract: A method, an image pre-processing apparatus, and a camera system for processing large images are provided. The method includes receiving from an image sensor an image frame at an image pre-processing apparatus, the image frame having a frame pixel resolution substantially equal to a sensor pixel resolution of the image sensor, dividing the image frame into first and second image subframes to be sequentially processed by an image signal processor, each of the first and the second image subframes having a subframe pixel resolution smaller than the sensor pixel resolution and a region in which the first and second image subframes overlap with each other. The subframe pixel resolution is predetermined by a processing capacity of the image signal processor, and the first and the second image subframes are consecutively processed by the image signal processor.

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture includes multiple chips, each with a central processing element, a global memory buffer, and a plurality of additional processing elements. Each additional processing element includes a weight buffer, an activation buffer, and vector multiply-accumulate units to combine, in parallel, the weight values and the activation values using stationary data flows.

Abstract: A system and method for inserting a composited image or otherwise generated graphic into a selected video by way of a programmatic process. According to some embodiments, a system may comprise an Automated Placement Opportunity Identification (APOI) engine, a Placement Insertion Interface (PII) engine, a preview system, and an automated compositing service. The system finalizes a graphic composite into a video and provides a user with a preview for final export or further manipulation.

Abstract: Disclosed are a driving circuit, a level shifter IC and a display device. The driving circuit includes a level enhancing module, a switch module, a current detecting module and a control module, the control module correspondingly switches on the switch module or switches off the switch module according to current signal output by the current detecting module.

Abstract: A method, an image pre-processing apparatus, and a camera system for processing large images are provided. The method includes receiving from an image sensor an image frame at an image pre-processing apparatus, the image frame having a frame pixel resolution substantially equal to a sensor pixel resolution of the image sensor, dividing the image frame into first and second image subframes to be sequentially processed by an image signal processor, each of the first and the second image subframes having a subframe pixel resolution smaller than the sensor pixel resolution and a region in which the first and second image subframes overlap with each other. The subframe pixel resolution is predetermined by a processing capacity of the image signal processor, and the first and the second image subframes are consecutively processed by the image signal processor.

Abstract: Systems and methods are utilized for performing geometric multiplexing in MEMS display systems that utilize RGB laser diodes and MEMS mirrors to compensate for angular separation between the RGB light that results from passing the RGB light emitted from the RGB laser diodes through a single collimating lens shared by the RGB laser diodes, as opposed to utilizing a separate collimating lens for each corresponding laser diode. Spatial offsets between the RGB light at the target display, resulting from the angular separation, are compensated for by applying temporal buffers to the pulsing of the RGB laser sources so that the RGB light is horizontally and vertically aligned at the appropriate pixels of the target display during scanning by the MEMS mirrors system.

Abstract: The display panel includes a source line, a common voltage line, a gate line, and a pixel circuit. The pixel circuit includes a first capacitor, a first transistor, a sample circuit, and a memory circuit. The first capacitor is coupled to the common voltage line. The first transistor is coupled to the source line and the first capacitor. The sample circuit includes a second transistor, and the second transistor is coupled to the source line and the first capacitor. The memory circuit is coupled to the first transistor, the sample circuit, and the gate line.

Abstract: A processor receives input video data of a video dynamic range and input dynamic metadata. It also receives: input graphics data of a graphics dynamic range and input static metadata, display identification data from a target display over a video interface, and a blending priority map characterizing a per-pixel priority of output pixels in an image generated by blending the input video data and the input graphics data. A video mapping function and a graphics mapping function which map data from the input video and graphics dynamic ranges to the target dynamic range are generated based on the dynamic and static metadata. Then, the input and graphics data are blended based on the blending priority map and a per-pixel decision to map pixels to the target dynamic range using either the video mapping function or the graphics mapping function.

Abstract: Concepts and technologies are disclosed herein for providing and using a distributed forwarding service. A service request can be received at a computing device and can relate to a distributed forwarding service. The computing device can configure the distributed forwarding service by determining a number of nodes that are to provide the distributed forwarding service and configuring a shared control function to control the nodes. The computing device can trigger instantiation of the distributed forwarding service. Instantiation of the distributed forwarding service can include dedicating a shared incoming switch for the distributed forwarding service, dedicating a shared outgoing switch for the distributed forwarding service, instantiating the nodes, and instantiating the shared control function. The distributed forwarding service can include the shared incoming switch, the shared control function, the nodes, and the shared outgoing switch.

Abstract: The present technology relates to an image processing apparatus that reduces a memory capacity necessary for deformation processing of each frame image of a moving image. Pixel data of a first frame image being each frame image of an input moving image is written into a plurality of storage areas in a write-in order, and the pixel data of the written first frame image is read out in a read-out order, thereby generating a second frame image being the first frame image deformed. The write-in of the pixel data and the read-out of the pixel data are performed in parallel, the first frame image is divided into blocks in 2 rows×2 columns or more, the blocks are written into each of the storage area and the block to be written next is written into the storage area that becomes vacant by reading out the pixel data immediately before.

Abstract: Video recognition processing on video signals input from an outside is performed. Hence, video reception device which is configured to transmit and receive data through communication network includes input unit, video extraction unit, video recognition region setting unit, control unit and additional information display control unit. The video recognition region setting unit detects superimposing information superimposed on a partial video, and sets a video recognition region or video recognition candidate regions to the partial video based on a detection result. The additional information display control unit generates content recognition information in the video recognition region or in the video recognition candidate regions of the partial video. The control unit performs control of requesting video recognition device to perform video recognition processing on this content recognition information.

Abstract: A system on chip (SoC) includes a first display subsystem configured to perform first and second imaging functions and a second display subsystem configured to only perform the first imaging function. The SoC is configured to activate one of the display subsystems and deactivate the other display subsystem based on a comparison of a current frame of image data and a previous frame of image data.

Abstract: One embodiment of a clock synthesis apparatus can include a clock generator that can provide two or more clock waveforms. One clock waveform from the clock generator can be selected to be an output clock in accordance with an error signal determined by a difference between a level of data in a buffer and a predetermined threshold. The output clock can also be a timing reference waveform for data removed from the buffer. In another embodiment, the error signal can be determined periodically. In yet another embodiment, the output clock domain can be different from the input clock domain of the buffer.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A vector image drawing device has the following configuration. A contour generation unit (104), based on vector data, generates contour data that represents the starting pixels on a scan line in a drawing area where fill-in starts, and the ending pixels where fill-in ends. An outline buffer (106) stores the number of starting or ending pixels in the contour data for fill-in for each drawn pixel. An error judgment unit (2), when storing the contour data in the outline buffer (106), determines in which pixel there is overflow in the outline buffer of contour data. A pixel position transfer unit (3) adds the numerical value of the overflow portion of a pixel that the error judgment unit (2) determined to have overflow to the numerical value of contour data that corresponds to a pixel.

Abstract: An image processing device includes: a horizontal resolution converting unit that converts a horizontal resolution of input image data to output horizontal resolution-converted image data; a line memory for the left eye and a line memory for the right eye that store the horizontal resolution-converted image data; a line memory specifying unit that specifies the line memory to store the horizontal resolution-converted image data; a line memory reading unit that reads the horizontal resolution-converted image data from either of the line memory for the left eye and the line memory for the right eye; and a vertical resolution converting unit that converts a vertical resolution of the horizontal resolution-converted image data read by the line memory reading unit to generate output image data.

Abstract: A projector is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.

Abstract: An object is to provide an image processing circuit adaptable to displays having a variety of pixel numbers. The image processing circuit includes a data adjustment circuit, a first line memory and a second line memory capable of storing K pieces of data, an output timing control circuit, and an arithmetic circuit. To the data adjustment circuit, (X×Y) pieces of pixel data are input. Y pieces of pixel data are transmitted to the first line memory. When Y is less than K, (K?Y) pieces of dummy data are added to fill the first line memory. Then, the K pieces of data are output from the first line memory to the second line memory and a new set of K data is input to the first line memory. The arithmetic circuit stores the data input from the line memories and performs filtering.

Abstract: A method for synchronization of data over multiple panels is provided. A communications apparatus that synchronizes data across multiple displays is provided. A computer program product, comprising a computer-readable medium that synchronizes video data across multiple displays is provided. At least one processor configured to synchronize data across multiple panels is provided. The video data can be sent between the multiple panels or displays at different rates to facilitate synchronization of the data. Double buffering at each panel can allow data to be written to a first buffer and at substantially the same time data is extracted from a second buffer and written to a display.

Abstract: A display system comprises line buffer memory that stores input image data in a first color space, and a plurality of gamut mapping modules that accept the input image data from the line buffer memory and performs a gamut mapping operation to produce mapped image data specified in a second color space. The system also includes a subpixel rendering module that renders the image data specified in the second color space for display on a display panel substantially comprised of a particular subpixel repeating group. The system architecture utilizes a plurality of gamut mapping modules which in turn allows for a reduction in the size of line buffer memory needed for the subpixel rendering operation.

Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.

Abstract: Methods and apparatus for performing an inline rotation of an image. The apparatus includes a rotation unit for reading pixels from a source image in an order based on a specified rotation to be performed. The source image is partitioned into multiple tiles, the tiles are processed based on where they will be located within the rotated image, and each tile is stored in a tile buffer. The target pixel addresses within a tile buffer are calculated and stored in a lookup table, and when the pixels are retrieved from the source image by the rotation unit, the lookup table is read to determine where to write the pixels within a corresponding tile buffer.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: One embodiment of a clock synthesis apparatus can include a clock generator that can provide two or more clock waveforms. One clock waveform from the clock generator can be selected to be an output clock in accordance with an error signal determined by a difference between a level of data in a buffer and a predetermined threshold. The output clock can also be a timing reference waveform for data removed from the buffer. In another embodiment, the error signal can be determined periodically. In yet another embodiment, the output clock domain can be different from the input clock domain of the buffer.

Abstract: A position of a predetermined object or a predetermined design is sequentially detected from images. Then, an amount of movement of the predetermined object or the predetermined design is calculated on the basis of: a position, in a first image, of the predetermined object or the predetermined design detected from the first image; and a position, in a second image, of the predetermined object or the predetermined design detected from the second image acquired before the first image. Then, when the amount of movement is less than a first threshold, the position, in the first image, of the predetermined object or the predetermined design detected from the first image is corrected to the position, in the second image, of the predetermined object or the predetermined design detected from the second image.

Abstract: Real-time scanning and display of images is synchronized for ultrasound imaging. The scanning rate requirements for obtaining a frame of ultrasound data are determined. The video rate for imaging is adjusted as a function of the scanning rate.

Abstract: An apparatus and method of processing image data sub-samples image data by generating a data patch by dividing the image data into a plurality of blocks and sequentially accessing pixel data values in each of the blocks through a plurality of line memories. The image data is divided into the plurality of blocks, the blocks are stored in each of the line memories, and the pixel data values stored in each of the line memories are sequentially accessed, so as to generate the data patch for sub-sampling the image data.

Abstract: A display device changes the gradation of pixels by a write operation of applying a voltage to the pixels a plurality of times. When newly changing the display state of pixels, the display device judges as to whether or not the pixels whose display state are to be changed are in a write operation. The display device starts the writing operation for those of the pixels that are not in a writing operation, and starts a new writing operation for those of the pixels that are in a writing operation, after the ongoing writing operation is completed. If a writing operation for pixels in progress of being updated and pixels with which a writing operation is to be newly started would lead to substantially large power consumption, the start of the writing operation for the pixels with which a writing operation is to be newly started is postponed.

Abstract: A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster pattern.

Abstract: An organic light emitting display and a method of driving the same, in which a driving frequency is lowered and at the same time a production cost is reduced. The organic light emitting display includes: a display region divided into a left part and a right part; a first data driver adapted to supply a data signal to data lines of the left part; a second data driver adapted to supply the data signal to data lines of the right part; and first and second memory groups wherein, when one of the first and second memory groups stores data to be supplied to the left and right parts therein, another one of the first and second memory groups supplies data to the first and second drivers, and wherein, when one of the first and second memory groups receives a reading signal in parallel, another one of the first and second memory groups receives a writing signal in series.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A color calibrating method includes receiving a color signal wherein the color signal is associated with a set of minimum brightness voltages and a set of maximum brightness voltages, analyzing a distribution of the set of the minimum brightness voltages and a voltage distribution of the set of the maximum brightness voltages to obtain a first distribution curve and a second distribution curve, and adjusting a maximum value of the first distribution curve to a first target value and adjusting a maximum value of the second distribution curve to a second target value.

Abstract: An apparatus has at least one port to receive a data stream of image and on screen display data, an image processor to process the image data separate from the on screen display data and produced processed image data, and a display port to combine the on screen display data and the processed image data and transmit the combined data to a display. A method of processing on screen display data with an image post processor includes receiving a data stream from a video processor at a post processing device having at least one port, the data stream having both image data and on screen display data, separating the on screen display data from the image data, storing the image data and the on screen display data in separate areas of a memory, performing image processing on the image data with the post processor to produce processed image data, and transmitting the processed image data and the on screen display data through a display port.

Abstract: A display controller for displaying multiple windows and associated memory access method are provided. The display controller receives a first video source and a second video source for displaying multiple windows, and includes a line buffer, a deinterlacer, a scaler, and a memory interface unit. The line buffer buffers pixel data of a non-overlapped area of a main image associated with the first video source, and pixel data of a sub image associated with the second video source. The deinterlacer is coupled to the line buffer for selectively deinterlacing data in the line buffer. The scaler is coupled to the deinterlacer for selectively scaling data outputted from the deinterlacer. The memory interface unit is coupled to the line buffer for accessing an external memory.

Abstract: A projector of an embodiment is provided with: an input line memory which holds an input image signal corresponding to one line; an image processor which generates an intermediate image signal correction-processed according to distortion of a projection lens, using the input image signal transferred from the input line memory; an output line memory which holds the intermediate image signal corresponding to one line; and an LCOS which guides light radiated from a light source to the projection lens in accordance with the intermediate image signal. The image processor is provided with an input supplementation buffer which stores the input image signals of a plurality of lines, an input data buffer which stores input image signals required to generate the intermediate image signal corresponding to one line, and a number-of-supplementary-lines calculator which calculates the number of supplementary lines of the input image signals.

Abstract: A driving integrated circuit and methods thereof are provided. The driving IC includes a memory for driving a display panel and having a memory structure including at least one cell block, a scan register receiving data read from the memory, a source driver receiving data output from the scan register and outputting the received latched data to the panel and a switching unit establishing a connection between an activated cell block and the scan register in response to an activation of the activated cell block. One method includes performing a read operation to read data from a memory, the read operation including sensing and amplifying data stored within a memory cell, turning on a switch to increase a bit line voltage above a voltage threshold and latching the amplified data received through a line connected to the switch and transmitting the read data to the panel of the display device.

Abstract: A method and an apparatus for mirroring a frame are provided. The method is suitable for a display device having a first storage unit and a second storage unit. In the present method, pixel values of a pixel row of the frame are read from the first storage unit and written into the second storage unit. Then, the pixel values of the pixel row of the frame are read from the second storage unit and written back to the first storage unit. When performing one of foregoing reading and writing steps, the pixel values of the pixel row are read or written in a reverse direction to mirror the pixel row. Finally, foregoing steps are repeated to mirror each pixel row of the frame, so as to mirror the entire frame.

Abstract: An image display device includes a timing controller capable of overdriving. The timing controller has three line buffers, an image reverse processing unit, and an overdrive unit. The first line buffer buffers first line data of a second frame, wherein the second frame is generated later than a first frame. The second line buffer buffers first compressed data. The image reverse processing unit estimates first and second line data of the first frame according to the first compressed data. According to the first and second line data of the first and second frames, the overdrive unit outputs first and second lines of interleaving data for an interleaving frame. The interleaving frame is inserted between the first and second frames. With the third line buffer, the timing controller outputs the first and second lines of interleaving data at different time point.

Abstract: A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory.

Abstract: An image generation apparatus provides interpolation and distortion correction. The interpolation and distortion correction may be provided in one or two dimensions. Nonlinear image scan trajectories, such as sinusoidal and bi-sinusoidal trajectories are accommodated. Horizontal and vertical scan positions are determined using a linear pixel clock, and displayed pixel intensities are determined using interpolation techniques.

Abstract: An image generation apparatus provides correction for color offsets. Color offsets may be caused by misalignments in laser diodes or optics assemblies in a laser projector. The offsets may be measured during or after manufacture of the laser projector. An image buffer is responsive to the offset data to translate each color plane separately. The image buffer may include separately addressable portions for each color. Further, variable delay elements on the output of the image buffer may provide color offset correction. Interpolation provides further offset correction.

Abstract: Provided is a memory device that allows an amount of leakage into a first retaining section to which a binary logic level is written to be balanced between different circuit states. A predetermined period is set in which in a state where a first control section turns off an output element, (i) a first retaining section and a second retaining section retain an identical binary logic level, (ii) an electric potential of a voltage supply is set to one of a first electric potential level and a second electric potential level, (iii) the other one of the first electric potential level and the second electric potential level is supplied from a column driver to a fourth wire, and (iv) subsequently the fourth wire is shifted to a floating state.

Abstract: A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

Abstract: A screen display control device includes: a compression unit which compresses input image data in a line unit; a rewritable image memory to which the compressed data compressed in the line unit by the compression unit is written in non-synchronization with a reading process; a decompression unit which decompresses the compressed data periodically read from the image memory in synchronization with screen display to restore original image data; a display unit which displays an image of the image data decompressed and restored by the decompression unit; a buffer memory which temporarily maintains one-line data of the image data; and a writing/reading control unit which controls the process of writing the compressed data to the image memory and the processes of writing and reading the image data to and from the buffer memory.

Abstract: A screen display control device includes: a compression unit which compresses input image data in a line unit; a rewritable image memory to which the compressed data compressed in the line unit by the compression unit is written in non-synchronization with a reading process; a decompression unit which decompresses the compressed data periodically read from the image memory in synchronization with screen display to restore original image data; a display unit which displays an image of the image data decompressed and restored by the decompression unit; a buffer memory which temporarily maintains compressed one-line data compressed by the compression unit; and a writing/reading control unit which controls the processes of writing and reading the compressed data to and from the image memory and processes of writing and reading the image data to and from the buffer memory.

Abstract: A display device changes the gradation of pixels by a write operation of applying a voltage to the pixels a plurality of times. When newly changing the display state of pixels, the display device judges as to whether or not the pixels whose display state are to be changed are in a write operation. The display device starts the writing operation for those of the pixels that are not in a writing operation, and starts a new writing operation for those of the pixels that are in a writing operation, after the ongoing writing operation is completed. If a writing operation for pixels in progress of being updated and pixels with which a writing operation is to be newly started would lead to substantially large power consumption, the start of the writing operation for the pixels with which a writing operation is to be newly started is postponed.