For 2d Coordinate To Linear Address Conversion Patents (Class 345/569)
  • Patent number: 11893676
    Abstract: In one embodiment, a computing system may store, by first buffer blocks, texels organized into a texel array including a number of N×N texel sub-arrays. Each texel may fall within a corresponding N×N texel sub-array and may be associated with a two-dimensional sub-array coordinate indicating a position of that texel within the corresponding N×N texel sub-array. Each first buffer block of may be assigned a particular two-dimensional sub-array coordinate and stores a texel subset having the particular two-dimensional sub-array coordinate. The system may receive, by filter blocks, texels from the first buffer blocks. Each filter block may receive a texel from each first buffer block to form a corresponding N×N texel sub-array. The system may perform, by filter blocks, sampling operations parallelly on their respective N×N texel sub-arrays.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 6, 2024
    Assignee: Meta Platforms Technologies, LLC
    Inventor: Larry Seiler
  • Patent number: 10908916
    Abstract: An apparatus and method are provided for executing a plurality of threads. The apparatus has processing circuitry arranged to execute the plurality of threads, with each thread executing a program to perform processing operations on thread data. Each thread has a thread identifier, and the thread data includes a value which is dependent on the thread identifier. Value generator circuitry is provided to perform a computation using the thread identifier of a chosen thread in order to generate the above mentioned value for that chosen thread, and to make that value available to the processing circuitry for use by the processing circuitry when executing the chosen thread. Such an arrangement can give rise to significant performance benefits when executing the plurality of threads on the apparatus.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 2, 2021
    Assignee: ARM Limited
    Inventors: Timothy Holroyd Glauert, David Hennah Mansell, Rune Holm
  • Patent number: 10496409
    Abstract: Systems and methods for prioritizing executions of a plurality of instructions in a computer system (such as an embedded system) are disclosed. An instruction can be associated with a priority and an atomicity. When an instruction is fetched, the computer system can access the priority and atomicity information together with the accessing the operand and decoding the instruction. The instruction may be executed in accordance with the fetched priority and atomicity. In some situations, the plurality of instructions may be executed in parallel by multiple functional units. Some of the functional units may be the same type, and therefore allowing multiple instructions to use the same type of functional unit at the same time, without waiting for another instruction to finish.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 3, 2019
    Assignee: The Arizona Board of Regents
    Inventor: Paul G. Flikkema
  • Patent number: 9355430
    Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: May 31, 2016
    Assignee: NVIDIA Corporation
    Inventors: Eric B. Lum, Cass W. Everitt, Henry Packard Moreton, Yury Y. Uralsky, Cyril Crassin, Jerome F. Duluk, Jr.
  • Patent number: 9042657
    Abstract: An image-based georeferencing system comprises an image receiver, an image identification processor, a reference feature determiner, and a feature locator. The image receiver is configured for receiving a first image for use in georeferencing. The image comprises digital image information. The system includes a communicative coupling to a georeferenced images database of images. The image identification processor is configured for identifying a second image from the georeferenced images database that correlates to the first image. The system includes a communicative coupling to a geographic location information system. The reference feature determiner is configured for determining a reference feature common to both the second image and the first image. The feature locator is configured for accessing the geographic information system to identify and obtain geographic location information related to the common reference feature.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: Trimble Navigation Limited
    Inventors: James M. Janky, Michael V. McCusker, Harold L. Longaker, Peter G. France
  • Patent number: 8947445
    Abstract: A display controller includes a graphic memory, a graphic memory control unit and a scan control unit. The graphic memory has a storage capacity defined by a first directional size multiplied by a second directional size. The graphic memory control unit converts two-dimensional (2-D) addresses to one-dimensional (1-D) addresses based on an input clock signal and first directional total pixel number of a display panel for displaying input data, converts the 1-D addresses to physical 2-D addresses based on the first directional size and controls the graphic memory to store the input data. The display panel has a resolution corresponding to the first directional total pixel number multiplied by a second directional total pixel number of the display panel. The scan control unit increases scan addresses one line by one line to display data stored in the graphic memory according to a display resolution.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jun-Seok Han
  • Publication number: 20140253575
    Abstract: Systems, apparatus, articles, and methods are described including operations to transpose image data between a linear-type storage format and a Y-tiled-type storage format.
    Type: Application
    Filed: December 29, 2011
    Publication date: September 11, 2014
    Inventors: Yuting Yang, Guei-Yuan Lueh, Stony Shen, John R. Hartwig, Kin-Hang Cheung
  • Patent number: 8780129
    Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 15, 2014
    Assignee: Silicon Motion, Inc.
    Inventor: Frido Garritsen
  • Patent number: 8514334
    Abstract: An image display device such as an LCD television comprises a microcomputer and LUTs (look-up tables) which are tables of correction data for correcting color balance of an image to be displayed. The microcomputer recalculates correction data in the LUTs and updates the correction data to the recalculated correction data based on: an input value InL of image data of a Low side white balance adjustment image; an input value InH of image data of a High side white balance adjustment image; and a gain value GainL and a gain value GainH which are provided to the input value InL and the input value InH, respectively, to bring color balance of the Low side white balance adjustment image and the High side white balance adjustment image to a predetermined color balance, respectively.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 20, 2013
    Assignee: Funai Electric Co., Ltd.
    Inventors: Yuya Nakamura, Masahiro Suzuki
  • Patent number: 8477146
    Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: July 2, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Shuhua Xiang, Li Sha, Ching-Han Tsai
  • Patent number: 8407615
    Abstract: A system and method by which menus, displays, charts, maps and pictures may be presented to a user and very quickly seen and used in the context of a larger display without obscuring key elements of that display. Menus or other graphical displays are anchored to the sides of a solid figure, which can be rotated to display the menu panels and other textual and graphical information.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: March 26, 2013
    Assignee: Pitney Bowes Software Inc.
    Inventor: Arthur R. Berrill
  • Patent number: 8269786
    Abstract: A method for reading and writing a memory having n rows and A columns includes a first step of writing data in 0th to (n?2)th rows by a first technique; a second step of writing data in (n?1)th row per column and reading data in the 0th section by a second technique; a third step of writing data in 0th to (n?2)th sections by a third technique and reading data in 1st to (n?1)th sections by the second technique, a fourth step of writing data in the (n?1)th section by the third technique and reading data in 0th row by a fourth technique; a fifth step of writing data in 0th to (n?2)th rows by the first technique and reading data in 1st to (n?1)th rows by the fourth technique; and a sixth step of returning to the second step.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: September 18, 2012
    Assignee: Ricoh Company, Ltd.
    Inventors: ChunJie Yu, Wentao Ye, Tsuyoshi Morimoto, Hirofumi Odaguchi
  • Patent number: 8209502
    Abstract: An area detection unit detects a main rectangular area to which an access start address indicated by one-dimensional access information is included among main rectangular areas corresponding to two-dimensional access information. An address conversion unit divides the detected main rectangular area into sub rectangular areas, detects a sub rectangular area to which the access start address indicated by the one-dimensional access information is included, and converts the one-dimensional access information into first two-dimensional access information based on a relative position of the sub rectangular area being detected. A memory controller receives the first and second two-dimensional access information, and converts the two-dimensional access information into an access address. Accordingly, a modification of a memory controller accessing a semiconductor memory by receiving the two-dimensional access information becomes unnecessary.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: June 26, 2012
    Assignee: Fujitsu Limited
    Inventor: Kiyonori Morioka
  • Patent number: 7990391
    Abstract: A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventor: William Radke
  • Patent number: 7986327
    Abstract: Embodiments of the present invention set forth a technique for optimizing the on-chip data path between a memory controller and a display controller within a graphics processing unit (GPU). A row selection field and a sector mask are included within a memory access command transmitted from the display controller to the memory controller indicating which row of data is being requested from memory. The memory controller responds to the memory access command by returning only the row of data corresponding to the requested row to the display controller over the on-chip data path. Any extraneous data received by the memory controller in the process of accessing the specifically requested row of data is stripped out and not transmitted back to the display controller.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: July 26, 2011
    Assignee: NVIDIA Corporation
    Inventor: John H. Edmondson
  • Patent number: 7859541
    Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: December 28, 2010
    Assignee: NVIDIA Corporation
    Inventors: John S. Montrym, David B. Glasco, Steven E. Molnar
  • Patent number: 7822891
    Abstract: A system and method for storing a multidimensional array of data, such as a two dimensional (2-D) array of video data, in a non-contiguous memory space. The system and method maps individually indexed elements of a multidimensional array of data from a source device into blocks of non-contiguous memory available in a destination memory system, even when the destination blocks are small and/or their size does not correlate in any way to the dimensions of a source buffer. In particular, the blocks of non-contiguous memory may be as small as a single element of the data indexed in the 2-D array.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: October 26, 2010
    Assignee: Broadcom Corporation
    Inventors: Glen T. McDonnell, Martin E. Perrigo
  • Patent number: 7737986
    Abstract: The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 15, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Seigneret, Sylvain Dubois, Jean Pierre Noel, Pierre-Yves J. Taloud
  • Patent number: 7719541
    Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: May 18, 2010
    Assignee: Silicon Motion, Inc.
    Inventor: Frido Garritsen
  • Patent number: 7545382
    Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: June 9, 2009
    Assignee: NVIDIA Corporation
    Inventors: John S. Montrym, David B. Glasco, Steven E. Molnar
  • Patent number: 7525550
    Abstract: A controller driver includes a color palette circuit configured to hold color palette data indicating a relation of a color reference numbers corresponding to a color and RGB data corresponding to the color, a first memory section configured to hold first layer data containing first RGB data specifying a color of each of pixels of a first layer image; a second memory section configured to hold second layer data containing a color reference number specifying a color of each of pixels of a second layer image; a calculating circuit configured to generate synthetic image data of the first layer data and the second layer data; and a driving circuit configured to drive a display panel based on the synthetic image data.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: April 28, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Junyou Shioda, Hirobumi Furihata
  • Publication number: 20090073180
    Abstract: A graphics drawing apparatus drawing a graphic, including: a generation unit, where a sequence of two-dimensional coordinates of vertices is input, generating the coordinates of each of the vertices and virtual vertex coordinates for the coordinates of each of the vertices on a memory, the virtual vertex coordinates being generated by converting the X-coordinate value of the coordinates of each of the vertices to the X-coordinate value of the coordinates of the leading vertex of the sequence; and a setting unit that sets the coordinates of two vertices of a partial graphic that is to be created as the coordinates of two adjacent vertices, in sequence starting from the leading vertex, and, after setting the coordinates of the trailing vertex of the sequence, setting the coordinates of two vertices of the partial graphic that is to be created as the coordinates of the leading and trailing vertices.
    Type: Application
    Filed: September 12, 2008
    Publication date: March 19, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hideaki YAMAUCHI
  • Patent number: 7397477
    Abstract: A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memory in accordance with a first memory address allocation format and the memory addresses are decoded to access the addressable memory locations of a second block of memory in accordance with a second memory address allocation method different from the first memory address allocation format.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: July 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: William Radke
  • Patent number: 7154501
    Abstract: A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image, and an address correction circuit for producing a corrected X-axis address in response to the original X-axis and Z-axis address outputs from the address generator. Also included is an address selection circuit for selecting either the original X-axis address supplied from the three dimensional address generator or the corrected X-axis address from the address correction circuit as a resultant X-axis address in response to a stereo graphic mode request signal. A frame buffer address generator is provided for converting the resultant X-axis address received from the address selection means and the Y-axis address received from the three dimensional address generator into the frame buffer linear address.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: December 26, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je Man Kim
  • Patent number: 7085804
    Abstract: In a method for processing objects of a standardized communication protocol for image and data exchange between devices via a communication network by means of processing devices, the objects are converted with a conversion routine into a pure text file (plain text), can be processed in a simple command language and are subsequently converted back into the objects.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: August 1, 2006
    Assignee: Siemens Aktiengesellschaft
    Inventor: Björn Nolte
  • Patent number: 6922198
    Abstract: A color signal processing apparatus and method calculate without errors a control vector that is a driving signal of a multi-primary display (MPD) corresponding to an input color signal in order to reproduce the input color signal on the MPD using at least four primary colors. The color signal processing apparatus includes: an XYZ color signal conversion unit; a parallel processing unit that obtains a polyhedron corresponding to a color gamut of the MPD in the CIE-XYZ color space based on an MPD Forward Model, divides the polyhedron into plural pyramids, and outputs intermediate values for calculating the control vector based on the plural pyramids; a restriction condition checking unit that outputs a valid value satisfying a physical restriction condition out of the calculated intermediate values and outputs an index for a pyramid for which the valid value is calculated; a pattern arrangement unit; and a control vector arrangement unit.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: July 26, 2005
    Assignee: Samsung Electronics Co., LTD
    Inventors: Sang-Jin Lee, Moon-Cheol Kim
  • Patent number: 6784885
    Abstract: A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image, and an address correction circuit for producing a corrected X-axis address in response to the original X-axis and Z-axis address outputs from the address generator. Also included is an address selection circuit for selecting either the original X-axis address supplied from the three dimensional address generator or the corrected X-axis address from the address correction circuit as a resultant X-axis address in response to a stereo graphic mode request signal. A frame buffer address generator is provided for converting the resultant X-axis address received from the address selection means and the Y-axis address received from the three dimensional address generator into the frame buffer linear address.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: August 31, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je Man Kim
  • Patent number: 6755745
    Abstract: By using a unique display control technique, game images are provided, in which characters can be displayed in different poses with a limited-capacity memory area. Both image data corresponding to each of a plurality of blocks obtained by dividing a character to be displayed in a game image and further image data for representing different pictures in connection with at least part of the blocks are prepared. And the display pose of the character displayed in the game image is changed by switching a combination of the prepared image data. By way of example, color of at least part of the character displayed in the game image is changed on the basis of the combination of the same image data, thereby representing a plurality of types of characters. The color within the block mapped uppermost in the game image among the blocks constituting the character is kept unchanged regardless of changing of the color with respect to the remaining blocks.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: June 29, 2004
    Assignee: Konami Co., Ltd.
    Inventors: Takeshi Seto, Kuniharu Suzuki
  • Patent number: 6614443
    Abstract: A method and apparatus for mapping graphics data of a texture map into virtual two-dimensional (2D) memory arrays implemented in a one-dimensional memory space. The texture map is partitioned into 2u+v two-dimensional arrays having dimensions of 2m bytes×2n rows. The graphics data is then mapped from a respective two-dimensional array into the one-dimensional memory space by calculating an offset value based on the coordinates of a respective texel of the texture map and subsequently reordering the offset value to produce a memory address value. The order of the offset value is, from least to most significant bits, a first group of m bits, a second group of u bits, a third group of n bits, and a fourth group of v bits. The order of the offset value is reordered to, from least to most significant bits, first, third, second, and fourth groups. The resulting value produces a memory address for the one-dimensional memory space.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventor: James R. Peterson
  • Patent number: 6563507
    Abstract: Texture data containing pixel data indicating the color of a plurality of pixels arrayed in matrix fashion are stored in a texture buffer of a DRAM, and the multiple pixel data stored in the texture buffer is simultaneously accessed using a two-dimensional address (U, V) corresponding to the two-dimensional array of the plurality of pixels. The texture buffer stipulates unit blocks containing multiple pixel data to be simultaneously accessed, and stores a plurality of unit blocks making up texture data so as to be continuously positioned within a one-dimensional address space. Accordingly, the storage area of the texture buffer can be used efficiently, and further, simultaneous processing of image data of multiple pixels can be realized.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: May 13, 2003
    Assignee: Sony Corporation
    Inventor: Takeshi Ito
  • Patent number: 6476818
    Abstract: Texture data which is two-dimensional image data indicating color data of multiple pixels positioned in a matrix form is stored in a texture buffer of a DRAM, a texture engine circuit combines the bit data making up the U address of a two-dimensional address (U, V) represented by n bits (wherein n is an integer of 1 or greater) and the bit data making up the V address of the two-dimensional address (U, V) represented by m bits (wherein m is an integer of 1 or greater), thereby generating an (n+m)-bit one-dimensional address, and the generated one-dimensional address is used to access the storage circuit. Accordingly, the storage area of the texture buffer can be used efficiently with a small circuit configuration.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: November 5, 2002
    Assignee: Sony Corporation
    Inventor: Takeshi Ito