Abstract: A screen-off display method includes: in response to a screen-off trigger operation, compressing image data of at least two images to be displayed and storing the compressed image data in the memory; and controlling the display screen to display images according to the image data in the memory.

Abstract: An image processing apparatus includes: a working storage section in which computer graphics description data of a storage format in which a computer graphics material can be edited are developed so as to be used for production of an image; an updating controlling section adapted to control a writing operation into part of the working storage section in accordance with derivative information representative of information which describes control for the stored contents of the working storage section; and an image production section adapted to produce a computer graphics image based on the stored contents of the working storage section.

Abstract: Concurrent display of graphic content on multiple displays is described. A frame of graphic content to be displayed on multiple displays can be written to a single memory location. Previously written graphic content can be read to multiple displays having misaligned synchronization signals and new graphic content can be written to a different memory location concurrently.

Abstract: A method of driving an electrophoretic display device includes changing the gradation level of image data on the basis of correction data corresponding to the gradation level, converting image data with the changed gradation level to a dithering pattern, in which the first color and the second color are combined, corresponding to the changed gradation level for each predetermined region of image data, and driving the electrophoretic particles of the first color and the electrophoretic particles of the second color on the basis of image data converted to the dithering pattern for the plurality of pixels in the display section.

Abstract: Methods and apparatuses for accessing data within programmable graphics hardware are provided. According to one aspect, a user inserts special log commands into a software program, which is compiled into instructions for the programmable graphics hardware to execute. The hardware writes data to an external memory during runtime according to a flow control protocol, and the software driver reads the data from the memory to display to the user.

Abstract: An application-switching program displays representations of applications, for example icons, on a screen of a device. As a user of the device navigates between the representations, a screen of the application to a representation of which the user has currently navigated is shown in the background of the display.

Abstract: Disclosed is an image processing apparatus for inputting a plurality of rectangular images each composed of n×n pixels and outputting line-by-line image data in which one line is composed of n×n×m pixels. A line buffer stores n lines of image data, each line is composed n×n×m pixels. The apparatus generate a write address for writing a rectangular image to the line buffer memory and a read-out address for reading line-by-line image data out of the line buffer memory, and changes over a method of generating the write address between a first write-address generating method and a second write-address generating method whenever m rectangular images are written to the line buffer, and changes over the read-out address between a first read-out-address generating method and a second read-out-address generating method whenever n lines of image data are read out of the line buffer.

Abstract: A flat display device has a circuit configuration in which a division-driving system and an aspect conversion are integrated with each other, and performs driving appropriate to achieve higher resolution even in driving a display unit. The device comprises a memory circuit which includes n unit memories each storing unit data, a display unit of which the horizontal driver is supplied signals read from the memory circuit and of which the regions divided into a plurality of portions in a horizontal direction is division-driven, and a memory control circuit which divides a digital video signal of one line into n, supplies n pieces of the unit data to the n unit memories, selects each direction of write or read addresses of the n unit memories, and outputs the read addresses so that the arrangement order of the unit data for the adjacent regions is set in an inversion horizontal direction.

Abstract: A signal processing circuit includes: multiple digital-signal processing units operating in parallel each including a selecting unit for selecting one of multiple systems of input picture signals, a double-speed converting unit for writing the data equivalent to one field of the picture signal selected by the selecting unit in field memory, and simultaneously reading the data equivalent to one field from the field memory twice at double speed, thereby converting the frequency of the picture signal into double speed, a reading unit for reading the picture signal converted into double speed by the double-speed converting unit and temporarily stored in line memory, and a correction processing unit for subjecting the picture signal read by the reading unit to predetermined correction processing; and a control unit for performing the selection control of the multiple systems of picture signals, and the read position control of a picture signal from the line memory.

Abstract: A video compression circuit including a video pre-processor, a macroblock data storage unit and a video processor is provided. When fulfilled by an input video signal, the video pre-processor converts the input video signal to generate a macroblock data. The macroblock data storage unit alternatively and temporally stores the macroblock data generated from the video pre-processor. The video processor alternatively reads the macroblock data stored in the macroblock data storage unit, and compresses the readout macroblock data to an output video signal.

Abstract: A method for reading and writing a memory having n rows and A columns includes a first step of writing data in 0th to (n?2)th rows by a first technique; a second step of writing data in (n?1)th row per column and reading data in the 0th section by a second technique; a third step of writing data in 0th to (n?2)th sections by a third technique and reading data in 1st to (n?1)th sections by the second technique, a fourth step of writing data in the (n?1)th section by the third technique and reading data in 0th row by a fourth technique; a fifth step of writing data in 0th to (n?2)th rows by the first technique and reading data in 1st to (n?1)th rows by the fourth technique; and a sixth step of returning to the second step.

Abstract: This is a computer-readable portable storage medium which is used by a computer managing a plurality of frame buffers and which stores a program enabling the computer to execute a process, and the process comprises preparing an area in which data of a valid chain indicating a connection among frame buffers storing valid image data of the plurality of frame buffers and data of a vacant chain indicating a connection among frame buffers storing no valid image data, is stored, on memory and generating/updating data of the valid chain and the vacant chain when valid image data is stored in one of the plurality of frame buffers and storing it in the memory.

Abstract: An image processing apparatus includes a signal input mechanism, a signal output mechanism and a control device. The control device controls a writing of data received from the signal input mechanism and outputs the data to a plurality of digital signal processors for image processing through the signal output mechanism. The control device includes a decision mechanism and a write administration mechanism. The decision mechanism is configured to decide data to be written to the plurality of digital signal processors. The write administration mechanism is configured to administrate writing operations of the data decided by the decision mechanism to be written relative to the plurality of digital signal processors.

Abstract: A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: Method for reversing a video signal having sequences of n elements comprises the steps of writing the n elements of a first sequence into memory locations of a memory in a non-reversed order and reading out the memory locations in a reversed order, and in a subsequent step, writing the n elements of a second sequence into the memory locations in a reversed order and reading out the memory locations in a non-reversed order. The memory locations are readout from the memory in particular one element ahead of the write locations of the memory. A method of this kind can be used in particular in a television camera comprising a lens unit, which is designed for film applications.

Abstract: A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory address engine with the initializing parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.

Abstract: A storage device comprises a plurality of memory blocks each including a plurality of cells in correspondence with a data length of image data consisting of a plurality of pixel data, wherein a specific number of cells are simultaneously selected in order to commonly store a specific number of pixel data, each having a same value, which consecutively emerge in the image data. That is, they are defined between a first address and a second address, which is produced by adding run-length data representing the specific number of the first data consecutively repeated in the image data to the first address. Herein, the specific number of cells are limited within a specific storage unit, consisting of a predetermined number of cells, even though the first address and/or the second address is set outside of the specific storage unit.

Abstract: A system and method of maintaining a gradient in a plurality of pixels of a graphics display, such as a color or intensity gradient, where each pixel has an X coordinate, Y coordinate, and other pixel data that includes a fast-clear bit The pixels are filled on the display to create a gradient based upon the X or Y coordinates of the pixels, or a combination thereof, and when performing a pixel data operation, such as a read operation, the pixel data for a pixel with an activated fast-clear bit is ignored.

Abstract: An image processing apparatus for converting image data between a raster format and a block format including an image data processor for providing the image data including a luminance component and at least one chrominance component in the raster format, at least two FIFO memories for storing corresponding image data components, a multiplexer for multiplexing the image data components from the at least two FIFO memories, a line buffer memory for storing outputs of the multiplexer linearly, and an image compressor for receiving the image data components in block format in sequence from the unified line buffer memory and compressing the received image data components. The image processing apparatus may also include an address generator for generating a common read/write address for the line buffer memory.

Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.

Abstract: In general, the invention is directed toward a device for processing digital video data, such as an encoder, a decoder or an encoder/decoder (CODEC). The device makes use of an innovative architecture in which functionality is partitioned between an embedded processor, a digital signal processor and dedicated hardware to achieve increased performance. In addition, the device includes a programmable video direct memory access (VDMA) controller to retrieve video data from memory in response to a command specifying a multidimensional block of video data.

Abstract: An image display system comprises: a transmission device (PC) 10, for transmitting image data upon receiving a drawing command from an OS or an application; and a receiving monitor 40, for displaying, on a high-resolution panel 41, image data received via a monitor cable 39, wherein the transmission device 10 includes a drawing command analysis device 20, for detecting an area on a screen wherein the content is changed by the drawing command, and for employing the detected area to calculate an area to be transmitted, and a graphics card 12, for transmitting a packet that includes the calculated area to be transmitted, and control data provided as header data for the area to be transmitted, and wherein the receiving monitor 40 includes a packet reception device 50, for analyzing the header data in the received packet and for, based on the header data, rendering image data in an internally provided frame memory.

Abstract: A method, apparatus and computer program product for parallel execution of primitives in 3D graphics engines. It includes detection and preservation of dependences between graphics primitives with the ability to execute multiple independent primitives concurrently while preserving their ordering because the architecture of the graphics engine for the present invention further provides concurrent resources for parallel execution. In a first preferred embodiment, primitives are executed in parallel using an in-order dispatch unit capable of detecting dependencies between primitives. In a second preferred embodiment, an out-of-order dispatch unit is used such that not only are primitives executed concurrently; but, the primitives may be executed in any order when dependencies are detected.

Abstract: A memory management apparatus and method for protecting an image tearing in the video system. The memory management apparatus includes a scaler that converts the format of input image data into a suitable format to fit the resolution of a display, a first memory, in which the format-converted image data is written, or from which the format-converted image data is read, and a second memory which is substituted for the first memory, so that addresses for reading or writing do not overlap addresses for writing or reading, respectively, due to a difference between a data reading rate and a data writing rate.

Abstract: In the present invention, map data managed in different formats in different geographic information systems is converted into raster data and subjected to various kinds of processing to produce raster layers for freer use of the map data, such as processing and editing of the map data. A server as a map display device of the present invention has a control section. The control section controls to adjust, on the basis of attribute data, a scale and size of image data, which is stored in a storage section, in accordance with functions of an application program, to produce a plurality of raster layers, and superimpose the plurality of raster layers, and then display a map on a display section.

Abstract: In order to reduce the power consumed by the circuit when the image data is transferred to a memory in a display means, a write region detecting means 8 is provided to detect the address region in the graphics memory 2 accessed for writing by the image data writing means 1, and only such data that is within the region including the addresses accessed by the writing means 1 is transferred to the memory 5 in the display means 4. The region including the accessed addresses may for example a rectangular region of from the minimum vertical direction address to the maximum vertical direction address Y among the accessed addresses, and from the minimum horizontal direction address to the maximum horizontal direction address among the accessed addresses.

Abstract: An image processing apparatus includes a memory circuit, one-line judging circuit, a write control circuit and a read control circuit. The memory circuit stores an input data in response to a write address and outputs an output data in response to a read address. The one-line judging circuit receives a horizontal synchronization signal and a sampling clock signal and compares a number of pixels sampled within one line of the horizontal synchronization signal with a predetermined number so as to output a comparison signal and a difference signal representing a difference between the sampled number and a predetermined number. The write control circuit generates the write address in response to the clock signal and the comparison signal, and a read control signal in response to the comparison signal. The read control circuit generates the read address in response to the write address, the read control signal and the difference signal.

Abstract: A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.

Abstract: Embodiments of the present invention are directed to a method and apparatus for hardware acceleration of graphical fill in display systems. In one embodiment, a bit-mask is maintained. The bit-mask, termed the “filled color bitmap”, has one bit for each pixel of the display data. A register, termed the “filled color register”, capable of storing a single color value is maintained. When a write command is executed to fill a portion of the display memory with the same value that is stored in the filled color register, the bits in the filled color bitmap corresponding to the portion of display memory are set equal to 1. In executing other writes, the value is written to display memory and the bits in the filled color bitmap corresponding to the portion of display memory are set equal to 0. In one embodiment, the bitmap is located in a dynamic random access memory (DRAM).

Abstract: A screen driver for a liquid crystal display screen includes an internal animation circuit for displacing data on a screen. The animation circuit also process data, such as modifying data between a source address and a destination address of a RAM memory. The RAM memory contains a screen memory and a buffer memory. The internal animation circuit allows relief of an external central microprocessor of equipment having the liquid crystal display screen from corresponding processes. Further, the number of data exchanges between the microprocessor and the screen driver is reduced and thus the power consumption of the equipment caused by the screen animations is also reduced.

Abstract: Imaging apparatus having a video memory function includes a video memory having a plurality of read ports and a capacity of storing images in two fields or more, wherein CCD storage sensitivity enhancement means is connected to a write port; a write control circuit for storing a single-field image in each memory area provided by dividing the storage space of the video memory into a plurality of sub-spaces; a plurality of read control sections for reading a single-field image stored in each memory area; and memory control means for reading an image from the video memory by a delay amount corresponding to the timing of a synchronization signal from the CCD storage sensitivity enhancement means. This configuration allows adjustment of the delay amount and prevents an image write address from passing by an image read address so that image data given CCD storage sensitivity enhancement is processed normally.

Abstract: An image data processing apparatus capable of performing processing at a high speed comprising a DRAM for storing display data including a plurality of first pixel data respectively indicating colors of a plurality of pixels arranged in a matrix and able to be simultaneously written with a plurality of first pixel data. Memory controllers are provided with a plurality of pixel data generation circuits provided corresponding to the plurality of first pixel data to be simultaneously written for performing color blending using the second pixel data and the third pixel data for blending a color indicated by corresponding second pixel data and a color indicated by third pixel data stored in the write address by a predetermined blending ratio to generate a new color so as to generate the first pixel data indicating the new color.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: The present invention relates a texture mapping system which can access texture data in parallel. The texture mapping system includes: a memory controller; a main memory storing filtered texture images; a cache memory receiving data of the texture image from the main memory, and separately storing texture data in odd-number columns and even-number columns; a texture address converter converting an address from the memory controller, and generating a read/write address of the cache memory; and an interpolator interpolating the texture data outputted from the cache memory, and forming a pixel data. Accordingly, when the texture data is mapped according to a bi-linear filtering method and the like in the three-dimensional graphic system, the cache memory is accessed as many as a half of the number of the necessary texture data, thereby improving the graphic performance.

Abstract: In a data transfer circuit, a hold signal generating circuit generates and outputs a hold signal Hold when transmission data is equal to transmission data one cycle before, and sets a 3-state output buffer for transmission data to high-impedance state, while, in a data reception circuit, when the hold signal Hold is valid, a data reception circuit outputs the reception data held, thereby power consumption in a data bus which is terminated with a terminal resistor is reduced.

Abstract: A display memory (15) for a display system (10, 20) having a spatial light modulator (SLM) (16). The memory (15) receives data in pixel format and delivers the data to the SLM (16) in bit-plane format. The memory (15) avoids the need for double buffering by reading out bit-planes that are comprised partly of data from one data from and partly of data from an adjacent data frame.

Abstract: A method of digital image storage utilizing a number of image storage memories, utilizing separate and independent write and read controls to the storage memories, utilizing write masking to selectively write to the storage memories, utilizing full or partial read from the storage memories to simultaneously access corresponding image data from multiple images, while permitting a non-integral number of image delays between input and output.