Abstract: A method and means for converting a high resolution machine monitored phoiode array, comprising staircased linear sets of detectors operating in a time-delay-integration mode, to a low resolution visually monitored array, by delaying the output signal of odd sets in the staircase by the time required to scan one set and integrating the outputs of odd and even sets.

Abstract: A chip set containing an infrared detector array and two signal processors are located on the focal plane of an infrared detecting system. Included in the processors is time delay and integrate circuitry for improvement of the signal-to-noise ratio of the detector outputs before further processing, remote to the focal plane. The time delay and integrate circuitry is comprised of a number of bucket brigade devices which are situated to form a parallel-input serial shift register. Detector column input signals are decoded and the appropriate detector signal loaded into the correct port on the shift register, so that correlated signals are summed as they move through the register.