Abstract: System and method to achieve high resolution and sensitivity from scanned focal plane array detectors without generating objectionable articfacts by scanning a scene in alternate odd and even channels at a predetermined scanning rate to provide a plurality of equally time spaced samples in each channel, offsetting the samples in the even channels relative to the odd channels to be time spaced intermediate adjacent samples of the odd channels, forming a plurality of odd TV lines, each of the odd lines composed of the samples from a different one of the odd channels and the interstices between the samples in each of the odd lines being composed of a sample which is a function of the samples abutting each of the interstices in the odd lines, forming a plurality of even TV lines, each of the even lines composed of the samples from a different one of the even channels and the interstices between the samples in each of the even lines being composed of a sample which is a function of the samples abutting each of the
Abstract: A method and means for converting a high resolution machine monitored phoiode array, comprising staircased linear sets of detectors operating in a time-delay-integration mode, to a low resolution visually monitored array, by delaying the output signal of odd sets in the staircase by the time required to scan one set and integrating the outputs of odd and even sets.
Type:
Grant
Filed:
June 17, 1992
Date of Patent:
June 21, 1994
Assignee:
The United States of America as represented by the Secretary of the Army
Abstract: A chip set containing an infrared detector array and two signal processors are located on the focal plane of an infrared detecting system. Included in the processors is time delay and integrate circuitry for improvement of the signal-to-noise ratio of the detector outputs before further processing, remote to the focal plane. The time delay and integrate circuitry is comprised of a number of bucket brigade devices which are situated to form a parallel-input serial shift register. Detector column input signals are decoded and the appropriate detector signal loaded into the correct port on the shift register, so that correlated signals are summed as they move through the register.