Abstract: An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the same period as that of the horizontal synchronous signal (HBK) of the digital video signal, the signal (EXT_H) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video; and means for generating a signal (EXT_F) having the same period as that of the frame synchronous signal (FRM) of the digital video signal, the signal (EXT_F) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video. The generated signals (EXT_F) and (EXT_H) are outputted as an external frame timing signal and an external horizontal timing signal of an external synchronous signal.

Abstract: A timing signal transferring circuit (10) that may be arranged to stably transfer a timing signal (S1) between two video signal processing circuits that may operate at different clock frequencies has been disclosed. A first timing signal (S1) may be received from a pre-stage video processing circuit (13). The first timing signal (S1) may be synchronous with a pre-stage system clock (C1) and may be set to the vicinity of a center of a screen by a video signal. A second timing signal (S2) may be generated on the basis of first timing signal (S1) and transferred to a post-stage video signal processing circuit (14). Second timing signal (S2) may be synchronous with a post-stage system clock (C2). In this way, a disturbance or distortion of a video on a screen due to a difference in system clock frequency affecting a video signal in the post-stage circuit may be reduced or eliminated.

Abstract: A synchronization signal generating apparatus and method in which an input circuit is inductively coupled to an alternating current signal line. The input circuit generates a rectified signal. A switch has a switch input and a switch output in which the switch input is electrically connected to the input circuit and is enabled when the voltage of the rectified signal is greater than a predetermined voltage and is disabled when the rectified signal voltage is less than the predetermined voltage. A pulse generating circuit has a pulse generating circuit input and a pulse generating circuit output. The pulse generating circuit input is electrically connected to the switch output. The pulse generating circuit generates a pulse each time the switch is enabled. The synchronization signal generating apparatus is used in a synchronized television display system to signal a video switch to switch the video signal generated by a camera to a monitor based on the occurrence of the synchronization signal.

Abstract: Disclosed is a video signal processing apparatus comprising a plurality of line memories to which in sequence input video signal data is written on a line-by-line basis; a timing controller for controlling a timing to write video signal data to the plurality of line memories and a timing to read video signal data from the plurality of line memories; a computation output portion for computing video signal data read from the plurality of line memories and outputting video signal data differing in resolution which is determined by a pixel count in the horizontal direction and a line count in the vertical direction; and a line controller which vary the pixel count in specified lines of video signal data obtained from the computation output portion, depending on a conversion rate of the video signal data resolution.

Abstract: A false DE rejection system is described. DEs are ignored during a programmable vertical lockout period. Internal timing is used during the vertical lockout period to count the number of vertical lines to ignore. The first DE received after the vertical lockout period signifies the start of the next graphics frame. Default video is output during the vertical lockout period. The TCON is synchronized to the start of the graphics frame. A horizontal line length timer measures the timing for the horizontal line length. The horizontal line length timer may also keep a moving average of all of the lines that it has measured. This helps to ensure that the TCON does not get out-of-sync with the input stream during the vertical blanking periods. The DE rejection system includes automatic blanking detection that ignores DEs that occur after the end of a predetermined graphics frame. The vertical lockout does not occur until there has been no DE for an entire line.

Abstract: A display timing generator is provided for selecting line types and providing synchronization timing signals for video signals. The display timing generator provides programmability for the user to select line types for a frame to be displayed on a display. The line types defining rise and fall times, synchronization shapes, blanking levels and horizontal and vertical timings for providing a desired display format to different display types. A plurality of programmable parameters for pulse width, horizontal timing and voltage amplitude allow a user to define timing variations associated with a given line type. The display timing generator also includes a generic mode for allowing a programmer to select line types for particular groupings of lines.

Abstract: A mask circuit masks a digital video signal so that a video signal of an analog video signal is not outputted for a predetermined period after the start of output of a horizontal synchronizing signal of the analog video signal. A period of masking the digital video signal by the mask circuit is set in a control register, and the control register transmits the masking period to the mask circuit. A digital video signal to analog video signal converting unit converts the digital video signal masked and outputted from the mask circuit into an analog video signal. Thus, by setting in the control register the period of masking the digital video signal until the video signal of the analog video signal is stabilized, a digital video encoder can output a stable video signal.

Abstract: A main control device, to which instructions for image recording from a dynamic-image terminal are transmitted, gives instructions for accumulation processing of dynamic-image information to a dynamic-image information processing device to transmit instructions for regeneration processing of dynamic-image information to the device dynamic image information processing by instructions for regeneration from a dynamic-image terminal, and to transmit to an accumulation control device instructions for transmitting regenerated dynamic-image information. The dynamic-image information processing device affixes synchronous information to accumulated dynamic-image information transmitted from the dynamic-image terminal by instructions for transmitting accumulated dynamic-image information to transmit it to the accumulation control device.

Abstract: Process for mobile reception of television signals in which an output signal (SA) is derived from n different (S1 . . . S5) and is supplied to the reproduction part of the receiver, the n input signals (S1 . . . S5) being weighted, the output signal (SA) being formed by summing of the weighted input signals, and the quality of each of the n input signals (S1 . . . S5) being evaluated using at least one given criterion for determining the adaptively determined weighting factors, characterized in that the n input signals (S1 . . . S5) are time-synchronized before their evaluation, summing and weighting, and the horizontal and/or vertical video synchronization pulses contained in the input signals (S1 . . . S5) are used for control of time synchronization.

Abstract: A video processing system and method are provided for generating clock and timing signals from an incoming video signal. The system includes a timing reference circuit for generating a reference clock signal, a video format detector coupled to the reference clock signal and to synchronization data derived from the incoming video signal for generating a format signal indicating the format of the incoming video signal, and a clock and timing generator circuit coupled to the format signal and the reference clock signal for generating clock and timing signals that emulate the incoming video signal, and may be locked to the incoming video signal.

Abstract: Moving image signal decoder section decodes the moving image bit stream and the time stamp for reproduction transmitted from multiple separator section on a frame by frame basis and stored in input buffer and provides time control section with the time stamp for reproduction that corresponds to the decoded frame and the information on the time stamp in the header of the moving image bit stream, while storing the decoded image data in frame memory. The time control section transmits a request to image output section for outputting image data at the time specified by the time stamp for reproduction as transmitted from the moving image signal decoder section or at the time as determined on the basis of the time stamp of the moving image itself and causes the image data to be read out of the frame memory and displayed on the LCD.

Abstract: A method for clock recovery comprises a series of steps to be performed in a decoder to adaptively estimate the ratio P/S of the frequency of an encoder system time clock and the frequency of a decoder. The steps include performing a series of overlapping trials N which calculate time differentials dP(n), dS(n), respectively) between selected pairs of temporally separated clock references CRs and arrival times STCs. Each trial concludes by calculating an estimated ratio X according to the formula: X(N)=(&Sgr;dP(n))/(&Sgr;dS(n)) A preferred embodiment of the present invention also includes the step of adjusting the decoder clock in accordance with a damped version of the estimate, thereby “recovering” the encoder STC in the decoder.

Abstract: In accordance with one embodiment of the invention a spread spectrum pixel clock signal is generated to spread out the frequency bandwidth within which the peak emission of an electromagnetic interference signal occurs, so as to decrease the peak electromagnetic emission level. In one embodiment of the invention, this objective is accomplished by employing the horizontal synchronization signal of a video image to generate a periodic waveform that modulates the pixel clock reference input, such that clock signal pulses are spread out within each scan line. The modulation signal is synchronized with the horizontal synchronization signal such that each pixel location remains consistent in the horizontal and time domain.

Abstract: A standard signal processing apparatus for a digital display that is adaptive for a digital display device. In the apparatus, a synchronizing signal/image signal separator separates an input signal into a composite synchronizing signal and image signals. A synchronizing signal separator separates the composite synchronizing signal into horizontal and vertical synchronizing signals. A clock generator generates a clock signal using any one of the horizontal synchronizing signal and the composite synchronizing signal. A display receives the clock signal, the image signals and the horizontal and vertical synchronizing signals to display a picture.

Abstract: A video timing system and method. The method typically includes receiving from an input video stream an input video field in a video buffer, transmitting an output video field from the video buffer to an output video stream, measuring a time interval between a predetermined point on the input video field and a predetermined point on the output video field, and altering timing of the output video stream where the time interval is outside a predetermined range.

Abstract: A method and apparatus for synchronizing multiple signals is provided. The method and apparatus utilize the timing information of one of the multiple signals as a reference clock for synchronizing multiple signals. The method and apparatus utilize selectively gating the clocks of the other signal processing chains in order to allow control by the reference clock.

Abstract: A timing recovery device in a digital television receiver using a VSB system is disclosed. In the present invention, the timing recovery device independently determines whether the detected hsync signal is reliable and operates if the detected hsync signal is reliable.

Abstract: A clock generating device for use in a digital video apparatus generates display clock matching an input video format. The clock generating device generates a clock of a frequency which is a predetermined number of times greater than the clock necessary for displaying video signals having a respectively different format, frequency-divides the generated clock, phase-locks the obtained stable frequency and supplies corresponding display clock. Video signals of a respectively different format can be displayed into a single display format, to thereby provide an effect of displaying a video signal without degeneration of a picture quality.

Abstract: A deflection apparatus capable of generating a stable deflection pulse in a deflection output circuit even when turning on the power source or changing over the frequency of horizontal synchronizing signal is disclosed. A pulse width modulation (PWM) controlled power supply circuit generates a supply voltage for obtaining a desired horizontal amplitude depending on the frequency of horizontal synchronizing signal. The PWM voltage controller discriminates the frequency of horizontal synchronizing signal, and controls the output voltage of the PWM controlled power supply circuit. An oscillation frequency switching controller discriminates the frequency of horizontal synchronizing signal, and outputs a frequency changeover signal to an oscillator so as to be an optimum oscillation frequency depending on the output voltage of the PWM controlled power supply circuit.

Abstract: A coded signal synchronizing device includes a first and a second signal synchronizing circuit. The first and second signal synchronizing circuits respectively feed a first and a second coded signal to a coded signal processor while synchronizing them to each other in accordance with a reference synchronizing signal. A synchronization control circuit compares the phases of frame synchronizing signals output by the decoding of the coded signals and the phase of the reference synchronizing signal. So long as a phase difference between either one of the frame synchronizing signals and the reference synchronizing signal lies in a preselected range, the synchronization control circuit reads the coded signal sequentially stored. If the phase difference is smaller than a first preselected value, the synchronization control circuit repeatedly reads an I (Intra-coded) picture two times.

Abstract: In a synchronization control circuit according to the present invention, an image can smoothly be switched to another without distortion due to switching between sync signals to be displayed. The phases of sync signals of input video signals A and B are compared with each other in a phase difference detecting section, and the sync signal of one (B) of the signals is matched with that of the other signal A. When signal A is switched to signal B, an image is displayed in response to the corrected sync signal of signal B (corresponding to the sync signal matched with that of signal A). As a result, the synchronization state of signal A is maintained on a display screen, and the image can smoothly be switched without distortion.

Abstract: A method and system for synchronizing modules associated with audiovisual devices, generally for use with a digital non-linear editor. A logical clock communicates information, including time and state (clock operating mode) information, to hardware and software modules through a synchronization port. The synchronization ports convert the time information into values recognizable by the module, and offset the time as needed to maintain synchronization. The state information may effect module commands for controlling audiovisual devices, such as rewind, playback and capture commands to tape players, timed such that various devices having different preparatory timing requirements are synchronized. State information, such as information indicating that a device is ready, may be returned by the modules. Video editing features such as scrubbing, looping and frame-stepping are supported by the mode information that is communicated between the clock and the synchronization ports.

Abstract: A signal production circuit for producing a control signal used in a driving and controlling circuit of a display device externally input to the driving and controlling circuit, using an external interface signal. There is a vertical synchronization signal having a predetermined frequency and a reference clock signal in synchronization with the vertical synchronization signal. The signal production circuit includes: a first counter circuit for counting a number of reference clock signal pulses up to a value of a parameter which is preset based on a time interval of one cycle of the vertical synchronization signal and a predetermined target period.

Abstract: In a sound-picture synchronous compression device, the picture compression process is performed on a designated amount of picture codes. Then, a necessary amount of sound codes is calculated on the basis of a time of the picture compression process and is subjected to sound compression process. Consequently, compressed picture codes and compressed sound codes are transmitted to a sound-picture synchronous reproduction device. Herein, the picture reproduction process is performed on a designated amount of the compressed picture codes. Then, a necessary amount of the compressed sound codes is calculated on the basis of a time of the picture reproduction process and is subjected to sound reproduction process. Thus, the device reproduces the picture codes and sound codes, based on which pictures and sounds are output by the monitor and speaker respectively.

Abstract: A sync signal processing device for a combined video appliance capable of directly processing a personal computer (PC) signal through a television (TV) receiver circuit to achieve the horizontal and vertical driving and deflection. The device can prevent the vertical trembling phenomena of the displayed picture and on-screen display by compensating for the sync frequency difference between the PC signal and the TV signal. According to the devices either a TV sync signal or a PC sync signal is selected in accordance with a selected TV/PC mode after the PC sync signal is frequency-converted and the selected PC sync signal is processed through the TV sync signal processing circuit. Either the horizontal driving pulse signal form the TV sync signal processing circuit or the horizontal driving pulse signal produced from a separate horizontal oscillation circuit is selected and outputted to a horizontal output circuit in accordance with the selected TV/PC mode.

Abstract: A signal transmitting-receiving system which has a signal transmitting side system constructed by signal transmitter T1, voice processor T2 and signal receiver T3 and also has a signal receiving side system constructed by signal receiver R1, synthesis circuit R4, signal transmitter R5 and delay circuit R3. The signal transmitting-receiving system is constructed such that no processing for making a video signal coincide with a voice used in communication using voices in position on a time axis is performed.

Abstract: A phase locked loop for synchronizing decoding clocks with encoding clocks in a Moving Picture Experts Group (MPEG) system. The phase-locked loop circuit includes a voltage controlled oscillator for converting a decoding clock into an encoding clock, a register unit for storing multiplexing program clock reference signals, each input with a desired number of bits, a counter being initialized by a first program clock reference signal output from the register unit, thereby generating a local program clock reference signal, and a phase error control unit for combinationally operating the program clock reference signal stored in the register unit and the local program clock reference signal, thereby generating a phase error signal for controlling the voltage controlled oscillator.

Abstract: The transmitting device latches the time of the absolute clock when the V-sync signal of the video signal block is transmitted, adds to the latched time a predetermined delay time equivalent to the sum of the time required for the transmitting device to process the video signal block and the time required for the transmittance; and transmits the resulting sum value together with the video signal block. The receiver extracts the sum value and produces the V-sync signal delayed by said predetermined delay time.

Abstract: The invention pertains to a digital video horizontal synchronization pulse detector and processor comprising pulse detector for generating a timing pulse in response to each horizontal synchronization pulse. A sync position error device generates a time position error signal for each timing pulse relative to a corresponding window pulse. A window pulse generator generates the window pulses and limits the time position error signals to a maximum value. An acquisition device tracks when the timing pulses occur inside and outside the corresponding window pulses. An averaging device averages the time position error signals to generate an average error signal.

Abstract: An automotive video display of a scene from a camera has a graphics window to display vehicle information. A video graphics controller has a programmable synchronous generator for the graphics window which is synchronized or gen-locked with the camera or external video signal. A digital sync separator provides digital external sync signals. A start circuit monitors the external sync signals to detect the start of a video frame and starts the sync generator which is initially in synchronism with the external signal. A phase locked loop maintains the synchronism. A crystal oscillator circuit includes an inductor and a varactor which is tuned to vary the oscillator frequency enough to track the external video signal.

Abstract: An information signal editing system comprises a plurality of information signal editing apparatuses and a network for interconnecting the plurality of information signal editing apparatuses and providing a bidirectional communication capability to transfer information signals between the editing apparatuses. Each editing apparatus edits at least one of a plurality of information signals entered asynchronously, the information signals containing synchronization information. Each editing apparatus is composed of a synchronization information detecting section and an editing section. The synchronization information detecting section detects the synchronization information from the entered information signals. The editing section performs editing processing on at least one of the entered information signals based on the synchronization information detected by the synchronization information detecting section.

Abstract: A high resolution digital phase detector adapted to receive a threshold value and a sequence of digital samples of a substantially linear portion of an analog video signal. A first output signal is provided when a digital sample is detected as having crossed the threshold value. An interpolation is done between the value of the digital sample to first cross the threshold value and the immediately preceding digital sample on the opposite side of the threshold value. In such manner, the time of the crossing within the sample interval is resolved to a subpixel level. A second output signal represents a fractional phase error between the actual crossing and a desired crossing point within the sample interval. The first and second signals are added in a phase locked loop to adjust the output of a voltage controlled oscillator to be synchronized to the incoming analog video signal in both integer and subpixel phase.

Abstract: A video camera in which an output signal from a solid-state image sensor is converted into the corresponding digital signal at the horizontal reading cycle of the output signal, and the digital signal is digital-processed with a first predetermined clock (fs) synchronous with the reading cycle to provide a luminance signal and a color difference signal.