Abstract: A communications network controller module for storing media data in memory is disclosed. The module comprises a media access controller and a message handler. The message handler is configured, in response to receiving a frame comprising frame data from the media access controller, to identify a frame type for the frame, to identify a target queue in dependence upon the frame type, the target queue comprising a series of data areas in memory reserved for storing frames of the frame type, to obtain a current descriptor address of a current descriptor for the target queue, the current descriptor comprising a descriptor type field, a descriptor pointer field and a descriptor data size field, and to obtain an address in the series of data areas, to store a part of the frame data at the data area address.

Abstract: Methods for video display using a computing system. The computing system includes a main computing module and an ancillary computing module. The main computing module may transmit a synchronization control information block to the ancillary computing module. The synchronization control information block includes a frame number of a current frame and the reference time associated with the main computing module. The ancillary computing module receives the synchronization control information block and selects a frame pack having the same frame number contained in the synchronization control information block as the current frame. The ancillary computing module may obtain the reference time of the current frame based on a local time of the ancillary computing module. The main computing module and the ancillary computing module may decode one or more parts of the frame, respectively. Further, the decoded parts of the frame may be combined and displayed.

Abstract: There is provided a video processing apparatus that includes a network interface, first and second video buffering sections, a video supply section, a video control section, and a command issue section. The two video buffering sections are configured to receive and store video data coming in packets over a network via the network interface. The video supply section is configured to supply a video signal to a video signal line, the video signal being a selected output from one of the first and second video buffering sections. The video control section is configured to execute control over the other components. The command issue section is configured to send a bus input change command to the video control section as an instruction for video data selection for supply to the video signal line, the bus input change command including information about identifying a video data supply source connected over the network.

Abstract: A prediction means for predicting a maximum delayed change time, which is the longest in a change time which allows a next program to be displayed, if a channel is selected to change the current program to the next program; and a display control means, by which, from a reception completion time when the reception of the current program has been completed, a relevant program is displayed on the basis of original program data remaining in a buffer at the relevant reception completion time, and at the same time, the reproduction speed of the display is based on a speed at which the current program is displayed during the period between the reception completion time and a maximum delayed change time.

Abstract: A video input section acquires a video signal formed of a plurality of frames. A frame separator separates the video signal acquired by the video input section on a frame basis and distributes the separated video signals. A plurality of parallel processors perform video processing in parallel on the separated video signals corresponding to the frames separated and distributed by the frame separator. A frame combiner combines the separated video signals on which the plurality of parallel processors have performed the video processing.

Abstract: A TV control device, for an external TV device includes a storage unit storing a user identification code and user setting data corresponding to the user identification code, and a wireless communication unit transmitting a control signal to the external TV device according to the user identification code and the user setting data, wherein the external TV device determines a TV setting of the external TV device according to the user identification code and the user setting data when the external TV device receives the control signal.

Abstract: According to one embodiment, an information processing apparatus includes a first receiver, a screen transmitter, a second receiver and a controller. The first receiver receives first information associated with a display function of an external device. The screen transmitter generates an operation screen for operating the apparatus based on the first information, and transmits a video signal of the generated operation screen to the external device. The second receiver receives second information associated with content of an operation on the operation screen from the external device. The controller controls operation of the apparatus based on the second information.

Abstract: Provided is a video processing device capable of displaying an easily viewable video utilizing a broader area in a display. A video processing unit that is included in the video processing device and processes an input video includes a first memory that stores the input video, a second memory that stores the input video, a compression/expansion control unit that compresses and/or expands a first area of the input video stored in the first memory and compresses and/or expands a second area of the input video stored in the second memory, and an image composing unit that generates an output video in which a video of the first area compressed and/or expanded by the compression/expansion control unit and a video of the second area compressed and/or expanded by the compression/expansion control unit are horizontally aligned.

Abstract: Systems and methods for calibrating a 360 degree camera system include imaging reference strips, analyzing the imaged data to correct for pitch, roll, and yaw of cameras of the 360 degree camera system, and analyzing the image data to correct for zoom and shifting of the cameras. Each of the reference strips may include a bullseye component and a dots component to aid in the analyzing and correcting.

Abstract: A system is disclosed for controlling operation of an electronic device, such as a TV. The system includes a first sensor located at or near the electronic device and a second sensor spaced apart from the first sensor, wherein the first and second sensors are configured to detect motion of a user within an operating zone associated with the electronic device. A processor is coupled to the electronic device and the first and second sensors, the processor being configured to input a signal from the first and second sensors. Memory is coupled to the processor, the memory comprising a sensing algorithm configured to process the input signal from the first and second sensors and determine the location of the user with respect to the operating zone. The processor is configured to send a control command to the electronic device based on an output of the sensing algorithm.

Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.

Abstract: A screen time control device includes a source interface for receiving a video signal, a processor connected to the video source interface for overlaying the video signal with a translucent signal to produce an overlaid video signal, and a device interface connected to the processor for receiving the overlaid video signal and providing the overlaid video signal to the display device. The processor substitutes the translucent signal in the overlaid video signal with a parental signal, where the parental signal can be a substantially opaque overlay signal that masks an image on the screen of the display device to prohibit viewing of the screen, a textual message, or a combination of both.

Abstract: A method for assisting users with channel entry utilizes channel tuning history to simplify the channel entry process. According to an exemplary embodiment, the method includes steps of storing a list of channel numbers previously tuned by the apparatus; receiving a first input selecting a most significant digit of a channel number; and enabling a display of channel numbers in response to the first input, wherein the displayed channel numbers comprise at least one channel number included in the stored list and having the most significant digit and at least one other channel number not included in the stored list and having the most significant digit.

Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.

Abstract: A method for converting a sink device and an apparatus for providing a content using the same are provided. The method for converting the sink device includes receiving a sink device conversion command from a first sink device, transmitting the content to a second sink device if a conversion approval of the sink device is received from the second sink device, and transmitting a control authority related to a content provision from the first sink device to the second sink device.

Abstract: A system for monitoring a sporting event includes devices for monitoring characteristics of the event and collecting monitored data. Devices address different aspects of the event and monitor and collect real-time data. The devices process the data into digitized frames, and a digital storage device receives and stores the frames in a random access storage buffer as time-stamped digitized data frames with unique addresses. The storage device is capable of both time-shifting and relational association. The system includes a controller and devices for monitoring and extracting a digitized data frame according to a predetermined criterion. A viewer communicates with the storage device and controller and selects, manipulates, and extracts the digitized data frame. The system records and plays back the monitored data using a circular storage buffer with a memory mapped file and allows playback of stored data without interrupting simultaneous recording of new input data.

Abstract: A video signal processing device, which includes: a plurality of imaging devices outputting mutually asynchronous interlace video signals; input buffers temporarily storing field by field the video signals outputted from the respective imaging devices; and an output image generating device generating field by field video signals of output target images from the video signals stored in the input buffers, wherein each of the video signals of the output target images is generated when all of the latest video signals to be components thereof are stored in the input buffers.

Abstract: A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.

Abstract: A video encoder includes a frame synchronizer to temporarily store video data supplied from an exterior in a plurality of memory banks repeatedly selected in a predetermined sequence and to read the video data successively from the plurality of memory banks repeatedly selected in said predetermined sequence, an encode unit to encode the video data read by the frame synchronizer, and a control unit to perform a bank switch process that swaps one memory bank among the plurality of memory banks for another memory bank separate from the plurality of memory banks.

Abstract: After an image compressed by a compressing portion is stored in a page memory, it is decoded by a decoding portion. A sub-scanning enlargement portion carries out sub-scanning direction enlargement processing upon the image decoded by the decoding portion and a printer prints out the enlarged image. At this time, the printer generates a printer synchronous signal each time when it scans an image formation object surface. A control portion provides the page memory, the decoding portion and the magnification changing portion with control signals so as to synchronize reading out of the image from the page memory, the decoding of the decoding portion and enlargement processing of the sub-scanning enlargement portion.

Abstract: An audio/video system (100) is capable of introducing variable amounts of delay into a signal path so as to properly synchronize two signals, such a video signal and a corresponding audio signal. According to an exemplary embodiment, the audio/video system (100) includes first circuitry (50) for applying a first delay to a first digital signal. Second circuitry (80) applies a variable second delay to a second digital signal to time align the second digital signal relative to the first digital signal. The second circuitry (80) includes an addressable memory (84) for selectively storing the second digital signal and for outputting the second digital signal on a first-in, first-out basis to apply the variable second delay to the second digital signal.

Abstract: An apparatus and a method of controlling image display in an image display apparatus having a panel and wherein an image output is synchronized to a frame synchronization signal of an input signal. The method includes determining whether or not an input synchronization signal is an abnormal synchronization signal, processing the abnormal synchronization signal if the input synchronization is the abnormal synchronization signal, and removing damaged frame data if the abnormal synchronization signal is processed.

Abstract: A method and circuit for generating a train of synthesized sync pulses in accordance with the Bresenham algorithm in response to an input clock having frequency Fi, such that the leading edges of the pulses occur at least nearly periodically, with time-averaged frequency at least nearly equal to (A/T)Fi, where A and T are integers, and such that the accumulated error, between the actual time interval between the first and last leading edges of Z consecutive ones of the pulses and the time ZT/(AFi), never exceeds 1/Fi. When Fi is equal to (T/A)Fo, where Fo is a predetermined output line frequency, an embodiment of the sync pulse generator includes an accumulator which stores a Count value, a comparator, and logic circuitry for generating the sync pulse train in response to a binary signal asserted by the comparator (and typically also control data that determines a configuration of the logic circuitry).

Abstract: A time sequentially scanned display comprises a matrix 20 of picture elements 21. Each of the picture elements comprises a display element 9, for instance of liquid crystal type. An addressable latch 3 has a plurality of storage locations which may be selectively updated in response to an address supplied to an address input. A multiplexer 7 supplies image data from any one of the storage locations at a time to the display element 9. The multiplexer has an address input for selecting which of the storage locations of the latch 3 supplies image data to the display element 9. In some of the embodiments, the address inputs are connected together and addressed by the outputs of a single counter 11 whereas, in other embodiments, the address inputs of the latch 3 and the multiplexer 7 are addressed independently, for instance by two counters 11a and 11b. Such an arrangement permits various types of asynchronous operation between addressing and displaying data.

Abstract: An image processing system for use in semiconductor wafer inspection comprises a multiplicity of self-contained image processors for independently performing image cross-correlation and defect detection. The system may also comprise an image normalization engine for performing image brightness and contrast normalization. The self-contained image processors and image normalization engine access image data from a memory array; the array is fed data from a multiplicity of imaging modules operating in parallel. The memory array is configured to allow simultaneous access for data input, normalization, and cross-correlation and defect detection. Multiple image processing systems can be configured in parallel as a single image processing computer, all sending defect data to a common display module.

Abstract: An information processing apparatus includes an address generation circuit for generating an address signal. A memory operates for storing an information signal containing a video signal in response to the address signal. The address signal is periodically updated. A compression processing circuit operates for reading out the information signal from the memory, and subjecting the readout information signal to a compressively encoding process. A head of every frame represented by the information signal is detected. A state of the address signal is stored which corresponds to the detected frame head. Detection is made as to whether or not the information signal becomes discontinuous. The updating of the address signal and also the operation of the compression processing circuit are suspended when it is detected that the information signal becomes discontinuous. Detection is made as to whether or not the information signal returns to a normally continuous state after the information signal becomes discontinuous.

Abstract: During decoding and processing of program clock reference (PCR) values in MPEG-2 transport streams, a first initial difference value is obtained by calculating a difference between a first detected PCR value and a system time clock (STC) value generated when the first PCR value is detected. Depending on the update status of the PCR values, a second initial difference value is obtained by calculating a difference between a second detected PCR value and a STC value generated when the second PCR value is detected. Thereafter, a composite difference value is obtained by further calculating a difference between the first initial difference value and the second initial difference value. Subsequently, the first and second initial difference values, and the composite difference values are calculated for a predetermined number of detected PCR values so that the decoder clock signal is generated and maintained at approximately the same frequency as an encoder clock signal.

Abstract: A video signal capturing apparatus has a converter unit that converts an input video signal into digital video data and a digital video data writing control unit that controls writing of the digital video data converted by the converter unit in a memory. Thereby, digital video data for an external processing apparatus that uses the digital video data stored in the memory is captured. A separator unit separates a horizontal synchronizing signal from the input video signal. Based on the horizontal synchronizing signal thereby separated, a writing instructing unit instructs that the portion of the digital video data corresponding to an image information transmission be written in the memory. Thereby storage of unnecessary data is avoided in contrast with an apparatus that captures all the data including synchronizing signals.

Abstract: The invention features the generation of timing signals for use in the generation of a video signal. Vertical timing codes and horizontal timing codes are stored in a memory. The horizontal timing codes define regions of at least two types of horizontal timing signals of the video signal, and the vertical timing codes define the timing of the horizontal timing signals. The vertical and horizontal timing codes are stepped through to generate at least one signal indicative of the timing of the horizontal timing signals.

Abstract: The present invention provides a method and apparatus for providing program clock reference (PCR) data to various devices in a digital transmission system in a robust manner. According to the present invention, PCR data representative of a snapshot of the system clock is encoded only an existing frequency reference signal. The frequency reference signal is a signal to which all clock dependent components lock to ensure that the proper frequency lock is used. By encoding the frequency reference with PCR data, effectively using the frequency reference as a PCR carrier wave, the PCR is efficiently and robustly delivered to the various devices requiring this PCR data.

Abstract: A digital sine wave signal is read form a memory storage of a phase synchronizing apparatus and is converted into an analog signal through a digital to analog converter. This converted analog sine wave is phase compared to an input analog sine wave supplied to an input terminal of the synchronization apparatus. The phase of the digital sine wave is synchronized with that of the input analog sine wave by controlling a read address signal of the memory storage based upon a detected phase error signal between the input analog sine wave and the converted analog sine wave. Thus, a desired digital signal synchronized with the phase of an input signal can be generated by a simple arrangement by digital processing.

Abstract: A monolithically integratable display apparatus for receiving a picture signal having frames of video information and horizontal and vertical synchronizing components includes a matrix of display cells arranged in an array of M rows by N columns. Display cells in the matrix are individually addressable by row and column signals so as to receive the video information in the picture signal in response thereto. A first shift circuit coupled to the matrix provides the row signals in response to a first clocking signal and a data signal. A second shift circuit coupled to the matrix provides the column signals in response to a second clocking signal. A first clock circuit, such as a phase locked loop, receives the horizontal synchronizing component of the picture signal and produces the second clocking signal in response thereto. A synchronizing detector circuit receives the vertical synchronizing component of the picture signal and produces the data signal in response thereto.

Abstract: A multiplex frame format for transmitting digital data in a data transmission system comprises a PACKETS portion comprising a highly error-protected region and a region having only Reed Solomon encoding as an error protection measure, the PACKETS portion including low speed data. The frame format also comprises portions for transmitting medium (AUDIO) and high speed (VIDEO) data streams following the PACKETS portion. Prior to transmission, the composed frame comprising the PACKETS, AUDIO and VIDEO portions is interleaved and the BLOCK SYNC and FRAME SYNC are added. A multiplex structure control packet word of the PACKETS portion immediately follows FRAME SYNC. Thus, the FRAME SYNC word defines where interleaving begins. A demultiplexer in concert with a microcontroller of a decoder decodes the multiplex structure control word and related PACKETS and outputs digital data streams to related output peripheral processors.

Abstract: When processing a digital video signal, the problem often arises of converting the signal from a first sampling raster which is asynchronous with respect to the line interval to a second sampling raster which synchronous with the line interval. Interpolation filters are used for this purpose. The present invention provide a simple method for the conversion which does not require intermediate D/A or A/D conversion. For each line of the input signal, the phase of samples of the first sampling raster relative to the line synchronization pulse and the total number of the samples for this line are determined and are used to control of the interpolation filter.