Abstract: A touch-screen input/output device including a touch sensor, a display, a display control module, a touch sensor control module and a synchronizer module. The touch sensor is overlaid on a display. The display control module is communicatively coupled to the display and converts video data into a serial bit stream video display signal including one or more blanking intervals. The touch sensor control module is communicatively coupled to the touch sensor and determines touch events and location of the touch event on the touch sensor during one or more touch sensor scan cycles. The synchronizer module is communicatively coupled between the display control module and the touch sensor control module, and interleaves the one or more touch sensor scan cycles with the one or more blanking intervals of the video display signal.

Abstract: A method and apparatus for measuring the quality of a video is provided. The method comprises: generating a frame loss pattern of the video by indicating whether each frame in the video is lost or successfully transmitted; and evaluating the quality of the video as a function of the generated t came loss pattern.

Abstract: A video input section acquires a video signal formed of a plurality of frames. A frame separator separates the video signal acquired by the video input section on a frame basis and distributes the separated video signals. A plurality of parallel processors perform video processing in parallel on the separated video signals corresponding to the frames separated and distributed by the frame separator. A frame combiner combines the separated video signals on which the plurality of parallel processors have performed the video processing.

Abstract: A system, method, and computer program product are provided for enhancing a viewing experience when display content is viewed utilizing stereo glasses. In use, display content is received for being outputted utilizing a display. Further, a duration of a vertical blanking interval associated with the display content is increased for enhancing a viewing experience when the display content is viewed utilizing the stereo glasses.

Abstract: It is determined whether or not an input image is an image converted from an image with a relatively low resolution based on one frame of an image. A resolution determination device includes: an edge strength calculator configured to obtain an edge strength of a pixel included in an input image based on luminance of the pixel and luminance of a pixel adjacent to the pixel, for each of a plurality of pixels included in the input image; and a resolution determiner configured to determine whether or not the input image is an image upconverted from an image with a predetermined resolution or less, based on distribution of the edge strengths.

Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.

Abstract: Stereographic glasses includes reception-stop timing control means that is so arranged as to: (i) cause a wireless-signal receiving section to stop receiving signals, after a cycle detection section detects a cycle of synchronous signals and a liquid crystal shutter control data memory section stores liquid crystal shutter control data therein signals; (ii) cause a liquid crystal shutter control signal timing generation section to generate timings for controlling opening and closing of liquid crystal shutters, based on cycle signals generated by a cycle signal generation section and the liquid crystal shutter control data stored in the liquid crystal shutter control data memory section; and (iii) cause a liquid crystal shutter control section to open and close the liquid crystal shutters, at the timings thus generated.

Abstract: A method for converting a sink device and an apparatus for providing a content using the same are provided. The method for converting the sink device includes receiving a sink device conversion command from a first sink device, transmitting the content to a second sink device if a conversion approval of the sink device is received from the second sink device, and transmitting a control authority related to a content provision from the first sink device to the second sink device.

Abstract: A display device includes a display panel, a control circuit and a random number generating circuit. The random number generating circuit includes a plurality of shift registers, an output circuit, and registers which holds initial values. By providing a plurality of initial values, the randomness of random numbers can be enhanced. Further, the random numbers different from each other can be outputted from the plurality of shift registers and hence, it is possible to increase the frequency and to output the increased frequency by an output circuit. Further, by adding a noise control signal which suppresses the number of inversion of a digital signal, electromagnetic wave noises generated from a liquid crystal display device can be reduced. Further, by adopting an intermittent drive clock which intermittently repeats stopping thereof as a basic clock of the plurality of shift registers, electromagnetic wave noises generated from the display device can be reduced.

Abstract: According to embodiments, a synchronization signal generating device includes: a cycle measuring unit configured to measure the vertical synchronization interval of the input video signal; a phase difference detecting unit configured to detect a phase difference between an input vertical synchronization signal based on the input video signal and the display vertical synchronization signal; and a vertical cycle determining unit configured to determine a cycle of the display vertical synchronization signal based on a measurement result of the cycle measuring unit and a detection result of the phase difference detecting unit so that the phase difference is decreased within the range of the compensation interval, and to determine 1/n of the cycle of the display vertical synchronization signal as a cycle of an n-times speed vertical synchronization signal.

Abstract: To realize a random number generating circuit that is optimum for a liquid crystal display device that is used in a terminal device that includes a display/input component. A liquid crystal display device includes a liquid crystal display panel, a control circuit and a random number generating circuit, the random number generating circuit comprises plural shift registers, an output circuit and a register that stores an initial value, and the random number generating circuit is equipped with plural initial values, whereby the randomness of the random numbers is improved. Further, it becomes possible to increase and output frequencies by the output circuit because it is possible to output respectively different random numbers from the plural shift registers.

Abstract: A clock generation method and apparatus in a multimedia system includes generating a first intermediate clock with multiple phases by multiplying a frequency of an input clock by a predetermined factor using a phase-locked loop or a delay-locked loop, generating a transmission clock by dividing a frequency of the first intermediate clock by 5, and generating a pixel clock used in the multimedia system using a frequency of the transmission clock. When the first intermediate clock with the multiple phases is used to generate the pixel clock corresponding to a color depth, the number of phase-locked loops or delay-locked loops necessary for frequency multiplication can be reduced.

Abstract: A video signal synchronization signal generating apparatus for making a display reference synchronization signal Vb that serves as a reference of video display and has a first frequency and an input synchronization signal Vi that constitutes images and has a second frequency synchronized with each other, the apparatus including: a frequency ratio generating section configured to divide a frequency that is double the first frequency by the second frequency to calculate a frequency ratio n; a Vx generation comparator circuit section configured to generate coincidence signal Vx? having pulses that are inserted by equally dividing one period of the input synchronization signal Vi by the frequency ratio n; and a Vx generation circuit section configured to remove the alternate pulses of the coincidence signal Vx? to generate synchronization signal Vx of a same phase as the phase of the input synchronization signal Vi.

Abstract: A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.

Abstract: A system, method, and computer program product are provided for enhancing a viewing experience when display content is viewed utilizing stereo glasses. In use, display content is received for being outputted utilizing a display. Further, a duration of a vertical blanking interval associated with the display content is increased for enhancing a viewing experience when the display content is viewed utilizing the stereo glasses.

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: A signal generator for use in producing a video top-of-frame signal based upon an input video signal with an input video frame including one or more input video fields and having an input video frame rate for an output video signal with an output video frame having a plurality of output video frame lines, each with a plurality of output video pixels, and an output video frame rate.

Abstract: A horizontal synchronization generation circuit, which generates a horizontal synchronizing signal from a given reference clock, enables accurate reproduction of a preferable frame frequency with a simple configuration. A clock counter counts the reference clock. A comparator generates the horizontal synchronizing signal at a time when a count value output from the clock counter becomes equal to a synchronization counter value. A synchronization counter value output section generates the synchronization counter value by performing addition/subtraction in each of scanning lines based on a basic counter value.

Abstract: A synchronization detecting apparatus includes a counter, an error detector, and a line length generator. The counter counts to a predetermined counter value in response to a clock signal. The error detector generates an error, which is the difference between a current counter value received from the counter and a previous line length, in response to a synchronization flag signal. The line length generator generates a current line length based on a compensated error and the predetermined counter value. The synchronization flag signal has an active level at a transitioning edge of a synchronization pulse signal contained in an input signal.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method comprises: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: A display drive integrated circuit is for driving a display panel. The display drive integrated circuit includes a division rate output unit which outputs as a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number, and a system clock generating unit which generates a system clock signal by dividing the dot clock signal using the division rate.

Abstract: An image processing device includes a synchronizing signal separation section, a counting section, a synchronizing signal determination section, and a video format determination processing section. The synchronizing signal separation section separates a horizontal synchronizing signal from a received broadcasting signal. The counting section counts the pulse number of the separated horizontal synchronizing signal. The synchronizing signal determination section determines presence/absence of a synchronizing signal based on the counted value by the counting section. The video format determination processing section determines a video format of the received broadcasting signal based on the number of scan lines. The video format determination processing section determines the video format only when it is determined that there is a synchronizing signal by the synchronizing signal determination section.

Abstract: An image signal processing device, which uses a horizontal synchronizing signal detector to find a frequency (period) of an original horizontal synchronizing signal from an external input horizontal synchronizing signal and provide an internal reference horizontal synchronizing signal with the same frequency same as the original horizontal synchronizing signal to a horizontal synchronizing signal output controller for determining to output the external input horizontal synchronizing signal according to the frequency of the internal reference horizontal synchronizing signal and filtering out the original horizontal synchronizing signal.

Abstract: A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method includes: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference to generate a comparison result; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: A video synchronization signal generating circuit includes a sample and hold circuit, a voltage divider and an amplifier. The voltage divider produces an adaptive voltage level based at least in part on an output of the sample and hold circuit. The amplifier, which receives a video signal, is connectable by switches in different configurations. In a first configuration the amplifier acts as a comparator to compare the adaptive voltage level with the video signal. An output of the amplifier in the first configuration is an output of the video synchronization signal generating circuit. In a second configuration the amplifier forms part of the sample and hold circuit.

Abstract: A synchronization separation circuit extracts a synchronization timing signal from a video signal, and a burst gate pulse generator generates a timing pulse signal for gating a color burst signal period. In the color burst signal period restricted by the timing pulse signal, a first counter counts up cycles of a color burst signal at a first timing as a rising edge of the color burst signal and a second counter counts up cycles of the color burst signal at a second timing as a falling edge of the color burst signal. A color burst determination circuit receives count values to determine presence/absence of a color burst signal superimposed on the video signal.

Abstract: A circuit for generating a timing signal, the circuit having a memory and a pulse generator, the timing signal consisting of a number of pulses. The memory stores pulse count data, including an indication of the number of pulses in the timing signal, and rising edge and falling edge position data of the timing signal. The pulse generator produces the timing signal in accordance with the pulse count data and has a first circuit for generating rising edge signals, a second circuit for generating falling edge signals, an active control circuit for setting, in correspondence only with the pulse count data, corresponding rising edge signals as active state rising edge signals, and corresponding falling edge signals as active state falling edge signals, and a third circuit for generating said timing signal corresponding to the active state rising edge signals and the active state falling edge signals.

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: A method and apparatus for a digital video display. A digital display device receives an analog signal representing an image formed of pixels in video lines and a signal containing a synchronization waveform for the image. An analog-to-digital converter (ADC) receives the analog signal and converts it to a sampled digital waveform. A phase-locked loop including a programmable frequency divider controls the sampling time for the ADC. The programmable frequency divider is controlled by a dividing-ratio algorithm that selects a dividing ratio, measures the number of pixels in a video line using the dividing ratio, and recomputes the dividing ratio by multiplying the selected dividing ratio by the expected number of pixels in a video line and dividing by the measured number of pixels. The sampling phase for the ADC is selected by a sampling-phase control algorithm that minimizes a function representative of the flatness of the sampled digital waveform.

Abstract: In order to reduce the circuit scale and the manufacturing cost by decreasing the amount of data to be stored, a synchronizing signal data generating circuit outputs, at each timing, relative synchronizing signal data showing the ratio of a synchronizing signal level to an amplitude level of the synchronizing signal, a multiplier multiplies synchronizing signal amplitude level data, a divider divides by the maximum value N of image signal data which can be outputted from the synchronizing signal data generating circuit, thereby the synchronizing signal data showing actual synchronizing signal level is provided, and an adder adds input image signal data thereto, whereby output image signal data, in which the synchronizing signal data is superposed on the input image signal data, is generated.

Abstract: An apparatus and method of extracting a sync signal from an analog composite video signal includes a controller to decide whether a horizontal sync signal in the analog composite video signal is a distorted abnormal signal, and extracts the horizontal sync signal from the composite video signal using a separate counter if the analog composite video signal is the distorted abnormal signal A sync signal can be precisely extracted from the distorted abnormal signal. Therefore, an overall system synchronization of the apparatus can be stable, and distortions in output images can be prevented.

Abstract: A circuit for generating video synchronization timing signals includes a negative peak detector (FIG. 5) for following variations of a composite video signal (FIG. 1), rather than clamping the most negative voltage of the composite video signal. The negative peak detector provides a voltage level VTIP representative of the voltage at the synchronization tip of the composite video signal. A sample and hold circuit (700,702,704) is used to add an offset VSLICE to VTIP, VSLICE being a voltage level of the breezeway, color burst, or back porch segments of the composite video signal, or a combination of these segments.

Abstract: Disclosed is a video signal processing apparatus comprising a plurality of line memories to which in sequence input video signal data is written on a line-by-line basis; a timing controller for controlling a timing to write video signal data to the plurality of line memories and a timing to read video signal data from the plurality of line memories; a computation output portion for computing video signal data read from the plurality of line memories and outputting video signal data differing in resolution which is determined by a pixel count in the horizontal direction and a line count in the vertical direction; and a line controller which vary the pixel count in specified lines of video signal data obtained from the computation output portion, depending on a conversion rate of the video signal data resolution.

Abstract: A system and method for correcting non-periodic event time of arrival data in a control system. The system and methods are particularly applicable to the speed and phase control of a color wheel used with spatial light modulators. The circuitry automatically and accurately compensates for non-periodic index signals occurring when one or more index marks on the color wheel are misplaced. The system adds to or subtracts clock pulses from the actual time of arrival of a specific index mark until the corrected value equals the desired or nominal value. The system then generates a PWM signal for controlling the speed and phase of the color wheel.

Abstract: A clock generating apparatus is provided for producing an output clock signal responsive to a source clock signal with a source frequency and a reference clock signal with a reference frequency. The clock generating apparatus includes a counting sequence generator, a measuring value generator and a ratio counter. The counting sequence generator is used for outputting a series of counting values in response to a triggering signal with a specified period determined by the source frequency of the source clock signal and a predetermined counting value. The measuring value generator generates a measuring value by operating the series of counting values according to a predetermined formula. The ratio counter produces the output clock signal with a frequency determined by the source frequency of the source clock signal and the measuring value.

Abstract: A method and circuit for generating a train of synthesized sync pulses in accordance with the Bresenham algorithm in response to an input clock having frequency Fi, such that the leading edges of the pulses occur at least nearly periodically, with time-averaged frequency at least nearly equal to (A/T)Fi, where A and T are integers, and such that the accumulated error, between the actual time interval between the first and last leading edges of Z consecutive ones of the pulses and the time ZT/(AFi), never exceeds 1/Fi. When Fi is equal to (T/A)Fo, where Fo is a predetermined output line frequency, an embodiment of the sync pulse generator includes an accumulator which stores a Count value, a comparator, and logic circuitry for generating the sync pulse train in response to a binary signal asserted by the comparator (and typically also control data that determines a configuration of the logic circuitry).

Abstract: A signal processing apparatus and method for up or down conversion of an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.

Abstract: To reduce the amount of data that should be stored on a memory-built-in timing generator for generating timing pulses for use to drive a solid-state imaging device, V- and H-counters, three ROMs, V- and H-comparators and combinatorial logic circuit are provided. The V- and H-counters perform a count operation responsive to vertical and horizontal sync signal pulses as respective triggers. One of the ROMs stores time-series data representing a logical level repetitive pattern of an output pulse train. The other two ROMs store edge data representing at what counts of the V- and H-counters control pulses should change their logical levels. The V- and H-comparators and the combinatorial logic circuit change the logical levels of the control pulses when the counts of the V- and H-counters match the edge data. The comparators and logic circuit also output, as the timing pulses, results of logical operations performed on the output pulse train, represented by the time-series data, and the control pulses.

Abstract: A method to generate an optimum phase shifted sampling clock for sampling a synchronized video signal A(t) having a synchronization signal SYNC pulse is achieved. The method comprises, first, generating a sampling clock having a first edge aligned with a trailing edge of the SYNC pulse. The sampling clock period comprises the SYNC pulse period divided by M. Second, the number of sampling clock cycles N is counted from the trailing edge of the SYNC pulse until the A(t) value at the first edge of the sampling clock exceeds a minimum value. Third, the sampling clock and the SYNC pulse are phase shifted forward until the A(t) value at the first edge of the sampling clock first exceeds a minimum value on clock cycle N?1 to thereby establish a worst case phase shift of the sampling clock. Finally, A(t) is sampled at an offset from the worst case phase shift to thereby generate an optimum phase shifted sampling clock.

Abstract: A time sequentially scanned display comprises a matrix 20 of picture elements 21. Each of the picture elements comprises a display element 9, for instance of liquid crystal type. An addressable latch 3 has a plurality of storage locations which may be selectively updated in response to an address supplied to an address input. A multiplexer 7 supplies image data from any one of the storage locations at a time to the display element 9. The multiplexer has an address input for selecting which of the storage locations of the latch 3 supplies image data to the display element 9. In some of the embodiments, the address inputs are connected together and addressed by the outputs of a single counter 11 whereas, in other embodiments, the address inputs of the latch 3 and the multiplexer 7 are addressed independently, for instance by two counters 11a and 11b. Such an arrangement permits various types of asynchronous operation between addressing and displaying data.

Abstract: A method for clock recovery comprises a series of steps to be performed in a decoder to adaptively estimate the ratio P/S of the frequency of an encoder system time clock and the frequency of a decoder. The steps include performing a series of overlapping trials N which calculate time differentials dP(n), dS(n), respectively) between selected pairs of temporally separated clock references CRs and arrival times STCs. Each trial concludes by calculating an estimated ratio X according to the formula: X(N)=(&Sgr;dP(n))/(&Sgr;dS(n)) A preferred embodiment of the present invention also includes the step of adjusting the decoder clock in accordance with a damped version of the estimate, thereby “recovering” the encoder STC in the decoder.

Abstract: A simulated burst gate signal and a video synchronization key are generated. A video decoder generates a horizontal sync pulse which is programmed to envelop a color burst, thereby simulating a burst gate signal. The offset to the horizontal sync pulse due to simulating a burst gate signal may be compensated at a video memory subsystem receiving the horizontal sync signal, in order to determine when active pixels are provided by the video decoder. Alternatively, counter circuitry external to the video decoder may be used to generate a simulated burst gate signal by counting the number of pixel clock cycles between the horizontal sync pulse and the color burst. Unlike a burst gate signal generated within a video decoder for use with color separation circuitry in the video decoder, a simulated burst gate signal allows for use of color separation circuitry external to the video decoder. Detecting a color burst using external color separation circuitry is thus also disclosed.

Abstract: A first counter counts a first clock signal repeatedly in accordance with an external synchronous signal. A second counter counts a second clock signal repeatedly in every predetermined cycle, and generates an internal synchronous signal having the predetermined cycle. A controller adjusts the cycle of counting performed by the second counter by controlling the second counter. By doing so, the controller controls the internal synchronous signal to synchronize with the external synchronous signal in each horizontal period.

Abstract: A sync signal generator circuit including a first counter which is reset each time it detects a reference edge of the input sync signal, a first register for holding a first value immediately before the first counter is reset, a reset signal generator for generating reset pulses, a second counter which is reset each time it receives a reset pulse, a second register for holding a second value immediately before the second counter is reset, and a sync pulse generator for generating an output sync signal on the basis of the reset pulses. The reset pulse is generated each time the counted value of the second counter matches a predetermined value or each time the first counter detects the reference edge while an absolute value of a difference between the counted value of the second counter and the second value held in the second register is not greater than a permissible value of period fluctuations.

Abstract: An apparatus and method for detecting a synchronizing signal in a digital TV receiver which adopts a VSB mode is disclosed. The apparatus includes a correlation unit for obtaining a correlation value between a received signal for each unit of symbols and a preset reference field synchronizing signal, a maximum value detector for detecting a location of the symbol having a maximum correlation value while performing counting operation for a unit of a variable constant added to the number of symbols corresponding to one field, a synchronizing lock signal generator for generating a synchronizing lock signal by testing reliability of the symbol location detected by the maximum value detector, and a synchronizing location controller for calculating a relative location of the symbol location having a maximum value to generate a corresponding synchronizing signal if the synchronizing lock signal is generated by the synchronizing lock signal generator.

Abstract: There can be solved a problem in which a lock range is narrowed by using an oscillator such as a ceramic having a high Q and a horizontal deflection frequency generating system compatible with all horizontal deflection frequencies of a variety of television systems cannot be formed without difficulty. This system includes a frequency-fixed oscillator oscillating at a frequency f0 sufficiently higher than a deflection frequency fh in a multi-scan display, a first counter for counting a clock outputted from said oscillator in a descending order, a duration in which an integer n which results from rounding a decimal point of a value obtained by a division of f0 fh is divided by an integer m smaller than n and said first counter counts a value k thus obtained k times is set to one cycle and a duration in which a second counter for counting a value m times repeats the counting m cycles is set to one period and thereby generating a deflection frequency fh.

Abstract: An ITU-R BT.656 (or similar) digital video signal is converted to analog at which point a simple 7-state state machine in combination with a 6 bit binary counter generates tri-level synchronized video. The state machine receives vertical and horizontal synchronization signals as well as End-Active-Video and Start-Active-Video signals from the ITU-R BT.656 video. A pixel clock clocks the 6 bit binary counter. Active video is passed directly to the output. Horizontal and vertical sync signals are mirrored at the output with the state machine generating a positive tri-level signal immediately following the horizontal synchronization signal. The high level signal is generated for a period of 44 pixel counts as counted by the 6 bit counter.

Abstract: A clock generating device for use in a digital video apparatus generates display clock matching an input video format. The clock generating device generates a clock of a frequency which is a predetermined number of times greater than the clock necessary for displaying video signals having a respectively different format, frequency-divides the generated clock, phase-locks the obtained stable frequency and supplies corresponding display clock. Video signals of a respectively different format can be displayed into a single display format, to thereby provide an effect of displaying a video signal without degeneration of a picture quality.

Abstract: This invention is a method and apparatus for identifying and separating the synchronizing signal component of video like signals by identifying or detecting the arrangement or sequence of the known occurances of events or patterns of the sync. The invention also provides for establishing data slicing references in response to the levels of known portions of the sync component.