Abstract: A sync separation circuit separates a synchronizing signal from a video signal containing the synchronizing signal. A minimum level detecting section detects a minimum level of a video signal. A sync tip level detecting section detects a sync tip level in the video signal. A pedestal level detecting section detects a pedestal level in the video signal. Based on both the sync tip level detected by the sync tip level detecting section and the pedestal level control by the pedestal level detecting section, a slice level setting section sets a slice level corresponding to an intermediate value between the sync tip level and the pedestal level. The slice level control section sets the slice level based on the minimum level detected by the minimum level detecting section if the slice level set based on the sync tip level and the pedestal level is inappropriate.

Abstract: In one aspect a transmission system with a transmitter which can be connected to a video source and a receiver linked to the transmitter via at least four circuit pairs, to which receiver a playback device can be connected is provided. Data is usually exchanged digitally between a graphics card in a personal computer and an LCD display module. The personal computer transmits a digital R, G, B video signal to the LCD display module via a special, so-called DVI (Digital Video Interface) cable. This DVI cable is also provided to transmit so-called DDC (Display Data Channel) data, which particularly comprises specification information of the LCD display module. A transmission system is proposed, which simplifies a connection of an LCD display module to a personal computer and with which the DVI cable can be dispensed with.

Abstract: A device for detecting synchronization pulses in a video signal is disclosed. The device includes a transistor. The base-emitter voltage of the transistor is maintained below a threshold level in response to receiving active video information. The base-emitter voltage is increased above the threshold level in response to receiving synchronization information, whereby the transistor is turned on to generate an asserted synchronization signal. Accordingly, in response to active video information being received and the transistor being off, the magnitude of the synchronization signal is set to a first level and in response to synchronization information being received, and the transistor being on, the magnitude is set to a second level. The synchronization signal generated by the transistor is processed to provide both horizontal and vertical synchronization signals.

Abstract: A synchronization pulse representing a symbol boundary in a signal such as an OFDM signal is obtained by deriving a first signal representing the difference between the amplitudes of samples separated by the useful part of an OFDM symbol, a second signal representing the phase difference between the samples, and combining the first and second signals to derive a resultant signal. The resultant signal is examined and the synchronization pulse generated in response to the signal changing in a predetermined manner.

Abstract: In order to reduce the circuit scale and the manufacturing cost by decreasing the amount of data to be stored, a synchronizing signal data generating circuit outputs, at each timing, relative synchronizing signal data showing the ratio of a synchronizing signal level to an amplitude level of the synchronizing signal, a multiplier multiplies synchronizing signal amplitude level data, a divider divides by the maximum value N of image signal data which can be outputted from the synchronizing signal data generating circuit, thereby the synchronizing signal data showing actual synchronizing signal level is provided, and an adder adds input image signal data thereto, whereby output image signal data, in which the synchronizing signal data is superposed on the input image signal data, is generated.

Abstract: Provided are an automatic signal gain control method and apparatus that adaptively controls signal gain according to sync tip depths in a video receiving system. The method includes: detecting a sync signal from a video signal; detecting a blank level and a sync tip level from a sync section of the sync signal; extracting a difference between the blank level and the sync tip level, as a sync tip depth; and controlling the gain of the video signal differently according to a variation of the sync tip depth.

Abstract: A television monitor display with video signal processing comprises a source (SM) of a video display signal (Y) including a sync component (S). A video processor (U1) is coupled to process the video display signal (Y). A sync separator (SS) is coupled to generate separated synchronizing signals (Sy) from the sync component (S) of the video display signal (Y). A video amplifier (100) is coupled to the sync separator (SS) and the video processor (U1) and generates an output video signal (Ys+) wherein a sync component (S+) of the output video signal is increased in amplitude in accordance with the separate synchronizing signals (Sy) coupled to the video amplifier (100).

Abstract: The invention relates to a synchronization signal decoder and associated method for improving digital image display. A composite video stream includes a distortion compliant signal and a synchronization signal. A level shift circuit is adapted to shift a voltage level of the composite video stream such that the distortion compliant signal is readily distinguishable from the synchronization signal. A level shift disable circuit is adapted to disable the level shift circuit responsive to the composite video stream.

Abstract: The depth of modulation and the absolute RF carrier level of an amplitude-modulated video signal are automatically adjusted. For adjustment of the depth of modulation, a sync tip of the video signal is sampled, corrected and normalized to a reference level, e.g., a 50% video level. A reference pulse is inserted into the video signal, e.g., in a sync pulse or in lines 22 and/or 23 of the vertical blanking interval. The reference pulse is sampled and compared to the normalized sync tip pulse to determine an error. The error is converted to an adjustment signal for a charge pump which increases or decreases the depth of modulation accordingly. For adjustment of the absolute carrier level, the insertion of a reference pulse is not required. Instead, a reference value is stored in a memory and retrieved for comparison with the corrected sync tip pulse. An error term is computed and converted to an adjustment signal for a charge pump which increases or decreases the absolute carrier level accordingly.

Abstract: The depth of modulation and the absolute RF carrier level of an amplitude-modulated video signal are automatically adjusted. For adjustment of the depth of modulation, a sync tip of the video signal is sampled, corrected and normalized to a reference level, e.g., a 50% video level. A reference pulse is inserted into the video signal, e.g., in a sync pulse or in lines 22 and/or 23 of the vertical blanking interval. The reference pulse is sampled and compared to the normalized sync tip pulse to determine an error. The error is converted to an adjustment signal for a charge pump which increases or decreases the depth of modulation accordingly. For adjustment of the absolute carrier level, the insertion of a reference pulse is not required. Instead, a reference value is stored in a memory and retrieved for comparison with the corrected sync tip pulse. An error term is computed and converted to an adjustment signal for a charge pump which increases or decreases the absolute carrier level accordingly.

Abstract: Sync separator and video detector circuits, including a sync tip clamp having symmetrical and non-symmetrical clamps. The symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output.

Abstract: A video sync slicing circuit is disclosed that employs an adjustable gain control (AGC) amplifier and circuitry that adjusts a gain of the AGC amplifier such that a blanking level of the video signal at an output of the AGC amplifier equals a blanking reference voltage. The slicing circuit includes a circuit that triggers a composite sync signal when a sync pulse of the video signal equals the fifty percent slicing level.

Abstract: A sync signal separating circuit of an image output apparatus includes an inversion amplifying section for providing a green video signal supplied from a video signal generator to be output as an output signal that is inverted and amplified, and a clipper receiving the output signal of the inversion amplifying section as an input signal to output a clipped output signal obtained by cutting over or below a prescribed amplitude. Here, the inversion amplifying section has an amplifying device, an input resistor and a feedback resistor, and the clipper has a diode having an anode connected to the output side of the inversion amplifying section and a load resistor having one side connected to a cathode of the diode and the other side grounded. Thus, the sync signal is accurately produced from the cathode of the diode without requiring a conventional horizontal sync signal detecting section.

Abstract: A circuit for removing every other equalizing pulse from a signal representing the sync pulses of a composite video signal, generates an output signal representative of every horizontal synchronization pulse and every other vertical synchronization pulse within the composite video signal. A sync separator circuit separates the synchronization pulses from the composite video signal. An output of the sync separator circuit includes all of the horizontal synchronization pulses and vertical synchronization pulses. The vertical synchronization pulses include equalizing pulses and serration pulses which have a frequency which is twice the frequency of the horizontal synchronization pulses. A capacitor is used to store charge. A current source charges the capacitor. A transistor controlled by the output signal provides a discharge path for the capacitor.

Abstract: An integrated active filter and sync separator circuit operates on precision internal reference sources to set the filter cut off frequency as a function of resistance of an external resistor. The active filter eliminates the source of sync tip crushing attributable to conventional clamping circuits associated with sync pulse detectors, and also provides sync pulses substantially devoid of time-variant jitter.

Abstract: A circuit that extracts the synchronization signal from a composite video signal. The circuit includes a stage for aligning the low level of the synchronization signal interval with a reference voltage; a stage for detecting the signal suppression level and a comparator for comparing the aligned video signal with a value intermediate between the low level of the synchronization interval and the signal suppression level. The detecting stage includes a second comparator charging or discharging a capacitor depending on the polarity of the voltage difference across its inputs. The ratio Ic/Id between the values of the charging and discharging currents is selected (approximately equal to 8 in one embodiment) to obtain the suitable value Vsup at the second input of the comparator.

Abstract: Reductions in size and cost for a sync chip clamping/sync separation circuit are envisaged by the use of the CMOS process. The final output amplification section of a differential amplifier circuit is implemented as a P channel FET, and the pull down current for the drain terminal of this P channel FET is set to a value which is smaller than the current which flows when this P channel FET is ON. A constant voltage is supplied by resistors to the non inverting input terminal (+) of the differential amplification circuit. Further, the inverting input terminal (-) of the differential amplification circuit and the output terminal thereof are connected, and also an input coupling capacitor is interposed between the inverting input terminal (-) thereof and an video signal input terminal. Further, a buffer is provided which takes out a sync signal from an input of the P channel FET.