Abstract: Electronic devices, storage medium containing instructions, and methods pertain to cancelling noise that results from application of clocks/clock drivers of a display. The electronic display may inject counter noise into the cathode. For example, the counter noise may be injected via a sensing layer, via unused clocks, and/or via a power rail of the display.

Abstract: A method for use in the manufacture of a filtration article includes providing a porous, fluoropolymer membrane, and applying a force to at least a portion of a first side surface of the membrane to modify the first side surface. The applied force may have a non-normal directional component relative to the first side surface. The surface modification may increase the density of the modified surface and/or reduce the porosity of the modified surface. Particle retention capabilities are thereby enhanced across the modified surface while maintaining permeability across the volume of the membrane.

Abstract: The display apparatus includes a video receiver which receives a video signal from an external source; a video processor which processes the video signal received in the video receiver to be displayable on a display unit; and a noise processor which determines frequency position information of an interference signal component from a frequency domain of sync sections extracted from the video signal with regard to the interference signal component mixed in a predetermined frequency band of the video signal and causing noise in a display image displayed on the display unit, and compensates the display image based on the determined frequency position information.

Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.

Abstract: In an image processing apparatus, information indicating a degree of correlation between a current frame and a previous frame is computed based on a pixel value in the current frame before being subjected to the recursive noise reduction and a pixel value in the previous frame after being subjected to the recursive noise reduction. Then, a recursive coefficient, which is a weight of the previous frame, is determined based on the degree of correlation and a frame rate of the moving image. The recursive noise reduction is applied to the current frame by combining the pixels in the previous frame and the current frame using the recursive coefficient. For the same degree of the correlation, the recursive coefficient is determined to be smaller as the frame rate is lower. Noise reduction in accordance with the image frame rate is achieved.

Abstract: There is disclosed a stream data reception/reproduction device capable of suppressing deterioration of quality of stream data reproduced even when the stream data is received via an IP network or the like in which the packet arrival timing and the order are not guaranteed. In this device, a reproduction speed control unit (107) sets various conditions in accordance with the value of the synchronization difference reported from a synchronization difference calculation unit (102). Only when the set conditions are satisfied, the speed of reproduction of a frame decompressed and inputted from a decoding unit (105) is adjusted. The reproduction speed control unit (107) interpolates a predetermined amount of sample data into the frame or decimates it from the frame when adjusting the reproduction speed.

Abstract: Techniques are disclosed relating to video signal-to-noise ratio (VSNR) measurement. In one embodiment, an analog television signal receiver includes a measurement circuit configured to measure noise in a video signal over one or more intervals that correspond to a horizontal control signal of the video signal and a control unit configured to determine a VSNR based on the measurement. In another embodiment, a first noise calculation circuit is configured to determine first noise information from a video signal and a second noise calculation circuit is configured to determine second noise information from a video signal in a manner different from the first noise calculation circuit. A control unit may be configured to generate a VSNR based on one or both of the first noise information and the second noise information.

Abstract: A video signal processing circuit includes: a composite sync signal generation circuit, generating a composite sync signal from a received composite video signal; a signal-noise-ratio calculation unit, generating a SNR of the composite video signal; a timing generation unit, generating a gated window based on the SNR; and a vertical sync signal separation unit, generating a vertical sync signal from the composite sync signal based on the SNR and the gated window, and dynamically adjusting a detection criterion on the vertical sync signal.

Abstract: Various embodiments of this disclosure may describe a two-stage ADC circuit, and a time-interleaved system based on the two-stage ADC circuit. The two-stage ADC circuit may include a SAR converter for the first stage and a charge based TDC for the second stage. The two-stage ADC circuit may be used in high performance serial I/O applications. Other embodiments may be disclosed and claimed.

Abstract: A method for performing de-noise processing includes: with regard to each direction of a plurality of directions, summing up absolute values of differences between a plurality of sets of first pixel values around a target pixel of an image to generate a first detection value, and with regard to each direction of at least a portion of the directions, selectively averaging at least one set of second pixel values around the target pixel to generate a second detection value; sorting a plurality of pixel values around the target pixel and generating a third detection value accordingly; and with regard to a specific direction of the directions, performing de-noise processing on the target pixel according to at least the former two of the first detection value, the third detection value, and the second detection value. An associated apparatus is also provided.

Abstract: A method for performing bad pixel compensation includes: with regard to each direction of a plurality of directions, summing up absolute values of differences between a plurality of sets of first pixel values around a target pixel of an image to generate a first detection value, and with regard to each direction of at least a portion of the directions, summing up absolute values of differences between a plurality of sets of second pixel values around the target pixel to generate a second detection value, where each set of the sets of first pixel values and the sets of second pixel values includes two pixel values corresponding to a difference; and with regard to a specific direction of the directions, selectively performing bad pixel compensation on the target pixel according to the first detection value and the second detection value. An associated apparatus is also provided.

Abstract: An imaging device of the present invention includes an image capturing unit, a noise obtaining unit, a fixed noise calculating unit, and a noise eliminating unit. The image capturing unit generates image data by photoelectrically converting, pixel by pixel, a subject image formed on an available pixel area of a light-receiving surface. The noise obtaining unit reads a noise output from a partial area of the available pixel area. The fixed noise calculating unit calculates an estimation of fixed pattern noise of the available pixel area based on the noise output read from the partial area. The noise eliminating unit subtracts the fixed pattern noise from the image data.

Abstract: An image processing apparatus includes a pixel difference calculator, a summing unit, a determining unit, and an output unit. The pixel difference calculator receives a present image having first pixels and a previous image having second pixels, calculates pixel differences between corresponding first and second pixels, and outputs positive and negative pixel difference values. The summing unit obtains a first output value by adding up those of the positive pixel difference values and a second output value by adding up those of the negative pixel difference values. The determining unit determines a noise level of the present image from the first and second output values, and outputs a blended value. The output unit adds together weights of pixels at the same positions of the present and previous images according to the blended value to generate an output image. An image processing method is also disclosed.

Abstract: A video signal processing circuit includes: a composite sync signal generation circuit, generating a composite sync signal from a received composite video signal; a signal-noise-ratio calculation unit, generating a SNR of the composite video signal; a timing generation unit, generating a gated window based on the SNR; and a vertical sync signal separation unit, generating a vertical sync signal from the composite sync signal based on the SNR and the gated window, and dynamically adjusting a detection criterion on the vertical sync signal.

Abstract: A number of invalid pixels at an outer peripheral part is reduced while suppressing an influence on an image quality such as discontinuity by pixel expansion, and suppressing increase in a number of processing pixels. When sequentially generating a plurality of reduced images having resolutions different from each other by sequentially performing a reduction process on an input image when realizing a noise reduction process using multiresolution transformation, the pixel expansion process of expanding the pixels at the outer peripheral part of the image of the reduced image is performed at least once before performing one of the reduction processes, and the reduced image after the pixel expansion process is further reduced to generate the plurality of reduced images.

Abstract: A visible mismatch in noise characteristics between a portion of a background scene inserted in composite image by a matte generated from a blue screen and a second portion of the same background inserted by a garbage matte is significantly reduced by adding extracted noise characteristics from the foreground image to the portion of the background scene inserted by the garbage matte. The selective addition of foreground noise characteristics to portions of the background scene significantly enhances the realistic look of a composite image.

Abstract: A microcontroller-based video AGC/sync regulator in which the parameters of various synchronizing signals of several different video formats are incorporated into a user program to generate signals to be processed by other sub circuits that correct and reinforce the AGC levels and sync signals of an incoming video signal is disclosed. The microcontroller-based video AGC/sync regulator is synchronized by the selection and isolation of a reference point of particular qualities that distinguishes itself from any other portion of the video signal. The reference points may be singular or plural in nature and are extracted from the video signal by means of a hybrid and specialized circuit or circuits, an auxiliary microcontroller and/or the system microcontroller. The microcontroller-based AGC/sync regulator is readily adapted for use as a decoder/encoder by altering the user program.

Abstract: In a method and circuit for recovering a sync signal from an input sync signal passing through a cable to a display device, an average value of the input sync signal is obtained during a predetermined time period so as to obtain a sync threshold, which is compared with the input sync signal. A sync signal is output when the input sync signal is greater than the sync threshold.

Abstract: In order to create a noise elimination device for the detection of the vertical sync pulse in video signals, which has a very fast locking behavior and in which additional components can be integrated easily, which components can measure fundamental parameters of the underlying composite video signal, it is proposed that the device comprises a vertical pulse detector (12), which detects successive vertical sync pulses in the composite video signal and a VPLL (vertical phase locked loop), which comprises at least a phase detector (18) that produces a phase error, at least a loop filter (20), at least an oscillator (16) on which the output signal of the vertical pulse detector is present as an input signal and which oscillator produces a clock signal phase-synchronized with the input signal, whereas the oscillator (16) is a counter which counts with an approximately constant clock frequency, while the length of an oscillation period of the oscillator (16) is determined by the change in its count due to a correc

Abstract: The present invention provides a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. The synchronizing signal detection circuit predicts detection positions of synchronizing pulses every synchronization cycle peculiar to an input video signal. The synchronizing signal detection circuit further supplies the input video signal to a plurality of unnecessary signal eliminating paths in common and extracts synchronizing signals of every path respectively from video signals of every path obtained by eliminating unnecessary signals according to the characteristics of the paths every path.

Abstract: A synchronization detector of a video signal processor includes a line buffer, a parameter extraction unit and synchronization detection unit. The line buffer sequentially stores a digital video signal corresponding to an input analog video signal, line by line of the input analog video signal. The parameter extraction unit continuously extracts horizontal synchronization parameters from the digital video signal stored line by line and continuously extracts vertical synchronization parameters from a portion of the digital video signal stored line by line. The synchronization detection unit generates horizontal and vertical synchronization signals of the input analog video signal using time information related to local minimum values of the horizontal synchronization parameters and time information related to local minimum values of the vertical synchronization parameters.

Abstract: In one aspect a transmission system with a transmitter which can be connected to a video source and a receiver linked to the transmitter via at least four circuit pairs, to which receiver a playback device can be connected is provided. Data is usually exchanged digitally between a graphics card in a personal computer and an LCD display module. The personal computer transmits a digital R, G, B video signal to the LCD display module via a special, so-called DVI (Digital Video Interface) cable. This DVI cable is also provided to transmit so-called DDC (Display Data Channel) data, which particularly comprises specification information of the LCD display module. A transmission system is proposed, which simplifies a connection of an LCD display module to a personal computer and with which the DVI cable can be dispensed with.

Abstract: A video noise reduction technique is presented. Generally, the technique involves first decomposing each frame of the video into low-pass and high-pass frequency components. Then, for each frame of the video after the first frame, an estimate of a noise variance in the high pass component is obtained. The noise in the high pass component of each pixel of each frame is reduced using the noise variance estimate obtained for the frame under consideration, whenever there has been no substantial motion exhibited by the pixel since the last previous frame. Evidence of motion is determined by analyzing the high and low pass components.

Abstract: A method and apparatus for rendering image data on a 3D display is disclosed. A first image signal is received and then at least one colour component of the first image signal is rendered in reduced spatial resolution to produce a second image signal. The second image signal is spatial filtered wherein spatial errors and view errors are balanced when reconstructing a full resolution signal for the display.

Abstract: An image processing apparatus of the present invention comprising (a) a first signal processing circuit for applying gamma correction to an n-bit (n: a natural number) digital signal inputted as a video signal and for converting the n-bit digital signal into an m-bit (m>n, m: a natural number) digital signal, and (b) a second signal processing circuit for adding a noise signal, which is used for pseudo contour reduction, into the m-bit digital signal from the first signal processing circuit and for outputting a Q-bit (Q: a natural number) digital signal, which is obtained from rounding off a less significant (m?Q) bit (Q?n) from the m-bit digital signal, to a display section.

Abstract: We describe and claim a system and method for horizontal and vertical sync detection and processing. A method comprises detecting synchronization information within a video signal, estimating stability of the video signal according to the detected synchronization information, and generating one or more synchronization signals according to the detected synchronization information and the estimated stability of the video signal.

Abstract: An apparatus, system, and method for determining an operational threshold level for distinguishing between video data and synchronization data in a video signal, are described herein.

Abstract: One embodiment of the present invention provides a system that removes noise from an image. During operation, the system first identifies blobs in the image, wherein a blob is a set of contiguous pixels which possibly represents a character or a portion of a character in the image. Next, the system analyzes the blobs to dynamically determine a “noise threshold” for the blobs. The system then removes blobs from the image which are below the noise threshold.

Abstract: Video control signals are received at a video input port of a system. A determination is made whether the video control signals are valid or invalid. When video control signals represent a valid video signal, providing a delayed representation of a control signal to a synchronization input of a display engine of the system, and when the video control signals represent an invalid video signal, providing a an alternative signal to the synchronization input of the display engine.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A dithering pattern that is generated based on a spatial operation is used for a Bit-Depth Extension (BDE) technique for preventing contouring artifacts in an image displayed by a display having a bit-depth that-is less than the bit-depth of the image. The dithering pattern can be based on achromatic visual model or a spatio-chromatic visual model. The dither pattern is formed by shaping a pseudo-random noise signal by an equivalent noise visual model that is based on an array of pixels. Alternatively, the array of pixels is based on an image, or a determinate array of pixels.

Abstract: A technique for the modification of sub-pixels to hide defects for defective sub-pixels.

Abstract: An image processing apparatus processes input pixel data and outputs the processed pixel data as output pixel data. The image processing apparatus includes an input reliability calculation section for calculating an input reliability indicating the reliability of the input pixel data, an output reliability calculation section for calculating an output reliability indicating the reliability of the output pixel data, a motion-amount detecting section for detecting the amount of the motion of the input pixel data, a compensation section for compensating the output reliability according to the amount of the motion, and a processing section for processing the input pixel data according to the input reliability and the compensated output reliability and for outputting the output pixel data.

Abstract: A processing circuit for a sync signal includes a trial circuit and a windowing circuit. The trial circuit includes a counter that generates a count value proportional to the duration between successive sync pulses. When the count value reaches a trial sync spacing count value, a trial window signal is created and the counter is reset. If a predetermined number of subsequent sync pulses occur within the trial window signal, the sync spacing count value is confirmed and stored in a sync spacing register. The windowing circuit includes a counter that generates a count value proportional to the duration between successive window signals, and compares the count value to the value stored in the sync spacing register to generate a window signal. The window signal is compared with the sync signal pass valid sync signals.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A numerically controlled oscillator (15) clocked by the system clock generates a phase lock reference signal for locking to the incoming video signal. Phase detection means logic unit (42, 74) sense a static phase offset magnitude from an ideal 90° phase offset between the digitized color sub-carrier burst component and the numerically controlled oscillator output signal. In accordance with the sensed static offset, a static phase error nulling circuit (70) generates a compensating offset in accordance for input to the system clock (27) to drive the static offset to zero, thus achieving frequency and phase locking.

Abstract: An image processing apparatus processes input pixel data and outputs the processed pixel data as output pixel data. The image processing apparatus includes an input reliability calculation section for calculating an input reliability indicating the reliability of the input pixel data, an output reliability calculation section for calculating an output reliability indicating the reliability of the output pixel data, a motion-amount detecting section for detecting the amount of the motion of the input pixel data, a compensation section for compensating the output reliability according to the amount of the motion, and a processing section for processing the input pixel data according to the input reliability and the compensated output reliability and for outputting the output pixel data.

Abstract: A method of detecting both linear and non linear noise in video data. Linear noise is detected on a line-by-line basis, by blocks within each line. Non linear noise is detected during horizontal blanking periods. The method provides a noise floor value for linear noise and an impulse noise flag for non linear noise, both of which are delivered to a noise reduction filter.

Abstract: Enhancement of contours in images that are noisy or otherwise corrupted is important in medical imaging, scanning for weapons detection, and many other fields. Here, the Curve Indicator Random Field (CIRF) is used as a model of uncorrupted images of contours for constructing filters with biased CIRF posterior mean approximations involving a coupled nonlinear system of equations with a number of adjustable parameters.

Abstract: Enhancement of contours in images that are noisy or otherwise corrupted is important in medical imaging, scanning for weapons detection, and many other fields. Here, the Curve Indicator Random Field (CIRF) is used as a model of uncorrupted images of contours for constructing linear, quadratic and cubic Volterra filters involving a number of adjustable parameters.

Abstract: A mask circuit masks a digital video signal so that a video signal of an analog video signal is not outputted for a predetermined period after the start of output of a horizontal synchronizing signal of the analog video signal. A period of masking the digital video signal by the mask circuit is set in a control register, and the control register transmits the masking period to the mask circuit. A digital video signal to analog video signal converting unit converts the digital video signal masked and outputted from the mask circuit into an analog video signal. Thus, by setting in the control register the period of masking the digital video signal until the video signal of the analog video signal is stabilized, a digital video encoder can output a stable video signal.

Abstract: Successive values of a horizontal phase of a video signal are determined a predetermined integer number of video lines after the successive occurrences of vertical synchronization pulses. The successive values of a parity bit are updated according to the successive values of the horizontal phase. Indications on the parity of the fields are provided from the successive values of the parity bit.

Abstract: An image processing apparatus processes input pixel data and outputs the processed pixel data as output pixel data. The image processing apparatus includes an input reliability calculation section for calculating an input reliability indicating the reliability of the input pixel data, an output reliability calculation section for calculating an output reliability indicating the reliability of the output pixel data, a motion-amount detecting section for detecting the amount of the motion of the input pixel data, a compensation section for compensating the output reliability according to the amount of the motion, and a processing section for processing the input pixel data according to the input reliability and the compensated output reliability and for outputting the output pixel data.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: A system and method of reducing an effect of signal distortion from reflection on a transmission line include changing at least one of a pedestal voltage level on the transmission line and a signal threshold voltage level in a processor coupled to the transmission line, such that the pedestal voltage level and the signal threshold voltage level are not substantially equal after the changing, and such that the effect of signal distortion from reflection on the transmission line is reduced.

Abstract: Methods and apparatus are described for time-correct combination of two data streams, particularly video data streams. In this case, a sync signal of the first video data stream is a horizontal sync signal. In this case, methods and apparatus are provided to combine the two video data streams in a pixel-precise manner, even though time base error, i.e. discontinuities occur in the second video data stream.

Abstract: A phase-locked loop is provided which is operable to lock the sampling clock (pixel clock) to the incoming horizontal sync pulse contained within composite video information. Given the input signal is a VCR signal or a normal noise-free signal, there exists two modes of operation, coarse lock mode and fine lock mode, which are used in controlling the phase-locked loop. In the coarse lock mode, coarse corrections are made to a horizontal discrete time oscillator so that a fast lock may be achieve using the fine lock mode. Coarse corrections are based on a normalized sum of weighted pixels collected within a narrow gate window. Lock is achieved when the falling edge is centered within the window. Given the input signal is a television signal having noise, there exists one mode of operation where the flat window phase detector is used instead of coarse lock mode to bring the sync edge to fall within the window, where the flat window normalization constant is tuned.

Abstract: An apparatus (100) for isolating a noise intolerant device (110) from a source of noise includes a digital bus (104/105). A processor (101) outputs clock signals and first data signals and receives second data signals over the digital bus (104/105). A bi-directional buffer (109) is coupled between the digital bus (104/105) and the noise intolerant device (110) disposed in a tuner module. The apparatus (100) operates such that, in dependence upon a control signal, the bi-directional buffer (109) selectively passes the clock signals and the first data signals from the digital bus (104/105) to the noise intolerant device (110), and the second data signals from the noise intolerant device (110) to the digital bus (104/105).

Abstract: A ringing detector detects mosquito noise and ringing for outputting an image signal smoothed by a horizontal/vertical high-pass filter when mosquito noise and ringing are detected while outputting the image signal as such when neither mosquito noise nor ringing is detected, thereby properly correcting the image signal without reducing the texture specific to the image signal also in a portion continuously exhibiting fine details.

Abstract: A method of synchronizing a watermark decoder with a watermark encoder uses a spatio-temporal (3D) synchronization pattern added to a data pattern to produce a watermark pattern for embedment into a signal. The spatio-temporal synchronization pattern is formed by multiplying a spatial (2D) synchronization pattern with a pseudo-noise sequence for a block of signal frames having a duration of N frames. Quadrature carrier modulation may be used to increase detectability of the watermark pattern at the watermark decoder. The watermarked signal is correlated with the spatial synchronization pattern to recover a temporal synchronization signal that is used to determine a temporal offset between the watermark encoder and watermark decoder. The temporal offset is then used to synchronize the watermark decoder with the watermark encoder.