Abstract: A method of generating an upsampled target pixel positioned between two lines of input source data includes the step of comparing pixels of different lines of the source data in a region surrounding the upsampled target pixel to be generated in at least two different directions. An interpolation direction based on the comparison is selected and interpolations between selected pixels of the source data in the determined interpolation direction are carried out to compute intermediate pixels on a line segment passing through the upsampled target pixel. An interpolation between the intermediate pixels is carried out to generate the upsampled target pixel. An apparatus for performing the method is also disclosed.

Abstract: The present invention relates to a video signal processing apparatus for converting video signals based on a desired transmission system such as NTSC, PAL, MUSE or any other system so as to conform to a display unit of a desired screen system such as XGA, VGA or the like. The apparatus has a feature that it is provided with a PLL circuit for changing a sampling frequency used by an analog-to-digital converter for converting inputted video signals into digital signals in accordance with the sort of the transmission system of the video signals, and a controller for controlling picture element interpolation of the digital signals performed by a picture image magnifying circuit for magnifying the video signals horizontally and vertically, in accordance with the sort of the transmission system of the video signals.

Abstract: In an image reader, a main scanning start point of a magnification-changing processing is stored in a main scanning start point register. An increment corresponding to a magnification-changing ratio is stored in an incremental register. A pixel number to be outputted as a magnification-changing output is stored in a multiple-changing output pixel number register. A pixel counter counts the number of pixels to be outputted as the magnification-changing output. An adder serially adds an increment to the main scanning start point and outputs it to a latch. A line memory stores original image data to be read, and the sum of the output value of the latch and +1 is given as a read address. A mean value arithmetic unit calculates a mean value of two adjacent pixels and outputs it as data after the magnification-changing processing.

Abstract: A video apparatus with image memory function has a memory of three ports (one for write, two for read), memory read control units corresponding to two independent read ports and adapted to read a desired area (first area) from a first read port and an area (second area) which contains the first area and is wider than the first area from a second read port, and a memory write control unit. With this construction, an input video signal is written to the memory, starting with a write head address designated by the memory write control unit, the first and second fields to be read during the next field are determined during the period of vertical blanking, a next write head address is determined to be after the first area, and a signal of the first area is delivered as an output video signal.

Abstract: An image control device for use in the computer system. The computer system includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. Writing of an image system signal into the video memory is controlled by supplying a first write address to the video memory. Reading of an image signal out of the video memory is controlled by supplying a read address to the video memory. The operation of reading the image signal out of the video memory independently changes a display part and a magnification of an image represented by the image signal read out of the video memory so that the display part of the image is displayed by the magnification on the display device.

Abstract: Methods and apparatus for generating pixel values in a magnified destination image of an object are provided. The pixel values in the destination image are generated from a source image of the object. A value of a first pixel in each row of the destination image is determined by transforming the first pixel to a first resampled point in the source image and by vertical interpolation between vertically-aligned neighbor pixels to provide intermediate pixel values followed by horizontal interpolation between the intermediate pixel values to provide the value of the first pixel. Each subsequent pixel value that has the same neighbor pixels as a previous resampled point is determined by transforming the subsequent pixel to a subsequent resampled point and by a single horizontal interpolation between the intermediate pixel values of the previous resampled point.

Abstract: An intuitively operated Electronic Program Guide (EPG) which presents program guide information in table form at two levels of resolution. Schedule information is presented in icon form over a long time window while textual information is presented for a viewer-selected time slot. The selected time slot may appear to be a magnified representation of the long time window view. In this way, a television screen of conventional resolution may present at least five hours of schedule information for eight channels. The viewer may operate the Electronic Program Guide (EPG) intuitively with simple remote control commands.

Abstract: In the image signal processing apparatus in this invention, control is carried out in such a manner that an enlarged image signal based on an image signal stored in a memory is produced a predetermined period of time after the image signal was written into the memory, a blanking signal is generated at a predetermined period of time after a further blanking signal included in the image signal applied into the memory occurs, so that during the blanking period occurring in the image signal, the blanking signal is produced, and during periods outside this blanking period, the output is changed over for the enlarged image signal produced from the memory so that the image signal may be enlarged in a stable manner, and the construction and work involved in circuit adjustment may be simple.

Abstract: In a picture signal decoding method, preceding of the display operation to the decoding operation can be prevented as to a bidirectional predictive picture. When the user specifies an arbitrary magnification display mode in which a part of a decoded picture is magnified to an arbitrary size and displayed on a display screen, the decoding operation of an input picture signal which corresponds to a bidirectional predictive picture in input picture signals is started from a signal portion corresponding to the input display start position. Thereby, a picture signal decoding apparatus in which decoding operation can always be finished before display operation starts, can be accomplished with a simple construction.

Abstract: An improved double picture producing apparatus for a wide screen television capable of concurrently achieving an aspect ratio conversion and a double picture display using a picture zooming up function of an aspect ratio conversion, which includes a clock generating unit for receiving a horizontal synchronous signal and for outputting a writing clock signal, a reading clock signal, and a mode selection signal; a decimating unit for counting the writing clock signal outputted from the clock generating unit and for outputting a writing address and a reading address in accordance with a mode selection signal; a double picture video signal generating unit for receiving a first video signal and a second video signal which are aspect-ratio-converted by the first and second zooming units and for outputting a video signal of a double picture by dividing the number of scanning lines of the video signals in half; and a video signal selection unit for receiving first and second video signals aspect-ratio-converted by th

Abstract: The horizontal processing circuits subject the image data input respectively to the compression processing or the expansion processing in the horizontal direction and output said processed image data. The transfer means composed of the bus controller 338 and the bus 333 transfers respective image data from the horizontal processing circuits time-divisionally. The vertical processing circuit 334 subjects the respective transferred image data to the compression processing or the expansion processing in the vertical direction time-divisionally. The post-processing circuit 335 and the display device 464 display the image data from the vertical processing circuit 334.

Abstract: A digital zooming system determines subpixel image information by detecting a camera motion component from a dynamic image (pixel images from across more than one image frame), the motion component being generated in an interval less than the standard interval between pixels. The system enhances the resolution of the magnified image by synthesizing the image signal through an IIR filter. This preserves image quality when magnifying the input image by a digital zoom. Accordingly, a high resolution image is obtained, and degradation and noise generated by interpolating the input image are reduced.

Abstract: There is provided an image sensing apparatus which comprises a detecting part for detecting an optical characteristic of a photographic optical system, an image sensing part for converting an optical image photographed by the photographic optical system into an electrical signal, a combining part for combining character information with image information outputted from the image sensing part, and a control part for controlling a combining operation of the combining part in accordance with an output of the detecting part.

Abstract: A video method and system for automatically tracking a viewer defined target within a viewer defined window of a video image as the target moves within the video image by selecting a target within a video, producing an identification of the selected target, defining a window within the video, utilizing the identification to automatically maintain the selected target within the window of the video as the selected target shifts within the video, and transmitting the window of the video.

Abstract: The present invention realizes high-speed transfer of video data into a video memory. Addresses used in DMA transfer operation are calculated by simple arithmetic operation in a DMA address operation unit of a DMA controller. Video data are transferred according to the addresses at a high speed to an arbitrary position in a VRAM. An FIFO memory unit can expand and reduce a video image by desirable magnifications in both vertical and horizontal directions during DMA transfer of video data.

Abstract: There is provided an image sensing apparatus which comprises a detecting part for detecting an optical characteristic of a photographic optical system, an image sensing part for converting an optical image photographed by the photographic optical system into an electrical signal, a combining part for combining character information with image information outputted from the image sensing part, and a control part for controlling a combining operation of the combining part in accordance with an output of the detecting part.

Abstract: A digital zooming system comprises a recording medium for saving a digital video signal forming a predetermined color array; a sum/difference signal separator for receiving the signal from the recording medium and then obtaining a sum value and difference value with respect to two neighboring pixels among the pixels of the predetermined color array; a correlation calculating circuit comprising a sum-value interpolation calculator for performing horizontal and vertical interpolations with respect to the sum-value according to a zooming ratio and a difference-value interpolation calculator for calculating the horizontal and vertical interpolations; a sum/difference signal mixer for receiving the interpolated sum value and difference value and producing the original digital video signal; a digital-to-analog converter for converting the digital video signal from the mixer into analog form; an address generator circuit for generating an address signal for reading or writing the data recorded on the recording mediu

Abstract: A double scan circuit has first and second data converters for converting n-bit real line data and n-bit interpolated line data into 2n-bit data; first and second RAMs in which the real line data and the interpolated line data are stored, respectively; a memory controller for generating a write/read control signal for the first and the second RAMs, a write address and a read address whose speed is double that for the write address, for outputting them to the first and second RAMs, and for generating a mixing control signal for mixing the original line data and the interpolated line data stored in the first and second RAMs for double scanning; and a multiplexer for selecting one between the 2n-bit real line data and the 2n-bit interpolated line data generated from the first and second RAMs in accordance with the mixing control signal and the real/interpolated line control signal and for producing the selected one as n-bit double scan data.

Abstract: An apparatus for converting an input video signal to a modified video signal comprises a memory for storing data corresponding to the input video signal, an address signal generating device for reading data from the memory and an interpolating filter for interpolating the data read from the memory to obtain a modified video signal. The data are stored and read from the memory using a clock having a predetermined frequency. However, since the number of addresses being read in one horizontal display varies with the conversion rate of video signals, the length of one horizontal display of the modified video signal is different from that of the input video signal.

Abstract: A circuit for compressing and expanding video color component data comprises a FIFO line memory and a delay circuit. A timing circuit generates control signals for writing data into the line memory and for reading data from the line memory to compress and expand the data. The delay circuit matches the data compressed or expanded in the FIFO line memory to luminance data which is similarly compressed or expanded. A switching network selectively establishes a first signal path in which the line memory precedes the delay circuit for implementing the data expansion and a second signal path in which the delay circuit precedes the line memory for implementing the data compression. The switching network is controlled according to selected display formats requiring compression or expansion, for example by a microprocessor.

Abstract: A video signal processing apparatus includes an A/D converter for converting an analog video signal to a digital video signal. Also included is a 3-dimensional scanning line interpolating unit for outputting an original video signal and an interpolating signal which is synchronized with the original video signal and which includes interpolated scanning lines. A magnification processing unit and a switching signal generating unit are also provided. The switching signal generating unit is for generating a switching signal corresponding to a vertical magnifying power. Further, a switching unit is included for switching between the original video signal and the interpolated video signal according to the switching signal and for outputting the switched signal.

Abstract: Video luminance data from a video signal is selectably compressed and expanded in a first signal path including a first line memory. A second line memory in a parallel signal path processes video chrominance data from the video signal. A control circuit generates respective timing signals for writing data into each of the first and second memories and for reading data from each of first and second the line memories. A timing delay circuit for the control circuit, has video compression and expansion modes of operation. During the compression mode, reading of the second line memory is delayed relative to writing of the second line memory. During the expansion mode, writing of the first line memory is delayed relative to writing of the second line memory or reading of the second line memory is delayed relative to writing of the second line memory. The duration of the timing delays can be selected from a range of values.

Abstract: A wide-screen television receiver capable of converting a TV signal of a non-aspect ratio into a signal of a wide aspect ratio which can be displayed on a wide screen of the wide aspect ratio and previously visually informing the user of what part of the image of the non-aspect ratio TV signal is converted in its aspect ratio and displayed on the wide screen. The receiver includes the interpolation scan speed conversion circuit, the mode setting circuit, the aspect ratio converting circuit, the wide cursor adding circuit and the wide display. The interpolation scan speed conversion circuit makes a series of processes such as Y/C separation and scan line interpolation for the input video signal supplied via the input terminal. The aspect ratio converting circuit compresses the video signal from the interpolation scan speed conversion circuit in the horizontal direction by use of a memory. The magnification processing circuit is provided after the aspect ratio converting circuit.

Abstract: A line memory and control system comprises a line memory, for example a first in first out (FIFO) device. A comparator compares a first value, specifying a location in the horizontal line period where reading or writing of the line memory is to begin, with a second value, fixing pixel location within each line period. A register stores the number of data samples stored in the line memory. A counter counts the number of data samples which have actually been written into the line memory or read from the line memory. The counter has an output of the comparator as a first input and the number of data samples previously stored in the line memory as a second input. In the case of both compression and expansion, a line memory control system assures that the number of samples written into each FIFO line memory be the same as the number of samples read out of each FIFO line memory.

Abstract: A video system comprises a video display having a wide format display ratio for displaying a video signal. A signal processor has an interpolator and a first in first out line memory having asynchronous write and read ports for selectably expanding and compressing a picture represented by data in the video signal. The picture is cropped to define a subset of the picture for display by controlling writing of the data into the line memory. A microprocessor for controls provides control signals with selectable time durations and selectable phases relative to a synchronizing component of said video signal for selecting boundaries of the subset of the picture for display. The microprocessor can select the time durations and the phases responsive to user commands.

Abstract: A display system controls vertical zoom and panning. A video display has a first format display ratio. A circuit, for example one generating a raster, maps on the video display an adjustable picture display area represented in a video signal having a vertical synchronizing component. The picture represented in the video signal has a second format display ratio. A vertical height control circuit, for example one controlling the vertical height of the raster by controlling the vertical deflection current, selectively enlarges the picture display area relative to the video display. A panning control circuit adjusts in phase a vertical blanking interval relative to the vertical synchronizing component to control which portion of the enlarged picture area is displayed and which portion is not displayed. The format display ratios can be the same or different, for example 16.times.9 for the video display and 4.times.3 for the picture, in the latter case.