Abstract: A power supply control circuit arranged to prevent a steady power loss from occurring in an input filter connected to an alternating current power source. In order to detect that an AC input has been turned off, diodes are connected to AC lines, thus detecting a full-wave rectified waveform. This detected voltage is compared with a reference voltage by a comparator. An output signal of the comparator is input into the reset terminal of a timer circuit having a time measurement period longer than the power source frequency of an alternating current power source. A switch element of a discharging circuit is turned on by an output signal of the timer circuit.

Abstract: There is provided a delta-sigma A/D converter including a first integrator, a second integrator located on an output side of the first integrator, a quantizer located on an output side of the second integrator, and a first current D/A converter receiving an output of the quantizer and providing a negative feedback signal to an input side of the quantizer.

Abstract: An apparatus includes a voltage controlled oscillator for outputting a clock signal having an oscillation frequency in accordance with an input voltage; a convertor for converting the analog video signal inputted from the exterior into the digital video signal synchronizing with the clock signal outputted from the voltage controlled oscillator; a phase difference detector for detecting a phase difference between the composite synchronizing signal in the analog video signal and a feedback signal which corresponds to the clock signal from the voltage-controlled oscillator; and a voltage control unit for controlling the input voltage of the voltage controlled oscillator to change in response to the phase difference detected by the phase difference detector when the phase difference is within the certain range, and to maintain the input voltage intact when the phase difference is in exceed of the certain range.

Abstract: A method, and apparatus, and logic encoded in one or more computer-readable media to carry out a method. The method is to sample analog video at a sample clock rate and at a phase selected from a set of phases based on a quality measure determined from the sampled video. The quality measure is based on statistics of pixel to pixel differences in a coordinate of the generated digital video that have a magnitude exceeding a pre-determined threshold.

Abstract: Provided is a video signal processing device capable of judging the viability of phase locking at a PLL circuit and, in accordance with the judgment, automatically switching between the PLL circuit and a DLL circuit to use to generate a sampling clock of an input analog video signal, the device including an AD converter for AD converting an analog video signal, and a clock signal generating circuit for supplying a clock signal to the AD converter. The clock signal generating circuit includes: a PLL circuit for generating a first clock signal on the basis of a horizontal synchronous signal acquired from the analog video signal; a DLL circuit for generating a second clock signal on the basis of a composite synchronous signal acquired from the analog video signal; and a clock selecting portion for selecting and outputting either the first clock signal or the second clock signal on the basis of output of a PLL-dedicated phase comparator.

Abstract: An image sensor for high-speed data readout is provided. The image sensor includes a line memory block temporarily storing a digital signal in unit of lines which is generated based on an analog signal output from a pixel array. The line memory block includes a plurality of line memories, a plurality of data line pairs respectively connecting the line memories to a sense amplifying unit, and a plurality of data line prechargers each including at least two precharge units separately connected with a corresponding one of the data line pairs to precharge the corresponding data line pair with a predetermined precharge voltage. Accordingly, the image sensor performs high-speed digital signal readout based on precharge operation of the data line prechargers.

Abstract: A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first dimension of a first length and a second dimension of a second length. Each of the beams spans a portion of the first length of the first dimension and a portion of the second length of the second dimension. The method also includes scrolling the plurality of beams along the second dimension of the spatial light modulator while maintaining at least a first gap between each of the plurality of beams.

Abstract: A shot size identifying device (1) includes an edge detecting element (102) for detecting edges in a frame constituting a video, a connected edge area detecting element (103) for detecting connected edge areas in which the detected edges are connected, an edge area counting element (104) for counting the number of edge areas which is the total number of the detected connected edge areas for each frame, and shot size identifying element (110, 113) for identifying the frame as a long shot if the number of counted edge areas is larger than the threshold value of a first edge area. This makes it possible to easily and immediately identify a shot size.

Abstract: A method for diffusing errors in a display device. Each frame of an input video signal is separated into at least two independent subframes. An error diffusion process is applied to each subframe of at least two independent subframes. The errors transmitted reciprocally from subframes are partially mixed, and the error diffusion process is applied to the mixed errors at each independent subframe.

Abstract: A system such as an audio and/or video system includes a multiplexed analog-to-digital converter arrangement. The arrangement includes an ADC for converting first and second analog signals to first and second digital signals, respectively, and for outputting the first digital signal during a first time interval and outputting the second digital signal during a second time interval. A digital filter is provided for filtering the first and second digital signals to generate first and second filtered signals, respectively, and for outputting the first and second filtered signals in a time-aligned manner during a third time interval.

Abstract: Structures and methods are provided for generating a digital display signal from an analog signal that is limited to 2N discrete analog levels and from a synchronization signal that defines spatial order for the digital display signal. These structures and methods accurately synchronize digitizers to the analog signal and they follow from a recognition that enhanced digitizer resolution will generate code patterns which easily distinguish between correct and incorrect sampling of the analog signals. Accordingly, the digitizers quantize the analog samples into an M-bit digital display signal wherein M exceeds N.

Abstract: An A/D converter updates its reference potential so that it coincides with an analog potential of a video signal. The A/D converter changes a variable voltage range of the reference potential during the same horizontal synchronizing period based upon a horizontal synchronizing signal. It is possible to correctly discriminate data superposed on the video signal even if an analog potential of the video signal considerably varies during the same horizontal synchronizing period.

Abstract: A method and apparatus for providing binary digital TV data from a structured data format, wherein data in a structured data format according to a predetermined intermediate data format definition is converted into binary digital TV data of a predetermined technical standard, a conversion algorithm being applied to a structured data format according to a user data format definition so as to convert the data in the structured data format according to the user data format definition to data in the structured data format according to said intermediate data format definition for conversion into the binary digital TV data.

Abstract: An image binarization method having highest fidelity for multi-digitized luminance data, and a binary image creation method by which images can be obtained in real-time without post-processing. Thresholds in binarization are not fixed, but set in accordance with changes in luminance, thus allowing real time images to be obtained.

Abstract: An analog Y signal input from an input terminal 101 is clamped at a pedestal level in a clamp circuit 102, and then, is converted to a digital image signal in a quantization circuit 103. The pedestal level Dp of the digital output D(t) 113 is stored in a register 702. A predetermined value Dref (Dref=0 for the Y signal) is subtracted from Dp in a subtracter 802. The subtraction output 806 is subtracted from the digital output 113 in a subtracter 803. The subtraction output 805 (D(t)?(Dp?Dref)) is a signal for which a shift caused by a variation in the precision of the clamp circuit 102 and the quantization circuit 103 has been compensated for. The subtraction output 805 is limited to a predetermined dynamic range by an overflow limiter circuit 807, and output as Dout.

Abstract: A solid state imager includes an arrangement for converting analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output providing a ramp signal with a level that varies corresponding to the contents of the counter. Latches or equivalent digital storage elements are each associated with a respective column. A counter bus connects the counter to latch inputs of said latches, and comparators associated the columns gate the latches when the analog ramp equals the pixel value for that column. The contents of the latch elements are transferred sequentially to a video output bus to produce the digital video signal. There can be additionally black-level readout latch elements, for storing a digital value that corresponds to the dark or black video level, and a subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer latches can be employed.

Abstract: A system for receiving and analyzing at least one inband user data packet within a CATV video signal. The system includes a data detector, a data processor and a memory. The data detector receives video signal samples of the data packet. The data detector includes a data slicer used to determine a threshold level based on a clock sync byte located in the data packet. The threshold level is compared to subsequent video signal samples of the data packet. The data processor determines the destination of the data packet. The memory selectively stores the data packet until it is required by the data processor.

Abstract: A variable voltage range of a reference potential is changed during the same horizontal synchronizing period. It is possible to correctly discriminate data superposed on a video signal even if an analog potential of the video signal considerably varies during the same horizontal synchronizing period.

Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.

Abstract: The present invention provides an image binarization method in a form with the highest fidelity for multi-digitized luminance data, and a binary image creation method by which images can be obtained in real-time without post-processing.

Abstract: A process for correcting the input-output correspondence of an analog-to-digital converter includes calculating the equation of the actual input-output correspondence, for known input values, during programmed conversion suspension periods. A comparison with the ideal conversion line subsequently makes it possible to calculate the necessary offset and gain corrections. The process is applied to the digital conversion of a plurality of component video signals.

Abstract: In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.