Color Signal Patents (Class 348/582)
  • Patent number: 5991463
    Abstract: A method of generating an upsampled target pixel positioned between two lines of input source data includes the step of comparing pixels of different lines of the source data in a region surrounding the upsampled target pixel to be generated in at least two different directions. An interpolation direction based on the comparison is selected and interpolations between selected pixels of the source data in the determined interpolation direction are carried out to compute intermediate pixels on a line segment passing through the upsampled target pixel. An interpolation between the intermediate pixels is carried out to generate the upsampled target pixel. An apparatus for performing the method is also disclosed.
    Type: Grant
    Filed: November 8, 1995
    Date of Patent: November 23, 1999
    Assignee: Genesis Microchip Inc.
    Inventors: Lance Greggain, Calvin Ngo
  • Patent number: 5959685
    Abstract: According to this character display apparatus, a limit of a frequency band of a character display signal is removed and small characters, etc., also can be displayed satisfactorily. A sync signal from a sync separating circuit (4) is supplied to a character generating circuit (8) in which a display signal of arbitrary characters or the like is formed by RGB three primary color signals in synchronism with predetermined dot clocks. The thus formed display signal is supplied to a line memory (9) and dot clocks are supplied to the line memory (9) and thereby the display signal is written in the line memory (9). Further, dot clocks are supplied to a multiplying circuit (10) and clock multiplied with an arbitrary multiplying ratio are supplied to the line memory (9) so that the written display signal is read out from the line memory (9).
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: September 28, 1999
    Assignee: Sony Corporation
    Inventor: Akira Yoshimi
  • Patent number: 5745186
    Abstract: A 4:4:4 component video signal comprising a luminance signal Y and color-difference signals Cb and Cr is transformed to a 4:1:1 component coded video signal coded by a coding device, reducing processing is carried out after transformation and the result is written into the frame memory based on an enable signal. At this point, the pulse number of the enable signal ENy of the reduced luminance signal is counted, the differential between the horizontal pixel number when the reduced color-difference signals are decoded to the original 4:4:4 component video signal and the horizontal pixel number of the reduced luminance signal is determined, a dummy pulse of this differential is generated and the dummy pulse portion only of the writing address of the frame memory for the reduced luminance signal is shifted backwards. Reduced signals read out from the frame memory are outputted after being decoded to the original 4:4:4 component video signal by the decoding device.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: April 28, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yutaka Shimizu, Mitoku Kamei
  • Patent number: 5703659
    Abstract: A method is provided for reducing or magnifying the picture size of a video composite signal with the use of fewer memories than a conventional video composite signal processor which processes pixel data after being converted into R, G, B signals. A video composite signal is directly converted into digital data and sampled with a sampling frequency of four times the color sub-carrier and stored in a pair of field buffers to be processed for picture size reduction or magnification. The digital data are reduced or multiplied in units of pairs of data with a phase difference of .pi./2. Color information is reproduced from corresponding two pairs of data of two adjacent fields having a phase difference of .pi..
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: December 30, 1997
    Assignee: NEC Corporation
    Inventor: Kazuyoshi Tanaka
  • Patent number: 5668604
    Abstract: In a structure composed having a one-bit counter, a D-FF, a selector, and an AND gate, while the signal level of a thin-out signal is low, a read clock signal of a line memory is thinned out. Thus, video signals (a Y signal, a CR signal, and a CB signal) read from a line memory are horizontally magnified. At this point, both edges of a low portion of the input thin-out signal are synchronized with even number data of color difference signals (CR/CB) read from the line memory after a start signal that is a video signal read start signal is input.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: September 16, 1997
    Assignee: NEC Corporation
    Inventors: Hiromitsu Takano, Nobuya Nakamoto
  • Patent number: 5666548
    Abstract: A computer implemented process for extracting and processing information in a vertical interval of a video signal comprising a plurality of video lines selects a portion of the vertical interval from the video lines as the video lines are coupled to a computer bus, detects information stored in the selected portion, places the detected information on the bus of the computer, processes the detected information according to the portion of the vertical interval from which it is selected, and processes the video lines responsive to the detected information from the vertical interval.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: September 9, 1997
    Assignee: Radius Inc.
    Inventors: Dennis L. Grimm, Erik A. Gutfeldt, Gregory M. Millar, Terence E. Worley