Abstract: This invention discloses an image pickup device and an image synthesis method thereof The image pickup device comprises an image-pickup module, an image-synthesis module, a database and a processing module. The image-pickup module captures a plurality of temporary images of a scene. The image-synthesis module extracts a part of each temporary image and combines the parts to form a panorama temporary image, and splits the panorama temporary image into a plurality of zone-areas according to at least one threshold value and a panorama luminosity histogram. The database stores a lookup table for recording a plurality of exposure values. The plurality of the exposure values correspond to luminance values of the zone-areas respectively. The processing module obtains the plurality of exposure values corresponding to the luminance values and obtains a weighting-exposure value by an equation, and controls the image-pickup module to capture the panorama image according to the weighting-exposure value.

Abstract: There is provided a delta-sigma A/D converter including a first integrator, a second integrator located on an output side of the first integrator, a quantizer located on an output side of the second integrator, and a first current D/A converter receiving an output of the quantizer and providing a negative feedback signal to an input side of the quantizer.

Abstract: A high dynamic range sensitive sensor element or array is provided which uses periodic sampling phase domain integration techniques to accurately capture high and low intensity images. The sensor element of the present invention is not limited by dynamic range characteristics exhibited by prior art solid-state pixel structures and is thus capable of capturing a full spectrum of electromagnetic radiation to provide a high quality output image.

Abstract: Systems and methods are provided for upscaling a digital image. A digital image to be upscaled is accessed, where the digital image comprises a plurality of pixel values. A first half pixel value is computed for a first point in the digital image based on a plurality of pixel values of the digital image surrounding the first point and an activity level. A second half pixel value is computed for a second point in the digital image, and an interpolated pixel of an upscaled version of the digital image is determined using a plurality of the pixel values, the first half pixel value, and the second half pixel value.

Abstract: A method and system for communicating text descriptive data has a receiving device that receives a data signal having text description data corresponding to a description of a video signal. A text-to-speech converter associated with the receiving device converts the text description data to a first audio signal. A display device in communication with the text-to-speech converter converts the first audio signal associated with the receiving device to an audible signal.

Abstract: A high dynamic range sensitive sensor element or array is provided which uses phase domain integration techniques to accurately capture high and low intensity images. The sensor element of the present invention is not limited by dynamic range characteristics exhibited by prior art solid-state pixel structures and is thus capable of capturing a full spectrum of electromagnetic radiation to provide a high quality output image.

Abstract: In a receiver, a synchronization circuit (MIX2, OSC, C1, R1) provides a set of oscillator signals (OSI, OSQ) that are synchronized with a carrier of an amplitude-modulated signal. The set of oscillator signals (OSI, OSQ) comprises a quadrature oscillator signal (OSQ), which is substantially 90° phase shifted with respect to the carrier of the amplitude-modulated signal. A quadrature mixer (MIX2) mixes the quadrature oscillator signal (OSQ) with the amplitude-modulated signal so as to obtain a quadrature mixer output signal (MO2a). A phase-error corrector (PEC) adjusts the phase of the oscillator signals in response to a variation in the magnitude of an alternating current component (AC) in the quadrature mixer output signal (MO2a).

Abstract: A digital video decoder architecture is provided wherein chrominance values are determined first, then luminance values are determined, in part, based on the previously determined chrominance values. In this architecture, luminance separation occurs after and based on one or more chrominance values.

Abstract: An apparatus for recovering a chrominance signal from a sequential color with memory (SECAM) composite video baseband signal (CVBS), and more particularly, to a frequency demodulator and method of recovering a SECAM chrominance signal which can utilize both a real number portion and an imaginary number portion, and generate a frequency-demodulated chrominance signal using an arctangent approximation, and thereby can simplify a circuit configuration of a frequency demodulator to perform a fixed-point calculation is provided.

Abstract: A method for removing color noise on a slowly varying component contained in color difference component image data of image data which is imported from an image sensor and converted to brightness and the color difference component image data, includes the steps of: sampling pixels of said color difference component image data by thinning out according to a first defined sampling format when not performing a color noise removal process on the slowly varying component; determining if the color noise removal process is necessary to be performed or not; producing the color difference component image data, corresponding to a compressed image data size smaller than an image data size without said color noise removal process, by thinning out according to a second defined sampling format when performing said color noise removal process; and recording the color difference and brightness component image data.

Abstract: A delay circuit is disclosed. A switched-capacitor group includes a plurality of switched-capacitor units, each of which have a switching element and a capacitive element charged/discharged by turning on/off the switching element. The switched-capacitor units are connected such that the input signal is input in common to all of the switched-capacitor units and the capacitive elements are charged as well such that the capacitive elements are discharged to allow the output signal to be output from the switched-capacitor units. A switching control unit performs on/off control of the switching elements to cause the capacitive elements to be charged in sequence based on the input signal, causing the capacitive element charged last time to be discharged to allow the output signal to be output in sequence from the switched-capacitor units, and performs control of all of the switching elements to be turned off upon on/off switching of the switching elements.

Abstract: A delay circuit acquiring an output signal delayed from an input signal, comprising: a switched capacitor group that includes a plurality of switched capacitor units, wherein each of the plurality of switched capacitor units has a charging MOS transistor and a discharging MOS transistor, and a capacitive element which is connected to sources of the charging and the discharging MOS transistors; and a switching control unit that performs on/off control of the charging and the discharging of the MOS transistors, to cause each of the capacitive elements to be charged in sequence based on the input signal, and that, upon causing the each of the capacitive elements to be charged in sequence based on the input signal, causes the capacitive element charged last time to be discharged, to allow the output signal to be output in sequence.

Abstract: A high dynamic range sensitive sensor element or array is provided which uses phase domain integration techniques to accurately capture high and low intensity images. The sensor element of the present invention is not limited by dynamic range characteristics exhibited by prior art solid-state pixel structures and is thus capable of capturing a full spectrum of electromagnetic radiation to provide a high quality output image.

Abstract: A digital video decoder architecture is provided wherein chrominance values are determined first, then luminance values are determined, in part, based on the previously determined chrominance values.

Abstract: When an A/D-converted composite video signal is directly outputted while a system clock frequency is switched so as to execute the determination of a signal system, a digital chroma demodulation system prevents the images displayed by the composite video signals from being distorted in accordance with a switching of the frequency of a system clock. The frequency m (=fsc×n) of the system clock is synchronized with a color burst signal and is set to fall in a predetermined range by changing a coefficient n in accordance with the system color burst signal freguency. Thus, since a composite video signal is A/D-converted in accordance with a substantially constant sampling frequency, the sampling condition such as a sampling frequency and a sampling point is not greatly changed.

Abstract: Chrominance phase error correction circuitry includes a demodulator for demodulating a received video color burst signal into first and second demodulated signals and signal generation circuitry for providing to the demodulator a demodulating signal for demodulating video color burst signal. Phase correction circuitry detects a phase error from the first and second demodulated signals and varies a phase of the demodulating signal to provide a corrected demodulating signal for demodulating a video chrominance signal with the demodulator during an active video period.

Abstract: A time-based, digital FM demodulator circuit receives a stream of digital samples corresponding to an analog FM waveform. The samples are provided to a zero crossing detector, which allows a counter to determine a number of clock cycles between zero crossings. The resolution of this coarse period determination is further refined by an intercept calculation, which further localizes the zero crossing of the FM waveform based on interpolation between samples on either side of the zero crossing. Accuracy of the period determination may be further enhanced by use of a sinusoidal correction filter, which minimizes error caused by the linear interpolation performed on the sinusoidal waveform. Although the FM demodulator circuit is particularly suitable for demodulation of the chroma component of a SECAM video signal, it may advantageously be applied in a wide variety of FM demodulation applications.

Abstract: An NTSC system chrominance signal demodulation apparatus is provided with a clock timing change circuit for burst-locking an input signal under the state where the phase is shifted by 90 degrees for every line, and phase axis rotation circuits for performing phase axis rotation, thereby to enable conversion of the phase axis of the burst signal. Therefore, demodulation of a PAL system chrominance signal can be carried out as well as demodulation of an NTSC system chrominance signal, and thereby demodulation of chrominance signals can be carried out using a common device regardless of the broadcast systems such as NTSC and PAL. Further, demodulation of chrominance signals can be carried out even under adverse conditions such as weak electric field or level compression of the burst signal.

Abstract: A color demodualation device having an AD converter, a phase signal generator, a burst data generator and a multiplier. The AD converter produces digital samples of chrominance signal at a frequency four times a color subcarrier frequency, and the phase signal generator generating a phase signal for identifying phases of a burst signal and color subcarrier signals modulated by respective B-Y and R-Y signals. The burst data generator produce burst data corresponding to the burst signals modulated by respective B-Y and R-Y signals. The burst respective color subcarrier signals according to the phase signal. The multiplier produces products of the burst data and the digital samples of the chrominance signal, from which digital samples of the respective R-Y and B-Y signals are produced.

Abstract: A video decoder for decoding a composite video signal. The decoder includes an analog-to-digital converter (ADC), an input resampler, and a Y/C separator, all coupled in series. The ADC receives and digitizes the composite video signal to generate ADC samples. The input resampler receives and resamples the ADC samples with a first resampling signal to generate resampled video samples. The Y/C separator receives and separates the resampled video samples into luminance and chrominance components. The Y/C separator includes a delay element configured to receive the resampled video samples and provide a variable amount of delay. The variable amount of delay can be adjustable from line to line, and is typically based on an approximated duration of a video line.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: A signal processing system and process for digitally filtering a single tone digital signal is disclosed. The system includes a single tone signal generator, which may or may not perform frequency modulation. The single tone signal generator receives an input signal and generates a frequency indicator which is used internally by the single tone signal generator and is also communicated to a direct realization filter. The direct realization filter uses the frequency indicator to generate a phase offset indicator, which is communicated back to the single tone signal generator. The single tone signal generator uses the frequency indicator and the phase offset indicator to generate a phase-adjusted single tone signal. The direct realization filter generates a filter gain and multiplies the single tone signal with the filter gain to produce a filtered single tone signal.

Abstract: A color demodulation apparatus having color demodulation capabilities as the conventional ones, with its size reduced by sharing part of processing circuit therein is provided. An adder circuit 10 and a SW circuit 11 shift the phase of a ramp wave generated by a VCO circuit 9 alternately 90 degrees and 180 degrees for each clock. A SIN data generator circuit 12 generates a phase alternate SIN wave signal from the shifted ramp wave. A multiplier circuit 3 performs R-Y and B-Y demodulation through multiplexing based on the phase alternate SIN wave signal. An accumulator circuit 6 accumulates burst signals of each of R-Y and B-Y signals of the demodulated, multiplexed signal. A second load hold circuit 8 separately outputs an R-Y burst signal to the VCO circuit 9, and a B-Y burst signal to a comparator circuit 13, constituting two feedback loops. A first load hold circuit 5 separates R-Y and B-Y signals from the multiplexed signal, and outputs these two signals.

Abstract: A system with chrominance delay lines has a first sampled channel including at least one smoothing filter, and has a second unsampled channel. A continuous bypass filter is placed in the second channel to balance the pulse response from these two channels.

Abstract: The demodulating device for a chrominance signal includes an oscillator with a controlled frequency, and an adjuster for adjusting the oscillator frequency as a function of a charge voltage of a memory capacitor. The adjuster preferably includes a fine adjustment channel to output a first adjustment value that depends on the charge voltage of the memory capacitor, and a coarse adjustment channel to output a second adjustment value. The second adjustment value is modified when the charge voltage of the memory capacitor is not within a given range. The device is used, for example, in integrated SECAM decoders.

Abstract: A signal processing system and process for digitally filtering a single tone digital signal is disclosed. The system includes a single tone signal generator, which may or may not perform frequency modulation. The single tone signal generator receives an input signal and generates a frequency indicator which is used internally by the single tone signal generator and is also communicated to a direct realization filter. The direct realization filter uses the frequency indicator to generate a phase offset indicator, which is communicated back to the single tone signal generator. The single tone signal generator uses the frequency indicator and the phase offset indicator to generate a phase-adjusted single tone signal. The direct realization filter generates a filter gain and multiplies the single tone signal with the filter gain to produce a filtered single tone signal.

Abstract: A procamp to color transforms component digital video data. The procamp includes a digital multiplier coupled to receive component digital video data corresponding to at least two different pixel parameters. The digital multiplier is configured to selectively multiply the component video data for different pixel parameters by different factors.

Abstract: A television receiver includes a tuner for receiving either analog or digital signals. Separate analog and digital demodulators are selectively coupled to the tuner through an RF switch that is controlled by the signal from a sync detector in the output of the analog demodulator. The selected one of the demodulators develops an AGC signal that is coupled to the tuner through a current mirror. Operating potential for the demodulators is coupled through the RF switch so that the oscillator in the non-selected demodulator is disabled and precluded from interfering with the oscillator in the enabled demodulator.

Abstract: A microprocessor controlled color phase locked loop is provided which provides flexibility and adaptability for different television standards and sampling rates. Color burst phase error and color burst amplitude information are stored in data registers located at the output of the phase locked loop's low pass filter rather than at the output of the color demodulator.

Abstract: The key component of a digital PAL or NTSC color decoder is a quadrature demodulator for these AM modulated signals. For a SECAM color decoder, however, an FM demodulation is required which is conventionally implemented using a Hilbert filter which is followed by a CORDIC processor and a differentiation stage. It would be advantageous if for multi-standard applications a general-purpose color demodulator for PAL, NTSC and SECAM systems could be implemented on one chip having as much as possible common demodulation processing stages. According to the invention a single common quadrature mixer is used for all three color systems. A resulting bias effect caused by the use of a single mixing frequency is corrected in a clamping stage. The bias effect can also be used for line identification.

Abstract: In a method of demodulating an analog chrominance signal (C), digital quadrature signals are generated (DPA, SIN ROM, COS ROM) for demodulating (MUL DAC U, MUL DAC V) the analog chrominance signal (C) to obtain analog demodulated color difference signals (U, V). A digital phase error signal is furnished (.SIGMA..DELTA.mod) from at least one (V) of the analog demodulated color difference signals (U, V). The digital phase error signal is digitally filtered (DLF) to obtain a phase control signal (K) for the digital quadrature signals generation (DPA, SIN ROM, COS ROM).

Abstract: An apparatus to modulate the digital color signal using a simple circuit that utilizes neither multiplier nor ROMs to multiplying a sine wave and cosine wave. The digital color signal modulating apparatus includes a first selector, a second selector 3, and a third selector. The first selector and the second selector provide the U signal component and the V signal component of the digital color signal to the third selector at a half cycle, rate respectively. The third selector alternately selects one of those signals, which is combined with the sub-carrier wave. For both modulations with the sine wave and with the cosine wave, the input signal is inverted and the fourth selector selects the outputs of the through path and the inversion path in turn, thus producing the modulated outputs.

Abstract: A device and method for generating a composite color signal are disclosed. The device includes a first memory unit for storing digital cosine data, a second memory unit for storing digital sine data, a first arithmetic unit for multiplying digital color difference data Cr input thereto with the digital cosine data, a second arithmetic unit for multiplying digital color difference data Cb input thereto with the digital sine data, and an adder for adding outputs of the first and arithmetic units to generate a digital composite color signal. The method includes the steps of storing digital cosine data and sine data in at least one of first and second memories, modulating digital color data using the stored digital sine and cosine data, and generating a composite color signal using the modulated digital color data.

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format includes input complex filters shared by a timing recovery network (30) and a carrier recovery network (50). The filter network includes a pair of upper and lower band edge filters (20, 22) mirror imaged around the upper and lower band edges of the VSB signal for producing suppressed subcarrier AM output signals. The timing recovery network includes a phase detector (28, 38, 62) and responds to an AM signal derived from the two filters (via 26) for synchronizing a system clock (CLK). The carrier recovery network (50) also includes a phase detector (54, 60, 62, 64), and responds to outputs from one or both of the filters for producing an output error signal (.DELTA.) representing a phase/frequency offset of the VSB signal. The error signal is used to reduce or eliminate the offset to produce a recovered baseband or near baseband signal.

Abstract: A method and apparatus for video filtering filters video frames by determining a set of frames to be used to generate a single filtered frame. This set of frames is then combined to generate a single combined image. In one embodiment, proportions of the luminances for each of four fields from two consecutive frames in an NTSC video signal are combined to generate the single combined frame.

Abstract: A phase error detecting method is applied to a VSB receiver or a QAM receiver. Q-channel data is recovered by digitally filtering transmitted I-channel data, and the phases of the I-channel data and the Q-channel data are corrected according to a fed-back phase error. A decided I-channel level value is chosen approximating the phase-corrected I-channel data among predetermined reference I-channel level values. A phase error value for the received data is obtained by subtracting the decided I-channel level value from the phase-corrected I-channel data, and multiplying the sign of the difference by the difference itself, and applying a weight value from a predetermined weighting function to the phase error value weighted phase error value is fed back to be used for phase correction of received data. Thus, the reliability of phase error detection can be increased by use of the weighting function.

Abstract: A method of digitization of an intermediate frequency signal having a bandwidth that can change from one standard to another and of which one of the frequency limits of this band is substantially constant, wherein before converting the analog signal into a digital signal, the signals of the channels (S.sub.if.sup.N+1, S.sub.if.sup.N-1) adjacent to the frequency band of the signal to be digitized are eliminated in three stages: in a first stage, the signals (S.sub.if.sup.N+1) of channels adjacent to said substantially constant frequency limit are eliminated by filtering; in a second stage, the signal to be processed is transposed in frequency so that in the transposed signal the variable frequency limit of said band of the signal to be digitized has a substantially constant value; in a third stage, the signals of channels adjacent to the transposed signal are eliminated by filtering. The invention is applicable to the processing of digital IF video signals.

Abstract: A video signal decoder using a sample clock tied to a frequency that is an integer multiple of four times the color subcarrier (4*Fsc). By using a 4*Fsc rate on a given input wave, the decoder determines the phase shift between the sample clock and the original wave being sampled. Then, the decoder calculates the color based upon that shift. Circuitry for implementing the decoder contains two major circuit paths. The decoding process consists of two main phases and each path performs a different function during each phase. During the first phase, the first path calculates constants based upon a user's hue and saturation adjustments used for chroma demodulation. Also during the first phase, the second path examines the color burst signal and from that signal finds the black level of the incoming video signal. During the second phase, the first path decodes the color in the TV signal using the constants calculated during the first phase.

Abstract: A system for the digital decoding of composite video signals (CVBS), comprising a brightness signal (luminance component Y) and two color difference signals (chrominance components U, V). The system modulates a color subcarrier according to the quadrature amplitude modulation principle, in which a plurality (N) of sample values of the video signal are transformed by a Walsh-Hadamard transformation (WHT) from the pixel domain into the WHT domain. The color difference signals (U, V) are derived as specific WHT coefficients of the WHT matrix obtained. The WHT coefficients determining the color difference signals (U, V) are subtracted from the WHT matrix. The WHT matrix is transformed back into the pixel domain an inverse Walsh-Hadamard transformation (IWHT), and the brightness signal (Y) are derived from the IWHT result.

Abstract: The invention relates to a digital multistandard decoder for composite video signals. The multistandard decoder according to the invention can selectively process NTSC or PAL video signals and there is no need to know the corresponding signal standard beforehand.

Abstract: A video display system comprises a video display for simultaneously displaying pictures representative of first and second video signals, having first and second synchronizing signals respectively. A switch selectably couples the video display with one of the first and second synchronizing signals. A horizontal synchronizing component of the first synchronizing signal is detected by a sensing circuit, the switch being responsive to the sensing circuit. The video display is synchronized with the first synchronizing signal when the horizontal synchronizing component of the first video signal is sensed and is otherwise synchronized with the second synchronizing signal.

Abstract: A device for digital demodulation of the video and audio elements of a television signal has a digital preprocessing stage for conditioning a complex digital signal for digital demodulation of a television signal at intermediate frequency, mixing devices for video and audio elements of the complex digital signal shifting the video sub-carrier and the audio sub-carrier, which is offset by the video sub-carrier frequency, to the frequency 0, digital audio-FM demodulators and parallel paths of mixing devices for the demodulation of the audio signals, so that fully digital signal processing of television signals from the intermediate frequency, with limited filter complexity can be performed.

Abstract: A synchronous detector for demodulating and decoding a digital data signal modulated either according to a vestigial sideband or a quadrature amplitude modulation scheme is based upon the principle of recognizing that a vestigial sideband signal may be regarded and treated as an offset-keyed QAM signal. The detector comprises a tuner for tuning to a center frequency symmetrically displaced within the transmitted digital data signal frequency spectrum and a decoder circuit selectively operating to reconstruct the transmitted digital data stream according to the duration of a transmitted data symbol. A related method of demodulating and decoding a modulated digital data stream comprises analogous steps of tuning to a center carrier frequency and selectively switching between in phase and quadrature arms of the demodulator such that the switch resides in one position or the other for a duration equal to half the duration of a transmitted data symbol.

Abstract: This invention is for a reference generator and demodulator for recovering information which has been phase, modulated on (or encoded on) a carrier. The inventive concepts described herein include a novel reference measurement circuit including a sampler and phase measurement circuit to measure the carrier reference's phase and/or frequency relative to a discrete time sampling phase and frequency, and a demodulator reference signal generator to generate properly phased reference signals for use by the phase demodulator circuit. The invention is particularly useful for decoding chroma difference signals of PAL and NTSC television video signals. It is suited to be implemented in digital form, operating on digitized signals thereby deriving all of the benefits normally expected of digital signal processing, including precision, freedom from drift and freedom from alignment. The invention is also particularly well suited to implementation by integrated circuit.

Abstract: A PAL encoder comprises phase converter, first and second low-pass filters, a burst signal adder, a chrominance subcarrier generator, and a modulator. The phase converter converts digital first and second color-difference signals into digital U-axis and V-axis signals. The first and second low-pass filters pass low-frequency components of the digital U-axis and V-axis signals to produce band-rejected U-axis and V-axis signals, respectively. The burst signal adder adds a predetermined burst signal to the band-rejected U-axis and V-axis signals to produce burst-added U-axis and V-axis signals, respectively. The chrominance subcarrier generator outputs digital sine and cosine signals of the chrominance subcarrier. The modulator multiplies the burst-added U-axis signal by the sine signal and the burst-added V-axis signal by the cosine signal and adds the multiplied results to produce a digital chroma signal.

Abstract: Different from typical signal processing which employs a feedback control, by adopting a demodulating circuit employing AFC, which is not affected by a comb filter, the response characteristic against jitter is improved and a down converted chrominance signal can be demodulated with a good accuracy. Therefore, the noise rejection effect by a comb filter is improved, the detecting accuracy of the residual phase error is also improved, and the S/N ratio of the phase is improved by combining feedforward APC compensation with a velocity error, and this results in a much improved picture quality.