Abstract: An endoscope apparatus has a clamp circuit that clamps an image pickup signal that is obtained by picking up of an image with a CCD at timing that is specified with an optical black pulse, an image processing section that applies various kinds of signal processing to the image pickup signal that is outputted from the clamp circuit to convert the image pickup signal into a video signal, and a timing generator and a control section that change a phase of the optical black pulse in response to a kind of an endoscope or a length of an insertion portion.

Abstract: A control device controls a television. The control device includes a touch module. The control device displays a menu containing a number of soft keys on a screen. The soft keys are activated to control the television to carry out corresponding functions. All positions on the menu are associated with all positions on the touch module correspondingly. As a result, a user can select desired soft keys to carry out corresponding functions by viewing the menu on the television and touching the touch module, rather than viewing the touch module.

Abstract: An analog-to-digital converting circuit includes a reference circuit and an analog-to-digital converter (ADC). The reference circuit provides a base voltage, which has one end grounded. The ADC receives an analog input signal and a base voltage signal. The ADC includes a first DC buffer and an ADC core unit. The first DC buffer internally receives an offset voltage signal and a data voltage signal to be digitized, and outputs two converting control signals. The ADC core unit receives the two converting control signals from the first DC buffer and an ADC input range voltage signal, and outputs a digital code. All of the offset voltage signal and the data voltage signal and the ADC input range voltage signal have been added with the base voltage signal.

Abstract: A digital to analog conversion apparatus includes a plurality of gain/phase adjusters configured to receive a digital signal and to output a plurality of adjusted digital input signals, a plurality of digital to analog converters coupled to respective ones of the plurality of gain/phase adjusters and configured to receive the adjusted digital input signals and to generate respective analog signals representative of the adjusted digital input signals, a plurality of phase shift elements coupled to respective ones of the plurality of digital to analog converters and configured to shift the phases of the analog signals generated by the digital to analog converters, and a combiner coupled to the outputs of the plurality of digital to analog converters and configured to combine the respective phase-shifted analog signals to form an analog output signal.

Abstract: A display apparatus includes a signal input unit through which an image signal is input, the image signal comprising a synchronization signal and an active signal; an adjustment signal generating unit that generates an adjustment signal; a signal processing unit that receives the adjustment signal and adjusts the image signal based on the received adjustment signal; and a controller which analyzes the input signal and controls the adjustment signal generating unit to change characteristics of the adjustment signal if the adjustment signal does not lie within a blanking interval between the synchronization signal and the active signal. With this configuration, even when an image signal having a reduced blanking interval between the synchronization signal and the active signal is input, the adjustment signal can be generated within the blanking interval of the image signal, not within the active signal interval.

Abstract: An image signal input circuit includes an input terminal configured to receive an image signal, a clamp circuit configured to hold a sink chip voltage contained in the image signal to be a constant value, a level shift circuit that includes a first emitter follower having a first transistor and a first current source, and a second emitter follower having a second transistor and a second current source, a base of the second transistor being connected to an emitter of the first transistor, and that is configured to shift a level of the sink chip voltage which is held constant, and an electric current source configured to attract a base current of the first transistor.

Abstract: A signal processing circuit includes an auto gain control circuit and amplifies a signal with an amplification ratio determined based on a synchronous signal level having a positive potential with respect to a black level included in a high definition television video signal. In consequence, during the processing of the high definition television video signal, the signal processing is performed with a desired amplification ratio.

Abstract: An image signal processing apparatus includes a clamp circuit that clamps an image signal having a horizontal synchronization signal, an optical black level period representing an optical black level, and an effective signal period representing an image signal for one horizontal line so as to clamp a value offset from the image signal on the basis of a first reference value during the optical black level period and to clamp the image signal on the basis of a second reference value different from the first reference value during the effective signal period, and a level computation circuit that determines the second reference value on the basis of a signal level clamped during the optical black level period.

Abstract: A Sync On Green signal detection circuit includes a clamping circuit for clamping a voltage of a video graphics signal within a default range and then outputting a clamped input signal; a first PGA (programmable gain amplifier) for receiving and amplifying the clamped input signal by a first gain to generate a first gain signal; a first low-pass filter for receiving the first gain signal and then generating a first filtered signal; a second PGA for receiving and amplifying the clamped input signal by a second gain to generate a second gain signal, wherein the second gain is different from the first gain; a second low-pass filter for receiving the second gain signal and then generating a second filtered signal; a programmable voltage shifter for receiving and adjusting the first filtered signal and then outputting a level shifted signal; and a comparator for receiving the level shifted signal and the second filtered signal and then generating a comparison signal as a SOG signal.

Abstract: According to an aspect of the invention, an information processing apparatus configured to be connected to a conversion adaptor having a video input connector and a video output connector, the apparatus including: a video output port complying with the first standard for connection of the video input connector; an image processing module configured to output a first signal when the video input connector is not connected to the video output port, the image processing module being configured to output a second signal when the video input connector is connected to the video output port; and a bias module connected to the video output port and the image processing module and configured to output a third signal to the video output port, the bias module being configured to change physical layer information of the first signal or the second signal.

Abstract: The invention relates a method of extracting synchronization signals from an input video signal (Csync) comprising horizontal synchronization pulses at the start of video lines, for generating a horizontal synchronization signal (Hsync), said method comprising:—a calculation step (105) for calculating the duration (D) of the video lines in said input video signal (Csync),—a forcing step (108) for forcing said input video signal (Csync) to an output level, said output level corresponding to the level of said input video signal (Csync) after the horizontal synchronization pulses, said input signal (Csync) being forced between the end of each horizontal synchronization pulse and a moment defined by a first percentage (X1) of said line duration (D), for generating said horizontal synchronization signal (Hsync). Use: Extraction of synchronization signals.

Abstract: In one embodiment, a signal processing system is provided that includes: (a) a video input 400 operable to receive a first analog video signal and remove the DC voltage offset component from the video signal to form a DC-adjusted analog video signal; and (b) DC restore circuitry 416 operable to set an average DC voltage of a first portion of the DC-adjusted analog video signal to a ground reference voltage to yield a DC-adjusted analog video signal. The DC-restored analog video signal is then provided to an Analog-to-Digital or A/D converter 112 for conversion into a digital video signal.

Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

Abstract: A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.

Abstract: A signal processing device of the present invention includes: an input unit which inputs an analog video signal; an A/D converter which converts the analog video signal to a digital video signal; a detecting unit which detects a level in a predetermined period of the digital video signal output from the A/D converter; a difference output unit which detects a difference between the level detected by the detecting unit and a desired value; a modulating unit which performs sigma-delta modulation on an output from the difference output unit; and a clamping unit which performs a clamping process on the analog video signal input by the input unit based on an output from the modulating unit and which outputs the clamped analog video signal to the A/D converter.

Abstract: A filter performs a filtering process by sampling a digital video signal only for an OB period. A first subtracter subtracts an OB data target value from the output value of the filter. A second subtracter sets a subtraction amount based on the subtracted result of the first subtracter and subtracts the subtraction amount from the digital video signal. A digital analog converter converts the subtracted result of the first subtracter to an analog signal and outputs it to an analog clamper. The analog clamper performs a subtracting process to an analog video signal based on the output value of the digital analog converter.

Abstract: The present invention provides an on-screen display apparatus which can eliminate variations in the DC level at a time when an input chroma signal and an OSD chroma signal are switched, and prevent an erroneous display of color. The on-screen display apparatus of the present invention comprises a voltage holder which holds a voltage value at a time when the input chroma signal is a null signal, and an output switch which outputs the voltage value held by the voltage holder in an OSD period and outputs the input chroma signal other than the OSD period.

Abstract: The invention teaches a method, means and apparatus for clamping a back porch interval of a video signal including clamping a sync-tip level of said video signal to a variable reference voltage, comparing a back-porch voltage level of the sync-tip clamped video signal to a predetermined reference voltage, generating an error signal representative of the difference between the back-porch voltage level and the predetermined reference voltage, and adjusting the variable reference voltage in response to the error signal such that the error signal is minimized.

Abstract: The keyed clamp circuit of this invention has the clamp circuit for clamping the video signal including the equalizing pulse and the vertical synchronization signal based on the clamp pulse, the synchronization signal separation circuit for separating the synchronization signal from the video signal clamped by the clamp circuit, and the clamp pulse generation circuit for generating the clamp pulse based on the synchronization signal from the synchronization signal separation circuit. The clamp pulse for the equaling pulse with a pulse width, which is shorter during the equalizing pulse period compared to the pulse width during the vertical synchronization signal period, is generated. The clamp pulse can be generated based on the equalizing pulse and the vertical synchronization signal, performing the keyed clamping on the video signal even during the blanking pulse period.

Abstract: A video signal processing system capable of adjusting errors and related methods are introduced. The video signal processing system and related calibration methods utilize the characteristic of periodic breaks of video signals to perform various kinds of calibrations including gain calibration of ADC, offset calibration of ADC, dc-level shifting of input signals, and quatization errors spreading by adding analog random signals to input video signals. The required high accuracy in video signal processing systems is achieved in the present invention with the claimed calibration methods.

Abstract: A modulation factor is kept immune from the influence of temperature variation. A modulator is provided with an operational amplifier to one of whose input ends are inputted video signals and to the other is applied a reference voltage and a video mixer into which are entered carrier wave signals and video signals amplified by the operational amplifier, wherein the reference voltage is raised or lowered as the gain of the video mixer increases or decreases, respectively, with a variation in temperature.

Abstract: A color video display signal processor comprises a source of a color difference signal and an analog to digital converter for converting the color difference signal to a digital signal. A potential divider is coupled to reference voltages of the analog to digital converter for generating a clamp voltage. A clamp arrangement is coupled to the color difference signal and to the analog to digital converter and receives the clamp reference voltage. In response to a clamp pulse the clamp arrangement couples said clamp voltage to said color difference signal.

Abstract: Disclosed are methods and systems for automatic level control (ALC) in a video signal processing system. The new ALC of the invention takes into account the gain applied to the video signal, such as that provided by an associated automatic gain control (AGC). Methods and systems of the invention use present gain control values and previous gain control values in quickly converging to a new offset control value.

Abstract: A method and apparatus within a television receiver for electronically aligning signals within the receiver by controlling support circuitry for an IF module. A video amplifier is coupled to an output of the IF module. A control voltage source (DAC 114) controls a DC level control circuit within the video amplifier (244) such that the video signal is amplified and DC level shifted to align the video signal with down stream circuitry.

Abstract: The invention teaches a method, means and apparatus for clamping a back porch interval of a video signal including clamping a sync-tip level of said video signal to a variable reference voltage (33), comparing a back-porch voltage level of the sync-tip clamped video signal to a predetermined reference voltage (22), generating an error signal (24) representative of the difference between the back-porch voltage level and the predetermined reference voltage (22), and adjusting the variable reference voltage (33) in response to the error signal (24) such that the error signal (24) is minimized.

Abstract: A method for estimating a level of a predetermined portion of a video signal comprising the steps of determining a location of the predetermined portion of the video signal, sampling the video signal during the predetermined portion and estimating the level as an average of the samples of the video signal during the predetermined portion.

Abstract: A method and/or apparatus is capable of performing high accuracy digital level restoration with a high degree of noise immunity provided by a passive clamping stage.

Abstract: A device to automatically adjust video signals to a blanking level to realize a precise intended color by being fed back with video signals at the blanking level stored in an ASIC (application-specific integrated circuit), which stores video signals at a blanking level received in a flat display panel, and by generating clamp signals so as to realize a blanking level precisely, and a method therefor.

Abstract: An AKB interface apparatus in a display system (10), includes a video signal processing IC (12) having outputs coupled via respective kinescope driver ICs (18,20,22) to respective kinescope cathodes (K1,K2,K3) for display of a color image, the signal processing IC having an input 27 for receiving an AKB input signal, the driver ICs having respective outputs (28,30,32) providing respective cathode current indicating signals (RP,GP,BP) An interface circuit (100) couples the cathode current indicating signals to the AKB input of the signal processing IC. The interface circuit comprises a load circuit (110) for generating a load voltage (Vo) in response to at least one of the cathode current indicating signals. A leakage correction circuit (130), responsive to said load voltage (Vo), feeds back a leakage correction current (Io) to the load circuit.

Abstract: A clamping circuit with a low-pass filter inserted in a feedback loop from an output terminal of a comparator to variable current sources for obtaining a feedback signal having only a DC component or having only a substantial portion of a DC component obtained by removing an AC component due to a burst signal from the output signal of the comparator.

Abstract: A symmetrical clamp clamps the input video signal to a reference voltage during composite sync pulses, so the coupling capacitor discharge current is kept small between composite sync pulses. For startup, the non-symmetrical clamp employs an operational amplifier, diode and controllable current source to charge the coupling capacitor to a minimum desired level, and to discharge the capacitor e.g. when there is a change in DC level so that the output level is too high. A sync slicing detector is also provided, using two comparators. One comparator compares the slicing level with the clamped video and produces a properly sliced composite sync output, while the other compares the clamped video with a small reference voltage and produces a fixed sync output. If the clamped video level drops suddenly, a delayed version of the fixed composite sync output clocks a flip flop, creating a fault signal which discharges a memory capacitor over a time period.

Abstract: A backporch soft-clamp circuit using a servo loop clamps the blank or DC level of a composite video signal to a known value without altering the other components of the signal. The values of the components of the composite video signal are determined by determining their amplitude with respect to the blank level. The backporch soft-clamp circuit sets the blank level to a known value for determining the true value of the components. An output composite video signal is generated which represents the input composite video signal with the blank or pedestal level set to a known DC level. Preferably, the DC level is set to two volts. A burst gate pulse representing the presence of a burst signal within the composite video signal is received by the circuit. During the burst period, the circuit soft clamps the blank level of the output signal to the appropriate level without altering the content of the burst signal. The DC level of the output signal is compared to the appropriate level by a comparator circuit.

Abstract: The present invention provides a clamp circuit for clamping a video signal which includes a sync tip clamp circuit, a pedestal clamp circuit, and a direct current electrical potential correcting circuit. The sync tip clamp circuit clamps a sync tip of the horizontal synchronization signal of the composite video signal at a first reference electrical potential when a clamp pulse is not received in a pulse input terminal, and outputs the composite video signal to an output terminal. The pedestal clamp circuit clamps the pedestal DC electrical potential of the composite video signal received to the video signal input terminal to the second reference electric potential when the clamp pulse is received at the pulse input terminal, and outputs the composite video signal to the output terminal.

Abstract: A clamp pulse generating circuit comprising a synchronizing decision circuit for deciding whether an external synchronizing pulse is being input or not; an exclusive-OR circuit, a change-over switch and a pulse width detecting circuit for deciding whether a video signal containing a synchronizing pulse is being input or not; and a pulse generating circuit for generating a clamp pulse at the front or rear edge of the external synchronizing pulse output from a synchronizing separator circuit, and outputting the clamp pulse at the front edge selected by a selection switch when the external synchronizing pulse is being input and forcing to select and output the clamp pulse at the rear edge of the synchronizing pulse irrespective of the presence of the external synchronizing pulse when the video signal containing the synchronizing pulse is being input.

Abstract: A luminance signal generation circuit with single clamp and horizontal synchronization pulse generation circuit generates a separate luminance video signal Y, representing RGB input signals, and having a horizontal synchronization pulse. During a burst period, the single clamping circuit compares the separate luminance signal Y to a reference signal. A difference signal, representing the difference between the separate luminance signal Y and the reference signal, is used to adjust a blanking level of the RGB input signals until the blanking level of the separate luminance signal Y is equal to the reference signal. During the non-burst periods, the single clamping circuit is disabled and a Y-matrix circuit combines the RGB input signals into the separate luminance signal Y. A horizontal synchronization pulse generation circuit generates a horizontal synchronization pulse to be added to the clamped separate luminance signal Y.

Abstract: An apparatus having a selectable first mode of operation for clamping an input signal to a first reference level and a selectable second mode of operation for clamping a signal derived from the input signal to a second reference level.

Abstract: A signal voltage level dual clamping circuit is disclosed for use in a receiving circuit for extraction of timing information from a signal. A first, start-up voltage level clamp is provided, the operation of which is independent of the signal timing information. A second, gated voltage level clamp is provided, the operation of which is dependent on the signal timing information. A switching circuit operates to switch the first clamp out of operation and switch the second clamp into operation once sufficient timing information has been extracted from the signal to permit operation of the second clamp.

Abstract: An image-signal clamping circuit processes image signals obtained from a solid state image sensor provided at a distal end of an electronic endoscope which do not have a direct-current component to restore a direct-current component thereof. The clamping circuit is arranged such that the restoration of a direct-current component of an image signal can be properly and stably carried out. The clamping circuit includes a sample-and-hold circuit to temporarily store an image signal, an analog-to-digital converter to output digital image signals, a device for digitally correcting the digital image data, and a digital-to-analog converter to output corrected analog image signals. The pedestal level of the corrected output analog image signal approximates a reference pedestal level.

Abstract: A cathode current detecting method wherein both a highlight detection pulse used to detect a white component and a cutoff detection pulse used to detect a black component are input to a signal input unit, and a cathode current flowing through a cathode is detected which corresponds to one of the highlight detection pulse and the cutoff detection pulse, includes the steps of: outputting a leak current detection pulse having the same magnitude as that of the cutoff detection pulse at a preselected timing; prohibiting an electron beam emitted from the cathode from flowing through an anode at the preselected timing; and detecting the leak current flowing through the cathode in response to the leak current detection pulse at the preselected timing to clamp a voltage corresponding to the leak current to a predetermined reference potential.

Abstract: The apparatus for displaying a clamp point on a screen includes an input amplifier; a clamp circuit which includes a sync separation circuit and a one shot; and a blanking circuit. The video signal is applied to the clamp circuit via the input amplifier and the output signal therefrom is applied to the blanking circuit to be modulated with respect to its brightness. Thus, the brightness-modulated clamp point is readily located on a screen of, for example, an oscilloscope.

Abstract: An image processing apparatus includes an analog image signal clamp and an A/D converter that converts the analog image signal into an m bit digital signal. The clamp is controlled in accordance with an n+1 (m>n) bit digital image signal converted by the A/D converter and an n bit digital image signal portion of the m bit digital image signal is processed.

Abstract: The present invention relates to a satellite television broadcasting receiver which receives waves from a satellite, selects a broadcasting channel and obtains an FM demodulated video signal by passing a selected signal through the band-pass filter. In this satellite television broadcasting receiver, the video signal superposed with a large energy dispersion signal is inputted to the first clamping circuit at a low level, to eliminate the energy dispersion signal. Thus, a room is provided in the dynamic range of the amplifier at the later stage and the DG and DP of the amplifier at the later stage are maintained at a satisfactory level by the second clamping circuit.

Abstract: A device for adjusting a video signal so that its black level is in coincidence with a predetermined reference level includes a capacitor having a first terminal that receives the video signal and a second terminal that provides the adjusted video signal, and means for discharging the capacitor at a constant current when the adjusted video signal exceeds the reference level, and for charging the capacitor at a constant current when the adjusted video signal is below the reference level, the ratio between the charging and discharging currents ranging from 4.3 to 12.6. The device further includes means for significantly reducing the current ratio at least during a portion of a frame synchronization pulse train.

Abstract: A first clamp circuit clamps a tip of a synchronization signal of input video signal in accordance with a synchronization signal generated from a synchronization signal generator and outputs a clamped video signal. A level detector detects a level of a tip of a synchronization signal of the clamped video signal. A converter converts the detected level to a reference level signal so that the greater the detected level becomes, the smaller the reference level signal becomes. A second clamp circuit clamps the tip of the synchronization signal of the clamped video signal to the reference level signal and outputs an output video signal. Thus, the second clamp circuit compensates a remaining sag component included in the input video signal accurately.

Abstract: An adaptive clamping circuit for a video signal processing device includes a control signal generator for generating a control signal capable of controlling a speed of clamping operation in an input signal provided to the video signal processing device, a variable response signal generator for generating a variable response gain signal which enables the input signal to be adaptively clamped by selecting a time constant which is derived from a most significant bit (MSB) and which is adaptively changed in response to the control signal from the control signal generator, and a clamping circuit producing a direct current signal from output of the variable response signal generator and for applying the direct current signal to the input signal.

Abstract: Image processing apparatus wherein the level of an input analog picture signal from an imaging device is controlled by gain control circuitry, and the gain-controlled analog signal is then converted into a digital signal. Feedback clamping is performed by generating an error signal by subtracting a target value from the digital signal, and then adding the error signal to the gain-controlled analog signal. Correct clamping is made possible by allowing the target value to be varied based upon the gain set by the gain control means.

Abstract: Automatically fine tuned pictures and sounds can be obtained from a novel color television system having a video/audio signal adjusting circuit, a remote controller operable for generating a program mode selection signal, a memory having a plurality of memory locations for storing operating parameter data for the video and the audio processing circuit corresponding to program modes, a microprocessor responsive to the program mode selection signal for receiving the operating parameter data corresponding thereto and for generating an audio control signal and a video control signal, a video signal adjusting circuit responsive to the video control signal for adjusting the video signal to have a video characteristic corresponding to the program mode selection signal, and an audio signal adjusting circuit responsive to the audio control signal for adjusting the audio signal to have a frequency band characteristic corresponding to the program mode selection signal.

Abstract: An image signal recording and reproducing system for recording an image signal on a recording medium and for reproducing the image signal recorded on the recording medium is arranged to perform a reproducing action on the recording medium on which a sampled image signal formed by sampling the image signal is recorded to sample a reproduced signal reproduced from the recording medium and, in outputting a sampled reproduced signal, the level of the reproduced signal to be sampled is controlled according to the sampling phase of the reproduced signal. This arrangement enables the system to record the image signal on the recording medium and to reproduce the image signal without deteriorating the image signal.

Abstract: A clamping circuit clamps an input signal applied at an input pin of an integrated circuit package by charging and discharging a series capacitor into the input pin with first and second controlled current sources. The voltage developed at the input pin is compared against a reference signal in either the analog or digital domain to generate control signals to control the first and second current sources. The controlled current sources maintain the proper voltage across the series capacitor to clamp the voltage at the input pin. In the digital embodiment, an analog-to-digital converter and digital filter provide a filtered digital signal to compare against a digital reference to generate the control signals.

Abstract: A digital clamp circuit obtains a variation value of the black level varying per 1H period according to a predetermined clamp reference value, adds the variable value to an entire signal level to perform compensation of the variation of the black level, thereby enabling stable signal processing.