Abstract: A display-driving apparatus for driving a display panel having at least two display areas is provided. The apparatus includes a storage device configured to receive and store a group of source data signals corresponding to a frame of image. The apparatus further includes a demultiplexer configured to split the group of source data signals into at least two sub-groups of data signals. Additionally, the apparatus includes a converter configured to convert a signal format of a respective one of the at least two sub-groups of data signals to a displayable format corresponding to the display panel. Furthermore, the apparatus includes a controller configured to transfer the at least two sub-groups of data signals in the displayable format to respective at least two display areas of the display panel to display a frame of image.

Abstract: Circuits and methods are described herein for suppressing interference in binary offset carrier (BOC) modulated signals The BOC signal includes an upper sideband (USB) and a lower sideband (LSB). The LSB or the USB of the BOC signal is rotated from a first frequency to a second frequency. Interference in the rotated LSB or USB is reduced. An output BOC signal with reduced interference is generated based on the rotated LSB or USB from which interference has been reduced.

Abstract: Surge protective devices having surge protective and overvoltage protection capability are provided. In one example embodiment, the surge protective device can include a surge protection circuit. The surge protection device can include an overvoltage protection circuit coupled in series with the surge protection circuit. The overvoltage protection circuit can include a voltage sensing circuit associated with a voltage threshold, one or more switching elements, and/or a gating circuit coupled to the voltage sensing circuit. The gating circuit can be configured to control the one or more switching elements to be in a non-conducting state when the voltage sensing circuit detects a voltage that exceeds the voltage threshold.

Abstract: A detection device includes: a drive circuit that receives a feedback signal from a vibrator and drives the vibrator; a detection circuit that performs detection based on a signal from the vibrator and outputs detection data; and a digital signal processing unit that performs digital filtering for the detection data from the detection circuit. The digital signal processing unit performs band elimination filtering for attenuating a component of a detuning frequency ?f=|fd?fs| corresponding to a difference between a drive side resonance frequency fd and a detection side resonance frequency fs of the vibrator for the detection data.

Abstract: Areas of a video signal that represent light emission are detected, the luminance levels at which said light emission areas are displayed are enhanced, emphasizing the areas, and the luminance stretching is controlled in accordance with the brightness of the surrounding environment, thereby increasing the resulting sense of brightness and improving the appearance of the video. A light emission detector counts pixels to generate a histogram of a prescribed feature quantity and identifies areas that fall within a prescribed range at the upper end of said histogram as being light emission areas. An area-active-control/luminance-stretching portion performs luminance stretching, increasing the luminance of a backlight portion and reducing the luminance of non-light emission areas of the video signal.

Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.

Abstract: Disclosed is a video signal output circuit including: a clamp circuit; a first differential amplifying circuit; a dividing circuit; and an offset circuit which adds or subtracts a predetermined offset voltage to or from a bias voltage, a reference voltage, or a base reference voltage generated by the dividing circuit so as to supply an offset voltage added/subtracted voltage to the clamp circuit or the first differential amplifying circuit, wherein the offset circuit includes a pnp bipolar transistor and an npn bipolar transistor, and outputs a difference voltage corresponding to a difference between a base-emitter voltage of the pnp bipolar transistor and a base-emitter voltage of the npn bipolar transistor.

Abstract: A display apparatus includes a signal input unit through which an image signal is input, the image signal comprising a synchronization signal and an active signal; an adjustment signal generating unit that generates an adjustment signal; a signal processing unit that receives the adjustment signal and adjusts the image signal based on the received adjustment signal; and a controller which analyzes the input signal and controls the adjustment signal generating unit to change characteristics of the adjustment signal if the adjustment signal does not lie within a blanking interval between the synchronization signal and the active signal. With this configuration, even when an image signal having a reduced blanking interval between the synchronization signal and the active signal is input, the adjustment signal can be generated within the blanking interval of the image signal, not within the active signal interval.

Abstract: A feedback circuit for restoration of DC in electrical signals is presented. A sample pulse representing a DC portion of an electrical signal is generated. The sample pulse triggers a sample and hold circuit to acquire the correct offset voltage in the electrical signal during this DC portion. The offset voltage feeds back through a summing node to the electrical signal thereby restoring the video signal to the desired DC voltage level with respect to ground.

Abstract: Disclosed is a video signal output circuit including: a clamp circuit; a first differential amplifying circuit; a dividing circuit; and an offset circuit which adds or subtracts a predetermined offset voltage to or from a bias voltage, a reference voltage, or a base reference voltage generated by the dividing circuit so as to supply an offset voltage added/subtracted voltage to the clamp circuit or the first differential amplifying circuit, wherein the offset circuit includes a pnp bipolar transistor and an npn bipolar transistor, and outputs a difference voltage corresponding to a difference between a base-emitter voltage of the pnp bipolar transistor and a base-emitter voltage of the npn bipolar transistor.

Abstract: An image signal input circuit includes an input terminal configured to receive an image signal, a clamp circuit configured to hold a sink chip voltage contained in the image signal to be a constant value, a level shift circuit that includes a first emitter follower having a first transistor and a first current source, and a second emitter follower having a second transistor and a second current source, a base of the second transistor being connected to an emitter of the first transistor, and that is configured to shift a level of the sink chip voltage which is held constant, and an electric current source configured to attract a base current of the first transistor.

Abstract: The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.

Abstract: A cable length detection apparatus is provided to detect the length of a cable having at least three pairs of wires for transmitting video signals. The cable length detection apparatus has a signal compressing circuit, a signal converting circuit and a length calculating circuit. The signal compressing circuit compresses an electrical signal into one pair of wires. The signal converting circuit converts the electrical signal transmitted by the pair of wires into a value. The length calculating circuit then calculates the length of the cable according to the value.

Abstract: An image signal processing apparatus includes a clamp circuit that clamps an image signal having a horizontal synchronization signal, an optical black level period representing an optical black level, and an effective signal period representing an image signal for one horizontal line so as to clamp a value offset from the image signal on the basis of a first reference value during the optical black level period and to clamp the image signal on the basis of a second reference value different from the first reference value during the effective signal period, and a level computation circuit that determines the second reference value on the basis of a signal level clamped during the optical black level period.

Abstract: A video signal output circuit includes a sync-tip clamp circuit fixing a sync-tip level of an input video signal at a constant voltage, a low-pass filter receiving the video signal output from the sync-tip clamp circuit and eliminating a predetermined high-frequency component, a dummy circuit receiving the video signal output from the sync-tip clamp circuit and outputting the video signal having substantially the same sync-tip level as that of the video signal output from the low-pass filter, and an output driver receiving the video signal output from the low-pass filter and outputting the video signal with a low output impedance. The sync-tip clamp circuit controls the sync-tip level of the video signal output from the dummy circuit such that the sync-tip level of the video signal is equal to a predetermined reference voltage.

Abstract: A feedback circuit for restoration of DC in video signals is presented. A sample pulse representing the back porch of an incoming video signal is generated from the horizontal sync signal. The sample pulse triggers a sample and hold circuit to acquire the correct offset voltage in the output signal during this back porch period. The offset voltage feeds back through a summing node upstream of either the circuit causing the offset or an input amplifier thereby restoring the video signal to the desired DC voltage level with respect to ground.

Abstract: According to an aspect of the invention, an information processing apparatus configured to be connected to a conversion adaptor having a video input connector and a video output connector, the apparatus including: a video output port complying with the first standard for connection of the video input connector; an image processing module configured to output a first signal when the video input connector is not connected to the video output port, the image processing module being configured to output a second signal when the video input connector is connected to the video output port; and a bias module connected to the video output port and the image processing module and configured to output a third signal to the video output port, the bias module being configured to change physical layer information of the first signal or the second signal.

Abstract: A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted noise at or near 0 Hz. The DC compensation is performed using direct coupling, as opposed to AC coupling, so that no useful signal information in the active period of the input signal is lost at DC. The DC compensation circuit samples the input signal during an inactive period of the input signal. Afterwhich, the unwanted DC noise is determined from the sampled signal and stored until an active period of the input signal. For example, the sampled signal can be filtered using a passband around DC so as to isolate the signal energy at DC during the inactive period. Since there is no useful signal information present during the inactive period, any signal energy at the output of the filter is necessarily unwanted DC noise.

Abstract: In a video signal processor (10), a video signal is given to a video input terminal (101) via a coupling capacitor (200). A clamp circuit (104) clamps the video signal input via the video input terminal (101). A format detector section (105) detects a format of the video signal. A controller section (107) changes power supply capability of the clamp circuit (104) according to a detection result of the format detector section (105).

Abstract: In one embodiment, a signal processing system is provided that includes: (a) a video input 400 operable to receive a first analog video signal and remove the DC voltage offset component from the video signal to form a DC-adjusted analog video signal; and (b) DC restore circuitry 416 operable to set an average DC voltage of a first portion of the DC-adjusted analog video signal to a ground reference voltage to yield a DC-adjusted analog video signal. The DC-restored analog video signal is then provided to an Analog-to-Digital or A/D converter 112 for conversion into a digital video signal.

Abstract: A cable length detection apparatus is provided to detect the length of a cable having at least three pairs of wires for transmitting video signals. The cable length detection apparatus has a signal compressing circuit, a signal converting circuit and a length calculating circuit. The signal compressing circuit compresses an electrical signal into one pair of wires. The signal converting circuit converts the electrical signal transmitted by the pair of wires into a value. The length calculating circuit then calculates the length of the cable according to the value.

Abstract: A video signal-processing device that can improve the apparent contrast of the luminance signal at a television receiving set includes a quantity of black expansion computing section for computationally determining the quantity of black expansion when the luminance component of the input video signal is not higher than a first luminance level, a gain controller for regulating the quantity of black expansion as computationally determined by the quantity of black expansion computing section, a quantity of black expansion adding section for generating an output video signal by adding the quantity of black expansion regulated by the gain controller to the luminance component of the input video signal, and a vertical span adding block for integrating the luminance component of the output video signal not higher than a second luminance level for a field.

Abstract: A data slicer of the present invention comprises a reference voltage generation circuit and a comparator. The reference voltage generation circuit comprises a plurality of capacitances which area connected in parallel to one another, holding electrical charges on the basis of an input signal, a plurality of first switches which are connected to the plurality of capacitances with first nodes, respectively, for controlling the inflow of the input signal to the plurality of capacitances and a plurality of second switches which are connected to the plurality of capacitances with the first nodes, respectively, for controlling the connection among the plurality of capacitances. The plurality of first switches are controlled with predetermined timing where these first switches are individually brought into an ON state, and the plurality of second switches are controlled with predetermined timing where all the second switches are brought into an ON state.

Abstract: A system in which drooping of the video levels due to leakage currents and proper DC bias level is addressed by providing a charge into the video signal to offset the leakage currents and to provide DC bias. To determine the leakage current level, measurements are made measuring the voltages of the syncs and the blanking intervals. To determine the DC bias, a measurement is made of the sync. Over a series of video lines these measurements are averaged. If the average is below the desired level, a charge is provided via a current source to the incoming signal. By having the current source provide charge during each video line, droop is reduced and the proper DC bias is provided.

Abstract: A low bandwidth signal path is added to copy internal node DC signal to output node. Therefore, for a DC or low frequency signal, the output signal is controlled by this loop. On the other hand, a high frequency signal is not affected because of the low-bandwidth of added loop. Thus, both DC and AC coupling modes are realized for components such as low-voltage video drivers.

Abstract: The present invention discloses a method and a device for dynamically adjusting a sync-on-green (SOG) signal of a video signal, capable of extracting an SOG signal from an analog video signal so as to dynamically adjust the SOG signal in real-time so as to overcome the problems due to voltage shift or noise.

Abstract: A device for detecting synchronization pulses in a video signal is disclosed. The device includes a transistor. The base-emitter voltage of the transistor is maintained below a threshold level in response to receiving active video information. The base-emitter voltage is increased above the threshold level in response to receiving synchronization information, whereby the transistor is turned on to generate an asserted synchronization signal. Accordingly, in response to active video information being received and the transistor being off, the magnitude of the synchronization signal is set to a first level and in response to synchronization information being received, and the transistor being on, the magnitude is set to a second level. The synchronization signal generated by the transistor is processed to provide both horizontal and vertical synchronization signals.

Abstract: An imaging apparatus includes a solid-state imaging device that outputs a captured image signal in current mode, which in turn is subjected to CDS processing in current mode by a current signal detector, thus suppressing FPN noise. A captured image signal output by the current signal detector is amplified by a programmable gain amplifier to a certain level, and the amplified signal is converted by a current-to-voltage transducer into a voltage signal. In a clamp circuit including a current-output differential amplifier and a current adder, the differential amplifier compares the voltage signal with a reference voltage from a reference voltage source and feeds back a clamp current to the current adder so that the difference between the voltage signal and the reference voltage becomes substantially zero. The current adder is required to simply add a signal current and the clamp current.

Abstract: A video decoder in which 1) resolution quality can be improved for a given bit count analog-to-digital converter, 2) a lower bit count analog-to-digital converter can be used with substantially similar quality or 3) a combination of improved resolution quality with a lower bit count analog-to-digital converter can be done. In the preferred embodiment, a DC bias is added to the video signal after the sync portion of the composite signal has been received and prior to the active video being received. This bias is then removed after the end of the active video period. By applying this bias, the DC voltage level of the video signals is actually reduced, so that the full scale value of the analog-to-digital conversion process can also be reduced. Thus, compared to using an unbiased signal, increased A/D converter resolution is obtained. In an alternative embodiment, the sync portion can be biased upwardly during the front porch and then be returned during the back porch.

Abstract: A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted noise at or near 0 Hz. The DC compensation is performed using direct coupling, as opposed to AC coupling, so that no useful signal information in the active period of the input signal is lost at DC. The DC compensation circuit samples the input signal during an inactive period of the input signal. Afterwhich, the unwanted DC noise is determined from the sampled signal and stored until an active period of the input signal. For example, the sampled signal can be filtered using a passband around DC so as to isolate the signal energy at DC during the inactive period. Since there is no useful signal information present during the inactive period, any signal energy at the output of the filter is necessarily unwanted DC noise.

Abstract: Disclosed are methods and systems for automatic level control (ALC) in a video signal processing system. The new ALC of the invention takes into account the gain applied to the video signal, such as that provided by an associated automatic gain control (AGC). Methods and systems of the invention use present gain control values and previous gain control values in quickly converging to a new offset control value.

Abstract: The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.

Abstract: The object of the invention is offering an external output video signal processor, which does not need coupling capacitor or clamping circuit. A system controller outputs a video signal by which the sync. tip level and the pedestal level were fixed to a predetermined value. It was considered as an external output video signal processor which carries out direct input of the video signal output to the video signal processing circuit from the system controller, and is characterized by providing a level shift circuit which adjusts the level and is sent to said latter part processing circuit.

Abstract: Digital dc restore methods and apparatus to restore the DC component of an analog waveform to a quantized reference value level at a given temporal point on a waveform, prior to an ADC. This may used to establish the relationship between the full scale digital value out of the ADC and the waveform being digitized. For a video signal, the Digital Value of Black, is compared with the value on the back porch of the video signal. The difference is converted to the analog domain by a DAC clocked at the Temporal Point to provide a sample and hold function. An amplifier compares the difference, mapped to one half full scale digital, to an analog common mode voltage for the ADC, removing any error due to the difference between them. Other applications include correlated double sampling of contact image sensors to remove Dark Current Offset.

Abstract: A clamping system for clamping a video signal, wherein the clamping system uses a charge-pump unit in company with a digital clamping controller to clamp the potential of the video signal, prior to the video signal being input to a programmable gain amplifier and an A/D converter, so as to reach a desired level. The charge-pump unit provides two charge-pump circuits, wherein one charge-pump circuit supplies a strong burst to boost the potential of the video signal while the video signal is below a threshold value. Otherwise, the other charge-pump circuit supplies a weak burst to fine tune the potential of the video signal when the video signal has reached the threshold value.

Abstract: The present invention provides an on-screen display apparatus which can eliminate variations in the DC level at a time when an input chroma signal and an OSD chroma signal are switched, and prevent an erroneous display of color. The on-screen display apparatus of the present invention comprises a voltage holder which holds a voltage value at a time when the input chroma signal is a null signal, and an output switch which outputs the voltage value held by the voltage holder in an OSD period and outputs the input chroma signal other than the OSD period.

Abstract: A circuit for selectively controlling signal baseline and frequency emphasis. An amplifier with selectively controllable feedback circuitry allows higher frequency components of a signal to be emphasized over lower frequency components while also allowing control over the baseline of the signal. Additionally, a multiplexed video signal interface provides a multiplexed component video signal which includes component video signals with OSD data and user-controllable contrast, video gain and signal baseline, along with the ability to individually control such signal components.

Abstract: An apparatus, system and method for clamping a video signal input to a coupling capacitor (215) for providing a clamping voltage. A charging current is applied to the capacitor (215) via an amplifier (225) having a first input (227) coupled with the capacitor output and a second input (226) coupled to a reference potential, the amplifier (225) is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (215). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Abstract: The invention relates to improvements to the operation of a broadcast data receiver (BDR) and, in particular, to the provision of a video data amplifier and driver circuit for the processing of a received video data signal. The circuit includes a means for generating at least one compensatory value and preferably a multiplication factor. The compensatory value is added to the received video data signal as it passes through the circuit to form a combined signal. The combined signal can also be multiplied. The level of the compensatory value can alter with reference to changes in the environment of the operation of the circuit so as to take into account and minimise changes affecting the operation of the circuit and on the video signal.

Abstract: The invention teaches a method, means and apparatus for clamping a back porch interval of a video signal including clamping a sync-tip level of said video signal to a variable reference voltage, comparing a back-porch voltage level of the sync-tip clamped video signal to a predetermined reference voltage, generating an error signal representative of the difference between the back-porch voltage level and the predetermined reference voltage, and adjusting the variable reference voltage in response to the error signal such that the error signal is minimized.

Abstract: An A/D converter updates its reference potential so that it coincides with an analog potential of a video signal. The A/D converter changes a variable voltage range of the reference potential during the same horizontal synchronizing period based upon a horizontal synchronizing signal. It is possible to correctly discriminate data superposed on the video signal even if an analog potential of the video signal considerably varies during the same horizontal synchronizing period.

Abstract: A method and apparatus for controlling the brightness of an image processing device to improve a brightness characteristic of an image signal, by reducing a pedestal voltage range and correspondingly expanding a brightness control voltage range in a highlight mode. The brightness control method includes the operations of determining whether a highlight mode is enabled; and if the highlight mode is enabled, reducing a pedestal voltage range by a first predetermined value and expanding a brightness control voltage range by a second predetermined value. The pedestal driving voltage and the brightness control voltage can be reciprocally controlled without modifications to a circuit having limited amplification, and the brightness can be improved without saturating an image in a highlight mode.

Abstract: A clamp control circuit outputs a clamp control signal after a delay of a predetermined time if a digital video signal is detected. A sampling circuit that extracts sampling data of a pedestal level from a luminance corrected signal based on a clamp pulse at a timing of the back porch. A data averaging circuit calculates an average of the sampling data of the pedestal level. A data holding circuit holds a difference between the average and a digital signal processing reference level when the clamp control signal is output and also when the clamp control signal is not output. A level correction circuit corrects a level of the luminance signal based on the difference held by the data holding circuit and outputs the corrected luminance signal.

Abstract: A calibration device for a video circuit input stage comprises an analog-to-digital converter and an input capacitor constantly discharged by a power source and recharged by a charging circuit by means of a first and a second charging current. The charging circuit is controlled by a central processing unit receiving an estimate of the variation between the converter's output code and a clamp value.

Abstract: Systems and methods for adjusting image contrast are provided. An exemplary method for adjusting image contrast includes determining a format of a television signal and outputting in conjunction with the television signal a reference level. If the television signal has a first format, then the reference level is caused to be substantially equal to a luminance level representing a black color in the first format. However, if the television signal has a second format, then the reference level is caused to be substantially equal to a luminance level representing a black color in the second format.

Abstract: In order to reduce a circuit scale such as a brightness adjustment circuit or the number of pins in an IC chip, in the brightness adjustment circuit, a brightness adjusted video signal (internal video signal) output from an analog signal synthesis circuit or a D/A converter is input to one input terminal of a switch and a sample/hold circuit. The sample/hold circuit holds a voltage of a level in accordance with the pedestal level of the internal video signal at a timing in accordance with a sampling pulse in synchronization with the internal video signal. A clamp circuit clamps the pedestal level of an external video signal in accordance with a clamp pulse, using the voltage held by the sample/hold circuit as the reference voltage, and input it to the other input terminal. The output terminal of the switch is connected to an amplifier.

Abstract: A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit (400) includes a clamping capacitor (404) that couples to an automatic clamping circuit portion (405) to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (Vref1) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion (405) connects to the customizable clamping circuit portion (411) to clamp any portion of the video input signal to a second predetermined reference voltage (Vref2) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer (416) connects between the customizable clamping circuit portion and the output node of the clamping circuit.

Abstract: When converting an interlace video signal into a non-interlace video signal by interpolating a scanning line of the interlace video signal, black stretching is carried out with respect to the interpolated scanning line. Thereafter, black stretching is carried out with respect to a non-interpolation scanning line of the converted non-interlace video signal.

Abstract: An object of the present invention is to provide a signal processor which improves the offset accuracy of a video signal without increasing the number of bits of a circuit. An N-bit adder (103) adds a video signal (S101) and an upper-N-bit signal of a brightness control signal (S102) as an offset value. A 1-bit pulse generator (107) generates a 1-bit pulse signal (S107) in which “1” and “0” have equal chances of appearing at random. A selector (106) selects the 1-bit pulse signal (S107) when the LSB of the brightness control signal (S102) is “1”, while selects a ground level “0” when the LSB is “0”, and supplies the selected signal to a carry input of the N-bit adder (103).

Abstract: A circuit for clamping a TV signal includes an input capacitor coupled to the TV signal, an analog-to-digital converter that outputs a digital signal corresponding to TV signal, a comparator that compares the digital signal to a black level signal, and a high impedance driver that charges the input capacitor in response to an output of the comparator.