Abstract: The disclosure extends to methods, systems, and computer program products for digitally imaging with area limited image sensors, such as within a lumen of an endoscope.

Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.

Abstract: A method and system for frame insertion in a digital display system is provided. The method is adapted for use with a liquid crystal display (LCD) type display and is effective to substantially reduce motion blur. The LCD display receives a sequence of digitized input frames at a first frequency. The method generates a sequence of output frames that include the digitized input frames interspersed with a plurality of modified frames. Each of the modified frames is substantially similar to a preceding digitized input frame, but has a reduced luminance. The modified frames may be generated by multiplying a preceding digitized input frame by a reduced luminance factor. The reduced luminance factor may be determined as a fixed value or as a function of an average pixel level of a preceding frame.

Abstract: In a semiconductor integrated circuit arranged to perform sag compensation for a video signal, an operational amplifier includes a non-inverted input terminal, an inverted input terminal, and an output terminal, in which a video signal is input to the non-inverted input terminal. A first resistor includes a first end connected to the inverted input terminal and a second end being grounded. The output terminal is connected to a first external terminal and the inverted input terminal is connected to a second external terminal. A second resistor includes a first end connected to the output terminal and a second end connected to the inverted input terminal. A first capacitor is disposed between the first external terminal and the second external terminal and connected in parallel to the second resistor, and the second resistor has a resistance value determined based on a capacitance value of the first capacitor.

Abstract: A display apparatus includes a signal input unit through which an image signal is input, the image signal comprising a synchronization signal and an active signal; an adjustment signal generating unit that generates an adjustment signal; a signal processing unit that receives the adjustment signal and adjusts the image signal based on the received adjustment signal; and a controller which analyzes the input signal and controls the adjustment signal generating unit to change characteristics of the adjustment signal if the adjustment signal does not lie within a blanking interval between the synchronization signal and the active signal. With this configuration, even when an image signal having a reduced blanking interval between the synchronization signal and the active signal is input, the adjustment signal can be generated within the blanking interval of the image signal, not within the active signal interval.

Abstract: A Sync On Green signal detection circuit includes a clamping circuit for clamping a voltage of a video graphics signal within a default range and then outputting a clamped input signal; a first PGA (programmable gain amplifier) for receiving and amplifying the clamped input signal by a first gain to generate a first gain signal; a first low-pass filter for receiving the first gain signal and then generating a first filtered signal; a second PGA for receiving and amplifying the clamped input signal by a second gain to generate a second gain signal, wherein the second gain is different from the first gain; a second low-pass filter for receiving the second gain signal and then generating a second filtered signal; a programmable voltage shifter for receiving and adjusting the first filtered signal and then outputting a level shifted signal; and a comparator for receiving the level shifted signal and the second filtered signal and then generating a comparison signal as a SOG signal.

Abstract: An image data decoding method of an image vertical blanking interval (VBI) and device thereof can adjust a run-in clock signal of data lines of teletext to a data phase of teletext data lines. The method can accurately decode data of the teletext data lines to avoid a phase bias and an erroneous decoding result. A main technical method to decode the data of the VBI is to extract the data of the teletext data lines to determine corresponding bit logical values of the image data and then to output a decode result and also output a phase adjustment value. The phase adjustment value is used to adjust a read phase value of the extracted image so as to synchronize a data phase in VBI.

Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

Abstract: A signal processing device of the present invention includes: an input unit which inputs an analog video signal; an A/D converter which converts the analog video signal to a digital video signal; a detecting unit which detects a level in a predetermined period of the digital video signal output from the A/D converter; a difference output unit which detects a difference between the level detected by the detecting unit and a desired value; a modulating unit which performs sigma-delta modulation on an output from the difference output unit; and a clamping unit which performs a clamping process on the analog video signal input by the input unit based on an output from the modulating unit and which outputs the clamped analog video signal to the A/D converter.

Abstract: The video signal processing circuit has a clamp circuit for clamping a composite video signal including a copy guard signal with amplitude of from white to black as well as a pseudo horizontal synchronization signal, a brilliant signal, and a synchronization signal. The circuit also has a synchronization signal separation circuit, which separates the synchronization signal from the composite video signal and a synchronization signal discrimination circuit, which identifies if the synchronization signal coming from the synchronization signal separation circuit has the same cycle as that of a horizontal synchronization signal, and which blocks the signal with the cycle shorter than the cycle of the horizontal synchronization signal, letting only the signal with the cycle of the horizontal synchronization signal pass.

Abstract: An imaging apparatus includes a solid-state imaging device that outputs a captured image signal in current mode, which in turn is subjected to CDS processing in current mode by a current signal detector, thus suppressing FPN noise. A captured image signal output by the current signal detector is amplified by a programmable gain amplifier to a certain level, and the amplified signal is converted by a current-to-voltage transducer into a voltage signal. In a clamp circuit including a current-output differential amplifier and a current adder, the differential amplifier compares the voltage signal with a reference voltage from a reference voltage source and feeds back a clamp current to the current adder so that the difference between the voltage signal and the reference voltage becomes substantially zero. The current adder is required to simply add a signal current and the clamp current.

Abstract: A circuit and method for clamping a composite video component signal at the video black level by using horizontal synchronization timing information contained within the signal and clamping the signal during a time interval in which it is at the desired black level.

Abstract: The invention teaches a method, means and apparatus for clamping a back porch interval of a video signal including clamping a sync-tip level of said video signal to a variable reference voltage, comparing a back-porch voltage level of the sync-tip clamped video signal to a predetermined reference voltage, generating an error signal representative of the difference between the back-porch voltage level and the predetermined reference voltage, and adjusting the variable reference voltage in response to the error signal such that the error signal is minimized.

Abstract: A control circuit for use in a video processor utilizes combined automatic kinescope bias (AKB) control, and average individual beam current sensing and limiting in at least one CRT. The control circuit includes automatic kinescope bias (AKB) control circuitry for detecting a magnitude of individual red (R), green (G) and blue (B) cathode currents driving corresponding R, G and B CRTs, generating R, G and B average cathode current control signals therefrom, and using the R, G and B average cathode current control signals as feedback to the video processor to reduce the R, G and B cathode currents approximately equal current amounts.

Abstract: An improved digital cut-off control loop for black level adjustment in a video processor for controlling RGB output signals. The improved circuit advantageously provides a higher resolution of the black level adjustment, and a short cut-off convergence time when the TV set is switched on. The improved circuit can also blank the RGB output when the cut-off control loop has not converged to the correct level.

Abstract: The circuit takes into account whether the image on a screen is too bright, whether more than one specific number of pixels have a luminance value that is greater than a given peak value and whether this condition is met in more than one specific number of lines in a picture and in more than one specific number of successive images with one such number of lines.

Abstract: A digital signal processing vestigial-sideband television modulator receives a television signal. The present invention digitizes the television signal to generate a video signal and a digital processor processes the video signal to generate a complex baseband signal. The complex baseband signal is converted into an in-phase baseband signal and a quadrature baseband signal and modulated to respectively generate a modulated in-phase baseband signal and a modulated quadrature baseband signal. The modulated in-phase baseband signal and the modulated quadrature baseband signal are combined to produce a vestigial radio frequency television signal. The undesired sideband of the vestigial radio frequency television signal is tapped, filtered, and, subsequently, the power level of the undesired sideband is detected. Any imbalance in the modulation process is compensated by using the detected power level of the undesired sideband.

Abstract: A method and/or apparatus is capable of performing high accuracy digital level restoration with a high degree of noise immunity provided by a passive clamping stage.

Abstract: A method and device are provided for correcting an amplitude of a synchronizing signal. A pedestal voltage, Vped, (i.e., a reference level) may be detected which repetitively occurs at the same period as a synchronizing signal of an input composite video signal. A reference voltage, Vsync, may be generated corresponding to an amplitude of the synchronizing signal which meets a standard for the input composite video signal. A DC voltage, Vh, may be generated having a voltage level corresponding to a tip or peak level of the synchronizing signal which meets the standard for the input composite video signal based on the pedestal voltage, Vped, and the reference voltage, Vsync. The DC voltage Vh and the composite video signal may be switchably output in synchronism with the synchronizing signal extracted from the composite video signal.

Abstract: A device to automatically adjust video signals to a blanking level to realize a precise intended color by being fed back with video signals at the blanking level stored in an ASIC (application-specific integrated circuit), which stores video signals at a blanking level received in a flat display panel, and by generating clamp signals so as to realize a blanking level precisely, and a method therefor.

Abstract: A clamping circuit with a low-pass filter inserted in a feedback loop from an output terminal of a comparator to variable current sources for obtaining a feedback signal having only a DC component or having only a substantial portion of a DC component obtained by removing an AC component due to a burst signal from the output signal of the comparator.

Abstract: A luminance signal generation circuit with single clamp generates a separate luminance signal Y by combining RGB input signals in a weighted manner within a Y-Matrix circuit. During a burst period the single clamping circuit is enabled. When enabled, the single clamping circuit compares the separate luminance signal Y to a constant reference voltage signal. A difference signal, representing the difference between the separate luminance signal Y and the constant reference voltage signal, is used to adjust a blanking level of the RGB input signals until the blanking level of the separate luminance signal Y is equal to the constant reference voltage signal. During the non-burst periods the single clamping circuit is disabled and the Y-Matrix circuit combines the RGB input signals into the separate luminance signal Y. Preferably, the single clamping circuit sets the blank level of the separate luminance signal Y to a level equal to two volts.

Abstract: A clamping circuit for use in a video camera varies a level of an image signal utilizing an analog feedback control signal, converts the varied image signal to a digital image signal, generates a digital zone value signal that corresponds to a level of a reference zone of the digital image signal, digitally detects an amount of error between the digital zone value signal and a predetermined zone value having a non-zero fractional portion, generates from the detected amount of error a digital error signal that has a predetermined number of data bits, switches between a coarse adjustment mode and a fine adjustment mode of the clamping circuit in accordance with a level of the digital error signal, generates, in the coarse adjustment mode, a pulse width modulated signal from the most significant bits of the digital error signal, generates, in the fine adjustment mode, the pulse width modulated signal from the least significant bits of the digital error signal, and generates from the generated pulse width modulat

Abstract: A backporch soft-clamp circuit using a servo loop clamps the blank or DC level of a composite video signal to a known value without altering the other components of the signal. The values of the components of the composite video signal are determined by determining their amplitude with respect to the blank level. The backporch soft-clamp circuit sets the blank level to a known value for determining the true value of the components. An output composite video signal is generated which represents the input composite video signal with the blank or pedestal level set to a known DC level. Preferably, the DC level is set to two volts. A burst gate pulse representing the presence of a burst signal within the composite video signal is received by the circuit. During the burst period, the circuit soft clamps the blank level of the output signal to the appropriate level without altering the content of the burst signal. The DC level of the output signal is compared to the appropriate level by a comparator circuit.

Abstract: Video signals to be displayed are applied via a video driver amplifier to the cathode electrode of a kinescope. A beam current sensor, also coupled to the cathode electrode, provides a beam current indicating signal. An AKB regulator, responsive to the beam current indicating signal, supplies a black level correction signal to the driver amplifier for regulating the black level of images displayed by the kinescope. A screen grid supply system is provided for controlling the G-2 (screen grid) voltage of the kinescope as a predetermined function of the black level correction signal thereby forming with the AKB regulator a dual feedback loop for providing black level regulation by both the driver amplifier and the screen grid thereby maximizing or extending the overall black level control range.

Abstract: The present invention relates to an apparatus for simultaneously estimating a set of frame-to-frame motions between two frames and a set of field-to-field motions between two fields.

Abstract: A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both sample and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus.

Abstract: The present invention relates to a circuit for locking an analog signal to a reference value, including an analog-to-digital converter receiving the analog signal modified by the charge stored in a capacitor. A digital comparator receives the output of the converter and a reference digital value, and controls capacitor charging and discharging sources. A memory point is a stability condition flag for inhibiting the charging and discharging of the capacitor. A circuit for analyzing the converter output activates the flag when the successive values of the converter output meet a predetermined stability condition, and deactivates the flag when the successive values of the converter output meet a predetermined divergence condition.

Abstract: A digital black clamp circuit for calibrating the black level of an image signal produced by an imaging device, such as a CCD sensor. The digital black clamp circuit comprises a source of a video signal having a first interval of black level pixels and a second interval of image pixels; a differential amplifier having first and second inputs and an output, wherein the source is coupled to one of the first and second inputs; an A/D converter coupled to the output of the differential amplifier; a digital signal processor coupled to the A/D for accumulating and averaging digital black level pixels; a D/A converter coupled to the digital signal processor; and a control for selectively uncoupling the D/A converter to the other of the first and second inputs of the differential amplifier during the first interval of the video signal; and for coupling the D/A converter to the other of the first and second inputs during the second interval of the video signal to clamp the image pixels to an average black level.

Abstract: An image processing apparatus includes an analog image signal clamp and an A/D converter that converts the analog image signal into an m bit digital signal. The clamp is controlled in accordance with an n+1 (m>n) bit digital image signal converted by the A/D converter and an n bit digital image signal portion of the m bit digital image signal is processed.

Abstract: A device for adjusting a video signal so that its black level is in coincidence with a predetermined reference level includes a capacitor having a first terminal that receives the video signal and a second terminal that provides the adjusted video signal, and means for discharging the capacitor at a constant current when the adjusted video signal exceeds the reference level, and for charging the capacitor at a constant current when the adjusted video signal is below the reference level, the ratio between the charging and discharging currents ranging from 4.3 to 12.6. The device further includes means for significantly reducing the current ratio at least during a portion of a frame synchronization pulse train.

Abstract: A synchronizing signal clamping circuit for an integrated image signal processing circuit has an input buffer circuit for receiving a composite image signal; a level clamping circuit for clamping a synchronizing signal tip level of the composite image signal, in response to an error detecting signal; an error detecting circuit for detecting the difference between a reference voltage signal and the output synchronizing signal tip level of the composite image signal and for outputting the result as the error detecting signal, in response to a control signal; and a synchronizing signal interval distributor circuit which controls the error detecting circuit so that the error detecting circuit can detect the difference between said reference voltage signal and the synchronizing signal tip level of the composite image signal only for a period shorter than the interval of a synchronizing signal applied to a third input terminal.

Abstract: A video signal clamp involves evaluating the difference between the signal level and the desired clamp level during the back porch interval. A correction signal indicates whether the signal level must be increased or decreased to establish the desired clamp level. Generation of the correction signal involves a median filter algorithm. Any required increase or decrease of the signal level occurs continuously throughout each horizontal line interval.

Abstract: In an image pick up device, signal level of red, green and blue color signals is coarsely adjusted in a signal processing circuit, and then a black level of video signal is finely adjusted in a digital signal processing circuit, thereby being capable of easily adjusting the black level and improving the accuracy of black level adjustment.

Abstract: A clamp circuit including a clamping capacitor and a differential amplifier charge and discharge the clamping capacitor in accordance with the magnitude of difference signals applied to the differential amplifier's inverting and non-inverting inputs. The inverting input receives the voltage produced by the clamping capacitor. This voltage is digitized by an analog-to-digital converter (ADC) and is set to a reference voltage range by a voltage divider network. The ADC output signal is compared to a given reference level corresponding to a selected voltage in the reference voltage range to produce a difference output signal. This difference output signal is summed with the selected voltage in the reference voltage range and applied to the non-inverting input of the differential amplifier to produce a clamp voltage with substantially minimum offsets due to the amplifier, ADC and DAC.

Abstract: A method for detecting the warm-up of a television CRT includes the following steps during a warm-up phase of the tube: providing the CRT with warm-up signals during predetermined line periods at the initial portion of frames; and detecting the cathode current of the tube during the occurrence of windows in correspondence with the predetermined line periods in order to enable black level regulation loops. The windows have a width smaller than a line period and are approximately centered on the line periods.