Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.

Abstract: Apparatus and methods for scalable block pixel filtering are described. A block filtering instruction is issued to a processing element (PE) to initiate block pixel filtering hardware by causing at least one command and at least one parameter be sent to a command and control function associated with the PE. A block of pixels is fetched from a PE local memory to be stored in a register file of a hardware assist module. A sub-block of pixels is processed to generate sub-block parameters and the block of pixels is filtered in a horizontal/vertical edge filtering computation pipeline using the sub-block parameters.

Abstract: The present invention is directed to a method for determining whether a current macroblock and an adjacent macroblock thereof are located in the same slice. The method is used in a predetermined process for a block-based digitally encoded image. The block-based digitally encoded image is represented as an encoded bit-stream and each macroblock therein is assigned a sequence characteristic number. The method includes: providing a memory space for storing and tracing a slice changing point; initializing the slice changing point to a predetermined number; checking the encoded bit-stream, and when the current slice is determined to change, setting the slice changing point to a derived sequence characteristic number derived from the sequence characteristic number of the current macroblock; and determining whether the current macroblock and the adjacent block thereof are in the same slice according to a comparison result between the sequence characteristic number of the adjacent block and the slice changing point.

Abstract: According to one embodiment, using several random access memory components, these several RAM components are integrally driven to form a logical line memory. The number of using RAM components is reduced to the minimum, and thereby, hardware cost is reduced. A line memory forming apparatus comprises cascade-connected several RAM components, several line memories logically serial-connected in a manner that of the several RAM components, part of an output of the final-stage RAM component and part of an input of the first-stage RAM component are provided with several connection portions, and a controller controlling write address and read address of the several RAM components to drive the line memories.

Abstract: The present invention is directed to a line address computer for calculating the starting line addresses for lines of a decoded frame. The starting addresses for a display frame are provided to the line address computer by a host processor. The line address computer determines the starting line addresses for subsequent lines by appropriately incrementing the line addresses of previous lines.

Abstract: A memory access system and method for efficiently utilizing memory bandwidth is disclosed. A data arrangement unit arranges video data into at least a primary block and a supplemental block, which are then stored in a memory device. The video data are arranged such that the video data of the primary block stored in the memory device can be sequentially read by a device, thereby increasing efficiency in memory bandwidth usage and memory data access.

Abstract: When various content is broadcasted via the Internet, a user is free from restriction of time and space and user's desired content is provided. The content is controllably recorded and read to a random-access recording medium via a network, and at least the content read from the recording medium is transmitted to the network.

Abstract: A video display for digitized video data interpolates values between time samples, such as luminance over a horizontal line or over an average of all the horizontal lines in a video signal, so as to produce a digitally plotted test display resembling the continuous line display of an oscilloscope. A digital impulse response filter has stored coefficients that contribute as factors to the values of interpolated data points to fill the line display between sample values. Instead of changing the coefficients to produce variations interpolating the output between sample values, the coefficients are held constant and a delay factor is varied to alter the extent to which the respective coefficients and sample values interact and contribute to the interpolated values.

Abstract: In the present invention, the same image data, captured by a TV camera, is processed by the use of an image-processing board connected to an extension bus constituted by a personal computer and a CPU board inside the personal computer so that the CPU board and the image-processing board are allowed to execute the image processes in parallel with each other.

Abstract: An image processing apparatus is disclosed by which correction of convergence and correction of distortion of an image can be performed with a high degree of accuracy. Correction data to be used for correction of position errors of the three colors of red, green and blue obtained by an adjustment apparatus in advance are stored in a storage section. The stored correction data are outputted to a correction waveform outputting section through a control circuit when necessary. The correction waveform outputting section produces correction waveforms based on the correction data inputted thereto and outputs the correction waveforms to a clock signal generation circuit. The clock signal generation circuit generates clocks, and the video data of red, green and blue stored in the memory are read out in response to the clock signals.

Abstract: An image processing device of the present invention includes a plurality of processing sections for successively receiving and decoding a plurality of data blocks, which have been obtained by encoding a plurality of image blocks of an image. The plurality of processing sections include an inverse discrete cosine transform processing section for performing two-dimensional inverse discrete cosine transform. When one of the processing sections is unable to receive the data block, the one of the processing sections sends a busy signal to preceding one of the processing sections. When one of processing sections receives the busy signal, the one of the processing sections discontinues data block transfer to following one of the processing sections.

Abstract: New and improved methods and apparatus for code packing in a digital video system. Among others, a method of transferring a data block to a storage device is disclosed. The storage device can include a plurality of compartments. The method includes receiving a plurality of length values. Each length value can correspond to a data block from a plurality of data blocks. The method further includes filling a first compartment of the storage device with a portion of data from a first data block, searching the length values to identify one of the plurality of data blocks having a length value less than a threshold value, and filling a second compartment with a remaining portion of the data from the first data block. In one embodiment, the second compartment can correspond to the identified data block.

Abstract: A method and apparatus for storing a macroblock from a video data stream is disclosed. A macroblock is received, the macroblock having a plurality of blocks corresponding to a plurality of color space components and having a width defined by a plurality of pixels. According to a first aspect of the present invention, the macroblock is stored in a vertical strip format. According to a second aspect of the present invention, the contents of the plurality of blocks are interleaved. According to a third aspect of the present invention, the contents of the plurality of blocks are interleaved and the macroblock is then stored in a vertical strip format.

Abstract: A method of storing a picture in a memory such that the latency of the memory can be reduced when retrieving a picture from the memory to be displayed while still reducing the bandwidth when retrieving an array portion of the picture from the memory, and a memory architecture. The memory is subdivided into a plurality of words for storing a picture having rows and columns. The picture is partitioned into one or more tiles each having a predetermined number of rows and columns. The number of bytes in one row of one tile is equal to the number of bytes in one word, for storing the data in one row of a tile in one word. The chrominance Cr and Cb components can be stored in one word, with the first 8 bytes of the word containing one and the next eight containing the other.

Abstract: A video signal memory holds blocks of data representing luminance and first and second chrominance signals, the first and second chrominance signals being held in interleaved rows within the blocks, data being transferred from said blocks to a temporary store for use by a processor in predicting picture frames from the stored data.

Abstract: A method and apparatus for draining video data from a planarized video buffer in a video camera. The method includes the steps of reading a first sequence of video data from a first plane of the planarized image buffer starting at a buffer address indicated by a first pointer, and then reading a second sequence of video data from a second plane of the planarized image buffer starting at a buffer address indicated by a second read pointer. The apparatus includes an address generation unit and a sequence counter. The address generation unit includes a number of read pointers each configured to indicate a memory location within a different data plane of a video buffer. The address unit is configured to address a sequence of memory locations in a video buffer starting at a location indicated by an active one of the read pointers.

Abstract: A multi-channel memory system for holding video image data employs a particular form of interleaving in each channel to achieve optimum performance. Data representing luminance and chrominance components are written into the memory in respectively different channels such that the luminance information occupies one part of a memory row while the chrominance information occupies another part. The channel assignment is cycled within a memory row and is changed from one row of the memory to the next such that all luminance information in the row is contiguous and all chrominance information is contiguous yet luminance information and its corresponding chrominance information may be accessed in a single operation using all three channels. The memory is organized in three channels, each channel including two devices and each device including two banks.

Abstract: An information processing method used for compressing or decoding picture data wherein, in securing an area in which to store restored picture data, pre-set processing can be performed speedily without producing caching errors. Storage sites on a data memory are allocated to luminance signals and to associated chroma signals so that the luminance signals and the associated chroma signals will be copied in different locations in a data cache. The luminance signals and the associated chroma signals so allocated are stored in the data memory. For decoding, plural picture data related with one another are allocated to different locations in the data memory so that the picture data will be copied indifferent addresses in the data memory.

Abstract: A picture storage device conveniently employed in conjunction with an electronic still camera or a video camera has an input data converting unit for separating luminance signals of input color picture data having a non-interlaced data format with the sampling rate of the luminance signals and two-route color signals of 4:2:0 into a data string of even-numbered pixels and a data string of odd-numbered pixels, separating the two-route color signals of the color picture data into a data string of the former half pixels and a data string of the latter half pixels, and distributing and re-arraying the separated data, a storage unit having a storage capacity of at least one frame and adapted for storing data in a data re-arraying sequence by the input converting unit, a display data converting unit for converting the data stored in the storage unit into picture-displaying data, and a controller for controlling the input converting unit into synchronization with data writing in the storage unit.

Abstract: A field emission device (10) includes a video memory device (12) that receives video data in parallel for each of three colors red, green, and blue. The video memory device (12) provides the video data in color sequential manner to a controller (14). The controller (14) provides appropriate control and data signals in response to the video data to drive a field emission device display (22). The video memory device has a first storage area (30) for a first color (red), a second storage area (32) for a second color (green), and a third storage area for a third color (blue). The second storage area (32) has capacity to store all of the second color of a frame, the first storage area (30) is two-thirds the size of the second storage area (32), and the third storage area (34) is one-third larger than the second storage area (32). The different sizes of the respective storage areas allows for 100% use of memory space without waste.

Abstract: A hierarchial search for moving image encoding determines a motion vector by comparing a target block to sets of blocks selected according to the results of previous comparisons. Typically, each set of blocks includes a central block and four blocks offset on x and y axes. Blocks most similar to the target block provide co-ordinates of a center block in a next stage of the search. The hierarchial search searches regions indicated by previous comparisons to be similar to the target block and thereby reduces the number of comparisons and the search time required to find a motion vector. A motion estimation circuit for the hierarchial search includes: five processing elements which compare the target block to five blocks; a first memory that asserts a target block pixel value to the processing elements; a second memory that asserts five search window pixel values to the processing elements.

Abstract: A method and apparatus for efficient motion vector detection is disclosed that provides an expanded search window with a plurality of motion processors. The internal search window of each motion processor is arranged as a set of N row by M column rectangular subblocks. An address generator circuit scans a stream of pixel data values out of a reference frame memory while a set of delay circuits route the stream of pixel data values to the input paths for the internal subblocks and match input timing for the motion processors.

Abstract: A picture storage device conveniently employed in conjunction with an electronic still camera or a video camera has an input data converting unit for separating luminance signals of input color picture data having a non-interlaced data format with the sampling rate of the luminance signals and two-route color signals of 4:2:0 into a data string of even-numbered pixels and a data string of odd-numbered pixels, separating the two-route color signals of the color picture data into a data string of the former half pixels and a data string of the latter half pixels, and distributing and re-arraying the separated data, a storage unit having a storage capacity of at least one frame and adapted for storing data in a data re-arraying sequence by the input converting unit, a display data converting unit for converting the data stored in the storage unit into picture-displaying data, and a controller for controlling the input converting unit into synchronization with data writing in the storage unit.

Abstract: A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value.

Abstract: A moving picture decoding device in which picture data is read from a picture memory responsive to a motion vector to perform decoding the motion-compensated moving picture and in which the picture data is also read in a pre-set sequence for display. With the present moving picture decoding device, the combination of data, that is a word format, for a word simultaneously read from four memory devices (DRAMs), is set so as to be different for the motion compensation and for display. That is, during motion compensation, simultaneous reading of a word consisting of luminance (Y) signal component data D0, D1, D2 and D3 is time-divisionally changed over to simultaneous reading of a word consisting of chroma (C.sub.b and C.sub.r) signal component data D2, D3, D0 and D1. During display, two luminance data D0 and D1 (or D2 and D3) are read out simultaneously with the chroma (C.sub.b and C.sub.r) signal component data D2, D3 (or D0 and D1).

Abstract: A digital video signal that has been encoded using motion-compensated prediction, transform encoding, and variable-length coding, is decoded using parallel processing. Frames of the video signal are divided into slices made up of a sequence of macroblocks. The signal to be decoded is slice-wise divided for parallel variable-length decoding. Each variable-length-decoded macroblock is divided into its constituent blocks for parallel inverse transform processing. Resulting blocks of difference data are added in parallel to corresponding blocks of reference data. The blocks of reference data corresponding to each macroblock are read out in parallel from reference data memories on the basis of a motion vector associated with the macroblock. Reference data corresponding to each macroblock is distributed for storage among a number of reference data memories.

Abstract: An image information signal processing apparatus for processing a first image information signal having at least a first image signal and a second image signal which is different from the first image signal, and a second image information signal having a third image signal with a frequency band wider than that of the first image signal or the second image signal. When the first image information signal is input, the apparatus forms first image data corresponding to the first image signal and second image data corresponding to the second image signal by performing sampling of the first image information signal in accordance with a first sampling signal having a first sampling frequency. When the second image information signal is input, the apparatus forms third image data corresponding to the third image signal by performing sampling of the second image information signal in accordance with a second sampling signal whose frequency is higher than that of the first sampling signal.

Abstract: An image coding and decoding apparatus which can produce an improved amount of the effective data per time unit especially in a case where the image data are processed in the field unit.

Abstract: An apparatus for synchronizing a plurality of signals forming a picture signal is provided. The plurality of signals include at least two types of signals, each having a predetermined time unit. The two types of signals are alternately outputted. The apparatus include separate memory devices for separately storing the two types of signals having predetermined time units. A memory control mechanism is provided for successively writing the two types of signals in a manner such that the writing operation is alternated between a first memory device and a second memory device of the separate memory devices so as to provide alternate blank memory areas in the first and second memory devices. Thus, the signals of the same type as those written in areas adjacent to the blank memory areas can be written in the blank memory areas.

Abstract: A video storage arrangement produces a continuous video signal representing a test pattern. One luminance frame store is provided and two chrominance frame stores. A selection can be made between NTSC, PAL and SECAM modes. Switches are provided for selecting between chrominance frame stores and between inverting and non-inverting mode. Depending upon the selected broadcast standard, these switches are driven from field and line clock signals to generate the required output field sequence in YC or composite form.

Abstract: The present invention concerns a processing method for a video signal coded in the form of blocks of K words, this signal being written to or read from two frame memories (FM1, FM2) each including an input port, a high speed output port and a low speed output port. According to this method, the input digital video signal is formed by sets of M' blocks with N' block containing luminance data (Y1, Y2 . . . ) and M'-N' blocks containing chrominance data (C1, C2 . . . ), the blocks containing the chrominance data (C1) are written in the first memory (FM1) and the blocks containing luminance data (Y1) are written in the second memory (FM2). Then the blocks containing the luminance data and the blocks containing the chrominance data are read simultaneously on the high speed output port of each memory, the memories being inverted at each frame, and the data eventually being processed to obtain video data in output that presents a compression ratio M/N with M>N.

Abstract: A method and system for compressing color video or other image data for transmission over a low cost, low bandwidth bus (or other transmission link). Preferred embodiments implement lossless compression and include a frame buffer for storing data compressed in accordance with the invention, and circuitry for decompressing and transforming compressed data read from the frame buffer. The image data are typically organized as a sequence of frames, each comprising a sequence of pixels. Data compressed in accordance with the invention are stored in cells in memory, with each cell storing the same number of pixels. The inventive method is denoted as "cell based image compression" ("CBC"). Advantages of CBC include increasing available data transmission bandwidth and lowering required system power as a result of minimizing transfer of redundant color information to and from memory as well as fast random single pixel reads and writes.

Abstract: A method and apparatus for time multiplexing and demultiplexing two channels of picture information within a standard video channel. The method is specifically designed for field sequential stereoscopic display applications, but may be used for non-stereoscopic applications where conservation of bandwidth is required. The technique is superior to prior art commercially available stereoplexing approaches, and increases vertical resolution while decreasing stair-stepping of diagonal lines. The demultiplexing display controller of the invention can be manufactured at a low cost because its design takes advantage of commercially available integrated circuits.

Abstract: There is disclosed a control circuit of a memory device of a random access type for storing first data and second data whose reading/writing cycle time is longer than that of the first data, including: a memory circuit for reading/writing a predetermined number of first data into/from each memory block which is obtained by dividing the memory device into at least two or more memory blocks, for reading/writing the second data into/from the other memory blocks, and for supplying address signals for the reading/writing cycle period of time of the second data; and a memory switching circuit for switching and using the memory blocks in order to read/write the first and second data, so that the memory device can be accessed at a high speed by using a small capacity.

Abstract: The present invention divides a video frame into a series of smaller and smaller quadrants until reaching a single pixel size. By issuing a series of commands, a logical cursor moves within the quadrants to evaluate the frame for changes from the previous frame. Upon detecting a color change, the exact location (identified by a level and a quadrant thereof) is encoded along with a value for the change. As a result of the novel approach disclosed herein, there may be significant storage savings over the prior art.

Abstract: At the time of registration, an image processing apparatus registers color information (R, G, B) from a host computer as permanently registered information in a buffer and as temporarily registered information in a table in accordance with a command from the host computer. The data registered in the buffer also is registered in the table and is used as internal data until initialization is performed. At the time of initialization, the data registered in the table is initialized with the exception of the data that has been registered from the buffer, if the command is indicative of a soft reset. In case of a hard reset, all of the data in the table is initialized.