Abstract: Techniques for lossless compression of a digital image using prior image context.

Abstract: Techniques are described that enable digital images to be delivered using a video codec that operates according to a video encoding standard. These techniques include encoding digital images as frames of video content files, and decoding the frames of the video content files to display the images.

Abstract: A video encoder may compare frames to generate a difference frames. The difference frame may be apportioned to generate a plurality of portions. Portions meeting a threshold pixel number condition are selected for compression. The threshold pixel number condition may measure the number of pixels which exceed an intensity threshold.

Abstract: A right image and a left image is provided. Then a disparity estimation map relating to both images is provided and a left subtitle detection map for the left image and a right subtitle detection map for the right image are generated. Each map indicates subtitle areas within an image. For said subtitle areas and based on said disparity estimation map a subtitle disparity value for X and Y directions common for all subtitle areas is determined. Said left and right subtitle maps and said subtitle X and Y disparity values are used in an image interpolation process.

Abstract: A data communication system includes a centralized server arrangement coupled via a communication network arrangement to a plurality of client devices. The centralized server arrangement and the plurality of client devices exchange data. The system allocates the data into a primary type of data and at least a secondary type of data. The primary data is communicated substantially immediately within the system, and the at least secondary data is communicated in the system in association with corresponding acknowledgements (ACK) in response to receipt and processing of the at least secondary type of data at one or more of the client devices. At least one of the one or more client devices is optionally a wireless-enabled mobile communication device or a wirelessly-connected personal computer (PC).

Abstract: A video communication system comprising at least one video data transmission unit for sending or receiving video data over a data network is disclosed, as well as a corresponding video data transmission method. The transmission unit comprising an image acquiring circuitry or an image reconstruction circuitry for acquiring or reconstruction an image frame or image field, a video processing unit for processing at least part of the video data and a communication unit for sending or receiving at least part of the data. At least two of the image acquiring circuitry or image reconstruction circuitry, the video processing unit and the communication unit are arranged for simultaneously handling different parts of a same image frame or image same field of the video data.

Abstract: An image processing apparatus reads an image out of a frame buffer by vertically flipping the image, writes the image into an output line buffer by horizontally flipping the image, divides each line, and simultaneously outputs the resulting line segments. Methods for vertical flipping, horizontal flipping, and simultaneous output are changed according to the output settings.

Abstract: A display apparatus which is controllable by a remote control apparatus is provided. The display apparatus includes: a communicator which communicates with the remote control apparatus, a storage which stores user interface (UI) screen information which is mapped to each application executable in the display apparatus, and a controller which, if a first application is executed based on a user command, controls a transmission of UI screen information corresponding to the first application from among the UI screen information stored in the storage to the remote control apparatus.

Abstract: A method of operating a camera with a microfluidic lens to identify a depth of an object in image data generated by the camera has been developed. The camera generates an image with the object in focus, and a second image with the object out of focus. An image processor generates a plurality of blurred images from image data of the focused image, and identifies blur parameters that correspond to the object in the second image. The depth of the object from the camera is identified with reference to the blur parameters.

Abstract: A prediction means for predicting a maximum delayed change time, which is the longest in a change time which allows a next program to be displayed, if a channel is selected to change the current program to the next program; and a display control means, by which, from a reception completion time when the reception of the current program has been completed, a relevant program is displayed on the basis of original program data remaining in a buffer at the relevant reception completion time, and at the same time, the reproduction speed of the display is based on a speed at which the current program is displayed during the period between the reception completion time and a maximum delayed change time.

Abstract: A visual display includes at least a first canvas configured to display a first session on the display and a second canvas configured to display a second session on the display. The first session includes first content received from a first content source and the second session includes second content having subject matter associated with the first content. The display includes a user agent configured to determine that the first content of the first session is associated with the second content of the second session and to pair the first and second canvases such that the first content and the second content are synchronized to each other.

Abstract: According to one embodiment, an information processing apparatus includes a first receiver, a screen transmitter, a second receiver and a controller. The first receiver receives first information associated with a display function of an external device. The screen transmitter generates an operation screen for operating the apparatus based on the first information, and transmits a video signal of the generated operation screen to the external device. The second receiver receives second information associated with content of an operation on the operation screen from the external device. The controller controls operation of the apparatus based on the second information.

Abstract: Systems and methods for calibrating a 360 degree camera system include imaging reference strips, analyzing the imaged data to correct for pitch, roll, and yaw of cameras of the 360 degree camera system, and analyzing the image data to correct for zoom and shifting of the cameras. Each of the reference strips may include a bullseye component and a dots component to aid in the analyzing and correcting.

Abstract: A system is disclosed for controlling operation of an electronic device, such as a TV. The system includes a first sensor located at or near the electronic device and a second sensor spaced apart from the first sensor, wherein the first and second sensors are configured to detect motion of a user within an operating zone associated with the electronic device. A processor is coupled to the electronic device and the first and second sensors, the processor being configured to input a signal from the first and second sensors. Memory is coupled to the processor, the memory comprising a sensing algorithm configured to process the input signal from the first and second sensors and determine the location of the user with respect to the operating zone. The processor is configured to send a control command to the electronic device based on an output of the sensing algorithm.

Abstract: An image processing device includes: a control section configured to allow, upon receipt of a moving image that includes, in time-series order, an original image and a duplicate image, a frame memory to hold a partial region in the original image and a remaining region in the duplicate image, in which the duplicate image is a duplicate of the original image, and the remaining region is a region excluding a region that agrees with the partial region; and an image processing section configured to read a piece of data that includes the partial region and the remaining region from the frame memory a plurality of times, and perform image processing by processing any of the read pieces of data as the original image and the remaining piece of data as the duplicate image.

Abstract: Video processing arrangement including a host computer, a video asset coupled to the computer for generating video signals, and an interface for connecting the video asset to the computer to enable the display of the video signals on a monitor. The video asset includes primary elements such as a primary composite video module that produces different types of a primary video signal and outputs the primary video signal, and a secondary video source module that produces a secondary composite video signal and outputs the secondary composite video signal. The primary composite video module includes a memory component including a user-programmable sequence of bits representative of a video signal and user-programmable signal generators synchronized to the primary video signal output of the primary composite video module. The memory component includes four user specified pulse memories which each hold a series of arbitrary bit line patterns.

Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.

Abstract: There are provided a video processing apparatus and a video processing method. The video processing apparatus includes: a buffer for storing data of an image frame inputted from the outside in the unit of line; a memory unit for randomly writing and reading data; a video processing unit for processing and outputting the image frame; and a central processing unit for inverting the image frame left-side right and/or upside down when writing the image frame stored in the buffer in the memory unit and/or reading the image frame from in the memory unit.

Abstract: A video test pattern generator and method include a control sequencer configured to control one or more address counters to generate a video test pattern. A first memory is configured to store pixel values for transitions between portions of the video test pattern and configured to store a repeated pixel value. A second memory is configured to store pattern information to determine placement of the pixel values for the transitions and the repeated pixel values. A repeat counter is configured to control a number of the repeated pixel values produced before a next transition.

Abstract: An advertising apparatus 10 including a generally flat base 12 and a broad face 14 which forms an acute angle 16 with the generally flat base 12. Further, the broad face 14 includes several display portions 20, 22, and 18 which, in one non-limiting embodiment of the invention, are programmable. In one non-limiting embodiment, the apparatus may include a selectively depressible alarm switch 100.

Abstract: Apparatus and methods for scalable block pixel filtering are described. A block filtering instruction is issued to a processing element (PE) to initiate block pixel filtering hardware by causing at least one command and at least one parameter be sent to a command and control function associated with the PE. A block of pixels is fetched from a PE local memory to be stored in a register file of a hardware assist module. A sub-block of pixels is processed to generate sub-block parameters and the block of pixels is filtered in a horizontal/vertical edge filtering computation pipeline using the sub-block parameters.

Abstract: An information processing apparatus for decoding compression-coded video data, including: at least one decoder that decodes the compression-coded video data; and a controller than controls processing executed by the decoder, wherein the controller, when a picture at a head of a decoding processing unit is an I-picture or a P-picture among decoded pictures output from the decoder, controls the decoder so that a decode start timing at which the decoder starts decoding and a display output timing at which the decoder starts outputting the decoded pictures are displaced from each other by a first predetermined number of pictures.

Abstract: In order to realize efficient memory access by reducing frequency at which areas specified by different row addresses in the same bank in a memory are consecutively accessed, the data processing apparatus (10) performs mapping so as to store data (21) and data (22), which are the same data, with use of the first arrangement and the second arrangement, respectively, in different memory areas constituting a memory (20). When reading a portion of the data, a selecting unit (21) selects one of the arrangements that is more efficient in accessing the portion of the data based on an address range corresponding to the portion of the data according to each arrangement, and an access control unit (13) accesses a memory area corresponding to the selected arrangement. Here, the data (21) is mapped to a position different from a position of the data (22) in terms of relative positions with respect to boundary addresses of blocks each corresponding to the same row address in the same bank.

Abstract: Systems and methods for the synchronization and display of video input signals. The input signals, associated with input channels, are received by a controller. On a frame-by-frame basis, the controller controls the writing of the input signals to, and the reading of the input signals from, a memory. A frame rate control module controls frame-level synchronization between the writing operations and reading operations of the controller so that when a frame is written to the memory is not simultaneously read from the memory. The controller writes video frames for each input channel to, and reads video frames for each input channel from, the memory on a channel-by-channel basis such that the video frames corresponding to each input channel are read and written independently of one another. This allows the input signals to be unsynchronized with one another without harming the writing operations, reading operations, and display of the input signals.

Abstract: The present invention is directed to a method for determining whether a current macroblock and an adjacent macroblock thereof are located in the same slice. The method is used in a predetermined process for a block-based digitally encoded image. The block-based digitally encoded image is represented as an encoded bit-stream and each macroblock therein is assigned a sequence characteristic number. The method includes: providing a memory space for storing and tracing a slice changing point; initializing the slice changing point to a predetermined number; checking the encoded bit-stream, and when the current slice is determined to change, setting the slice changing point to a derived sequence characteristic number derived from the sequence characteristic number of the current macroblock; and determining whether the current macroblock and the adjacent block thereof are in the same slice according to a comparison result between the sequence characteristic number of the adjacent block and the slice changing point.

Abstract: The present invention provides a method and system for providing access to information of potential interest to a user. Closed-caption information is analyzed to find related information on the Internet. User interactions with a TV which receives programming including closed-caption information are monitored to determine user interests. The related closed-caption information is analyzed to determine key information therein. The key information is used for searching for information in available resources such as the Internet, and the search results are used to make recommendations to the user about information of potential interest to the user.

Abstract: An apparatus includes a memory which successively stores frame data of video data, an interpolating unit which generates interpolation frame data which is inserted between the frame data and stores the interpolation frame data in the memory, and a readout unit which successively reads out the frame data and the interpolation frame data from the memory at a frame rate higher than a frame rate of the video data. The apparatus further includes a generating unit which generates image data which is composited with the frame data and stores the image data in the memory, and a control unit which, based on display-related characteristics of the image data, controls the interpolating unit to halt the generation of the interpolation frame data, and also controls the readout unit to read out the frame data in duplicate instead of the interpolation frame data.

Abstract: A memory accessing apparatus and a method thereof are provided, which are suitable for methods and apparatuses that access memory data in blocks, such as a video decoder. An advanced memory mapping method is adopted to generate the column address and row address of a data word in a memory based on the logic address of the data word in a video frame. Macroblocks are organized into clusters, macroblocks of the same cluster are stored in the same row of the memory, and the orders in which the video decoder reads and writes macroblocks are rearranged so as to reduce the number of row changes in memory access and improve the throughput of memory access. Furthermore, memory accesses between the video decoder and the display controller can be coordinated.

Abstract: An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: According to one embodiment, using several random access memory components, these several RAM components are integrally driven to form a logical line memory. The number of using RAM components is reduced to the minimum, and thereby, hardware cost is reduced. A line memory forming apparatus comprises cascade-connected several RAM components, several line memories logically serial-connected in a manner that of the several RAM components, part of an output of the final-stage RAM component and part of an input of the first-stage RAM component are provided with several connection portions, and a controller controlling write address and read address of the several RAM components to drive the line memories.

Abstract: Methods and systems for performing interleaved to planar transformation operations in a mobile terminal having a video display are disclosed. Aspects of one method may include extracting similar color space components from a received block of interleaved YUV color space format video data as data is received, where the block may comprise 128 bits. The similar color space components may be extracted and transferred to a memory, where each type of the similar color space components may be stored contiguously in separate portions of the memory in planar format. The transferring of data may be via direct memory access of 32-bit words. When the line buffer that is receiving the interleaved video data is full, a direct memory access operation may be initiated. Direct memory access operation may also be initiated when the data for a similar color space component for a complete horizontal line is extracted.

Abstract: A signal processing device with high efficiency of teletext information processing is provided. The signal processing device is configured to receive and encode a transport stream for display, wherein the transport stream provides teletext information associated with a plurality of teletext lines and video information associated with a plurality of video lines. The video signal processing device includes a memory configured to store line enable signals and line data associated with the teletext lines and the video lines, a VBI controller coupled to the memory, configured to read the memory to obtain the line data associated with enabled teletext lines of the teletext lines, and an TV encoder coupled to the VBI controller, configured to receive and encode the line data associated with the enabled teletext lines for display.

Abstract: Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.

Abstract: A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

Abstract: A system and method, for reprogramming registers without having to reprogram unchanged registers. The registers are divided into groups based on common characteristics or functions. The values for the groups that differ from the current values are written into a linked list, which is then loaded into the appropriate registers. The linked list contains information indicating the groups of registers in the linked list.

Abstract: A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first dimension of a first length and a second dimension of a second length. Each of the beams spans a portion of the first length of the first dimension and a portion of the second length of the second dimension. The method also includes scrolling the plurality of beams along the second dimension of the spatial light modulator while maintaining at least a first gap between each of the plurality of beams.

Abstract: The present invention is directed to a line address computer for calculating the starting line addresses for lines of a decoded frame. The starting addresses for a display frame are provided to the line address computer by a host processor. The line address computer determines the starting line addresses for subsequent lines by appropriately incrementing the line addresses of previous lines.

Abstract: In accordance with an embodiment, a method of operating a video server includes receiving a first video bitstream, storing the first bitstream in a memory, generating a second video bitstream from the first video bitstream, and storing the second video bitstream in the memory. The first video bitstream has a plurality of independently coded views and the second video bitstream has one of the plurality of independently coded views.

Abstract: When various content is broadcasted via the Internet, a user is free from restriction of time and space and user's desired content is provided. The content is controllably recorded and read to a random-access recording medium via a network, and at least the content read from the recording medium is transmitted to the network.

Abstract: An electro-optical device includes a plurality of pixels arranged in association with intersections of a plurality of scanning lines and a plurality of data lines, each of the plurality of pixels displaying a grayscale level corresponding to a data signal supplied to a corresponding data line when a scanning line is selected; a memory that stores upper n bits of input image data in which the grayscale level of each of the plurality of pixels is designated by m bits and that reads the stored n bits of image data, where “m” and “n ” represent positive integers satisfying a condition m>n; an adding circuit that adds lower (m?n) bits to the n bits of image data read from the memory; a selector that selects the input image data when the m bits of image data are input and that selects image data including the (m?n) bits added thereto by the adding circuit when the n bits of image data are read from the memory; a scanning line driving circuit that selects, from among the plurality of scanning lines, the scanning

Abstract: There is provided a multi-screen synthesis apparatus that can execute display of video data and update of an OSD image without causing a user to feel a visual sense of incongruity, and reduce system costs. Periodic video source data and aperiodic OSD image data are written into a unified memory reserved for planes. The video source data and the OSD image data are read from the unified memory, based on a synthesis layout, for simultaneous display on a single display in a synthesized state. Video data to be written into the unified memory is decimated in units of a frame on an input video source-by-input video source basis. The decimation of the data is controlled based on display priority of the video data determined based on a multi-screen display layout.

Abstract: There is provided a moving picture processing device (100) that has a display unit (120), a main processor (150), a display control unit (160), and a main memory (180). Using an overall-moving-picture data item stored in the main memory (180), the display control unit (160) and the display unit (120) play the overall moving picture (AM1), whereby a plurality of sectional moving pictures (SM11 to SM14) is displayed. In other words, displaying one moving picture enables a plurality of moving pictures to be displayed. Therefore, by using the moving picture processing device (100), it is possible to simultaneously display more moving pictures than those determined depending on the device's capacity to play moving pictures.

Abstract: An information processing apparatus for decoding compression-coded video data includes at least one decoder decoding the compression-coded video data, a supply controller controlling the supply of the compression-coded video data to the decoder, and a controller controlling processing executed by the supply controller and the decoder. The controller determines the order of decoding processing performed by the decoder so that, among pictures contained in a decoding processing unit for the decoding processing performed by the decoder, I-pictures and P-pictures are decoded before B-pictures. The controller selects pictures to be output from the decoder from among the pictures contained in the decoding processing unit on the basis of a playback speed instruction provided by a playback speed instruction unit.

Abstract: A video data displaying device is disclosed. The video data displaying device is used to drive a displayer according to a first display data set to display a first picture, the displaying device comprises a memory for storing the first display data set, and a display engine which is electrically connected to the memory for storing a part of the first display data set stored in the memory, wherein the display engine selects a specific display data set from the first display data set according to a display area of the displayer, and the display engine does not output the specific display data to the displayer.

Abstract: A video processing method utilized in a video data processing device for processing video data is disclosed. The video data includes at least a first video data set, and the video data processing device has a memory and a video decoder. The method includes utilizing the video decoder to decode the video data for generating a display data set, driving the video decoder to select a specific video data set from the first video data set wherein the display data set does not have display data corresponding to the specific video data set, and utilizing the memory to store the display data.

Abstract: Presented herein is a system for storing macroblocks for concatenated frames. A decoder system comprises a frame buffer. The frame buffer comprises one or more rows. A particular one of the rows stores macroblocks from a plurality of frames.

Abstract: Presented herein are Tertiary Content Addressable Memory based motion estimator(s). In one embodiment, there is presented a method for encoding a picture. The method comprises storing a reference picture in a memory; taking samples from at least one line of a prediction block; generating at least one data word, the data word being a function of the samples; addressing the memory with the at least one data word; receiving one or more addresses, said one or more addresses associated with one or more blocks; and selecting a reference block from the one or more blocks for the prediction block.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: A video communication system comprising at least one video data transmission unit for sending or receiving video data over a data network is disclosed, as well as a corresponding video data transmission method. The transmission unit comprising an image acquiring circuitry or an image reconstruction circuitry for acquiring or reconstruction an image frame or image field, a video processing unit for processing at least part of the video data and a communication unit for sending or receiving at least part of the data. At least two of the image acquiring circuitry or image reconstruction circuitry, the video processing unit and the communication unit are arranged for simultaneously handling different parts of a same image frame or image same field of the video data.