Abstract: Plural-conversion radio receivers for receiving DTV signals, in accordance with the Advanced Television Systems Committee (ATSC) standard, or analog TV, in accordance with the National Television Sub-Committee (NTSC) standard, utilize a first intermediate-frequency band spanning 917-923 MHz and a second intermediate-frequency band spanning 35.5-41.5 MHz. A local oscillator generates local oscillations at 958.5 MHz for mixing with signal in the first intermediate-frequency band to generate signal in the second intermediate-frequency band. These local oscillations do not interfere with the aeronautical navigation band or with channel 81 television broadcasting. The second harmonic of sound carrier in the second intermediate-frequency band falls below the 88-108 MHz FM broadcast band.

Abstract: A video transmitting apparatus having a plurality of transmission medium for transmitting multiplexed video information, a plurality of video information receiving units each connected to a corresponding transmission medium to receive specific video information on the corresponding transmission medium, a video displaying unit for displaying video information, a switcher for connecting the video displaying unit to any one of the video information receiving units to supply video information to the video displaying unit, and a video display requesting unit for communicating with each of the video information receiving units and the switcher to request to display specific video information on the video displaying unit by giving instructions to a relevant video information receiving unit which can receive the specific video information and the switcher.

Abstract: A radio receiver uses the same tuner for receiving a selected digital television (DTV) signal, irrespective of whether it is a quadrature-amplitude-modulation (QAM) or a vestigial sideband (VSB) signal. The final IF signal is digitized at a rate that is a multiple of both the symbol frequencies of the QAM and VSB signals, for synchrodyning to baseband. The carrier frequencies of the QAM and VSB final IF signals are regulated to be submultiples of the multiple of both the symbol frequencies of the QAM and VSB signals by applying automatic frequency and phase control (AFPC) signals developed in the digital circuitry to a local oscillator of the tuner. Baseband DTV signals obtained by synchrodyning the final IF signals have a sample rate higher than symbol rate to facilitate symbol synchronization. The baseband DTV signals are decimated to symbol rate before performing channel equalization to reduce the number of multipliers required in the channel equalization filter.

Abstract: In a signal transmission chain containing, for example MPEG2 coders (12, 20, 28) and decoders (24, 30), an information channel extends throughout the signal chain. Signal processing elements in the chain take advantage of information (VP) on the information channel and also add to it information (VP) concerning the process performed by that signal processing element. The information channel, towards the end of the signal transmission chain, therefore carries information (VP) relating to all or most of the various processes performed by in the chain.

Abstract: A television receiver for processing both analog television signals and digital television signals. Specifically, the television receiver contains a RF/IF front end, an analog-to-digital converter that samples a near baseband signal using a "free running" sample rate, and a combined demodulator that demodulates the digitized analog television signals or the sampled digital television signals. The combined demodulator recovers both pilot and pix carriers as well as provide a passband adaptive equalizer that removes ghosts from analog television signals and intersymbol interference from digital television signals.

Abstract: A processing device for video signals has a memory device suitable to store discrete image elements of a video field and a filtering device supplied by the memory device and suitable to recover errors introduced by the memory device. The filtering device includes a filter, noise detector means, and soft-switch means. The filter has an input supplied with digital signals representative of values of a plurality of discrete image elements and comprises an image element to be examined and neighboring image elements. The discrete image elements is stored in the memory device, and an output supplying digital signals representative of a filtered value of the image element to be examined. The noise detector means operating on fuzzy-logic rules has an input supplied with the digital signals representative of the plurality of values of the image elements and an output supplying a weight signal representative of a degree of erroneousness of the discrete image element to be examined.

Abstract: A receiving process is realized with a simple configuration when a plurality of sources such as in the television broadcasting or the like are transmitted efficiently at the same time. A plurality of transmission bands are prepared each including a predetermined number of subcarriers arranged at a predetermined frequency interval. The signal of each transmission band is delimited at a predetermined time interval to form a time slot. For transmitting a plurality of data A to P, after individual data are transmitted during a predetermined time slot period using a predetermined transmission band, the transmission band is switched to the separate transmission band and the particular individual data is transmitted during a predetermined time slot period. The receiving band is switched at the receiving side in an interlinked relation with the switching of the transmission band for transmitting the desired data.

Abstract: A video receiver includes a tuner, a QAM demodulator including a selective gated PLL carrier recovery circuit, and a digital equalizer. The selective gated PLL carrier recovery circuit has a normal operation mode and a selection control mode. The channel changing of the tuner is performed after the selective gated PLL carrier recovery circuit is set to the selection control mode and the digital equalizer is held at its current state.

Abstract: A radio receiver uses the same tuner for receiving a selected digital television (DTV) signal, irrespective of whether it is a quadrature-amplitude-modulation (QAM) or a vestigial sideband (VSB) signal. The final IF signal is digitized at a rate that is a multiple of both the symbol frequencies of the QAM and VSB signals, for synchrodyning to baseband. The carrier frequencies of the QAM and VSB final IF signals are regulated to be submultiples of the multiple of both the symbol frequencies of the QAM and VSB signals by applying automatic frequency and phase control (AFPC) signals developed in the digital circuitry to a local oscillator of the tuner. Baseband DTV signals obtained by synchrodyning the final IF signals have a sample rate higher than symbol rate to facilitate symbol synchronization. The baseband DTV signals are decimated to symbol rate before performing channel equalization to reduce the number of multipliers required in the channel equalization filter.

Abstract: A method and apparatus for increasing the processing speed or decreasing circuit complexity (or both) of a digital image processor by eliminating the conventional multiplication operation from the RGB to YUV and YUV to RGB transforms having NTSC compatible equation coefficients. In particular, the change of color-basis matrix for converting RGB data to obtain YUV data is factored into a scale factor and a coefficient matrix. The coefficient matrix contains coefficients such that its product with the RGB input vector can be performed using only seven binary additions and five shift operations. This process effectively removes the conventional multiplication operations from the RGB to YUV conversion. The scale factor is conveniently absorbed into the quantization of the YUV data before transmission. The quantization process includes a multiplication already and the two multiplication steps are folded into one step.

Abstract: A method of adaptively performing motion compensation in a video processing apparatus is provided. The video processing apparatus processes macroblocks of compressed video information. Some of these macroblocks have motion vectors associated therewith. The method is conveniently implemented on a general purpose computer in one embodiment. In accordance with the disclosed method, the performance of the processor in the computer is monitored and a measurement of this performance is made. A threshold dependent on the measured processor performance is then set. For those macroblocks which have motion vectors associated therewith, the magnitude of the motion vector is determined. If the magnitude of the motion vector of a particular macroblock exceeds the threshold, then motion compensation is performed on that macroblock. However, if the magnitude of the motion vectors or motion vectors associated with a particular macroblock do not exceed the threshold, then no motion compensation is performed.

Abstract: A video processing system includes but structure, signal flow, and components to process and combine audio and video signals with improved power, cost-effectiveness, and flexibility. The system includes one or more input modules to convert input video signals to a predetermined format. A router routes converted video signals to selected ones of upstream processing cards, which perform video processing such as digital video effects, frame synchronization, non-linear editing, cascading, filtering, and the like. Signals from the upstream processing cards are directed to a switcher, which selectively mixes the upstream-processed signals. A switcher preview module may be provided to intermediately view signals provided by the switcher. The switcher is also attached to a series of downstream video processing cards, which may insert logos, add overlaying, and other suitable post-mixing functions.

Abstract: An adaptive trellis decoder seamlessly switches between multiple operational modes. The trellis decoder employs a code sequence detection system that detects codes in input interleaved packet data. The code sequence detection system also reduces the delay (latency) between the input of encoded data and the output of decoded data. The code sequence detection system processes video data in the form of groups of interleaved trellis encoded data packets and includes a traceback network that identifies a sequence of antecedent trellis states, in accordance with a state transition trellis. The traceback network identifies the antecedent states for collocated interleaved packets in response to decision data associated with trellis state transitions. Output trellis decoded data is provided in response to the identified sequence of antecedent trellis states. The decoder can also provide a plurality of trellis decoded data sequences.

Abstract: Image data is processed in the form of digitized frames on a video clip. A first clip is received in combination with a second clip. Frames are alternately supplied from each of said clips to a real time rendering device configured to produce a viewable composited clip at video rate. By making use of a rendering engine primarily designed for rendering synthesized images, it is possible to view many video effects, such as dissolves and wipes, in real time.

Abstract: A television signal receiver for processing an HDTV signal transmitted in a vestigial sideband (VSB) format includes input complex filters shared by a timing recovery network (30) and a carrier recovery network (50). The filter network includes a pair of upper and lower band edge filters (20, 22) mirror imaged around the upper and lower band edges of the VSB signal for producing suppressed subcarrier AM output signals. The timing recovery network includes a phase detector (28, 38, 62) and responds to an AM signal derived from the two filters (via 26) for synchronizing a system clock (CLK). The carrier recovery network (50) also includes a phase detector (54, 60, 62, 64), and responds to outputs from one or both of the filters for producing an output error signal (.DELTA.) representing a phase/frequency offset of the VSB signal. The error signal is used to reduce or eliminate the offset to produce a recovered baseband or near baseband signal.

Abstract: The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.

Abstract: A video signal is supplied from a digital VTR 1 and is encoded by an MPEG encoder 8. The encoded video signal is recorded as a compressed video signal in an HDD 9. A plurality of compressed video signals are recorded in the HDD 9 and addresses of the compressed video signals are stored in a controller 6. MPEG decoders 12 and 14 decode the compressed video signals which are read out from the HDD 9. After a video signal processing apparatus 3 executes an editing process on the decoded video signals, a synthesized video signal is supplied to a digital VTR 10 through a switch 7. The synthesized video signal recorded in the digital VTR 10 is supplied to the video signal processing apparatus 3 for further processing through a switch 13 without being decoded.

Abstract: Input image data and audio data divided into a plurality of portions are continuously recorded in a solid-state memory. When the audio data is to be reproduced in units of the portions, a reproducing start address of each portion of the audio data is changed in an order different from that in recording, thereby reproducing the audio data. The image data is divided into a plurality of portions corresponding to the plurality of portions of the audio data. The image data is reproduced in units of the portions. At this time, the reproducing start address of each portion of the image data is changed in an order different from that in recording, thereby reproducing the image data. With this arrangement, even when the image and audio data are reproduced in an order different from that in recording, the reproduced audio data can be confirmed.

Abstract: A scalable architecture MPEG2 compliant digital video encoder system having an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. For IPB bitstreams the system includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element motion estimation. The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips, that is one for each processor, the I-frame video encoder module, the second processor element, and the third processor element. There can be one or more of the third processor units.

Abstract: As processing a digital information signal (a digital video signal etc), the improvement in the accuracy of the signal process can be made by integrating the time region process and the frequency region process. An input digital video signal is supplied to a DCT circuit 3. The DCT circuit 3 converts the input video digital signal into coefficient data. A categorizing circuit 5 separates a flat component 6a and an impulse component 6b in a frequency region from the input signal. The flat component 6a is supplied to an inverse DCT circuit 7. The inverse DCT circuit 7 converts the input signal into a signal on a time axis. A class categorizing adaptive processing circuit 9 compensates a resolution in a time region. The impulse component 6a is supplied to a gain converting circuit 10. The gain converting circuit 10 compensates the high band in a frequency region. The output signal of the gain converting circuit 10 is supplied to an inverse DCT circuit 11.

Abstract: In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected.

Abstract: Processing a moving image such that, after an input video signal is supplied to an image inputter, the image inputter time-divisionally converts the input video signal to a digital signal and outputs a control signal such as a vertical synchronous signal. A multiplexer reads image data converted by the image inputter into the digital signal and stores them into a plurality of temporary storers unique for frames according to the control signal from the image inputter. The plurality of temporary storers are respectively connected with a plurality of processor elements which process the memory contents of the plurality of temporary storers and re-store the processing results back in the plurality of temporary storers. A multiplexer sequentially retrieves the memory contents from the plurality of temporary storers, and has an image outputter for converting a digital signal to a video signal output them.

Abstract: A television signal format converter is provided for converting without loss of picture information a television format to or from a given recorder/player format. An interface converts between RGB and luminance/chrominance inputs and between analog and digital inputs. The interface couples a source television format to a plurality of pairs of memories. A clock and control circuit controls addressing of the memories for reading and writing so that conversion is performed with an improved luminance signal-to-noise ratio between a source television format and the format required for a given high definition digital video tape recorder or any other comparable recorder.

Abstract: This invention relates to a device for correcting DC of a HDTV, which can correct DC(Direct Current) that is liable to cause in mixers, base band amplifiers and ADC(Analog/Digital Converter) for a HDTV receiver. The device includes a non-interference DC detector for detecting DC from digital signals of an I channel and a Q channel applied under non-interference conditions in which an IF signal input has been cut off. An interference DC detector for detecting DC from the digital signals of an I channel and a Q channel applied at every field according to data field synchronization signal applied from outside. A selection part for selecting either one of the DC values received from the non-interference DC detector and the interference DC dectector. And, a D/A conversion part for D/A conversion of the DC value received from the selection part. Whereby, the DC value varying with time can be corrected by using field synchronization data and without turning the switch of IF terminal off.

Abstract: It is an object of the present invention to restrict EMI radiation at a specific frequency by inserting a delay time that is effective for that frequency. The feature of the present invention is to provide a delay generator that can selectively alter delay times. The delay generator comprises: delay means, which is connected to a plurality of data input lines, and which has a plurality of delay paths for the generation of a plurality of alternative delay times; a register for storing a digital value of pre-determined bit; and selection means for selecting one of the delay paths in consonance with the digital value and for providing the selected delay path for the signal lines.

Abstract: Pixel data is stored and subsequently read from a random access memory of a video decompression processor in a manner that reduces the number of times different rows of the RAM must be addressed in order to retrieve portions of the pixel data therefrom. Pixel data from a video frame is stored in the RAM as a plurality of pages. Each page substantially fills a different row of the RAM and corresponds to a different section of the video frame. A motion vector is decoded to determine the location of a prediction area within the video frame. In the event that the prediction area encompasses more than one of the pages of the video frame, the pixel data is retrieved one page at a time, minimizing the number of row changes required when addressing the RAM to retrieve the data.

Abstract: A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing n data values at a time from the memory modules and asserts address values to access corresponding rows of the first and second memory modules. Select logic selects between respective columns of the first and second memory modules to retrieve the desired data values according to a predetermined order. A shift network reorders the retrieved data values, if necessary, to place them in the proper order for the processing array. The address decoder provides a select value to the select logic and a shift value to the shift network for each cycle. For purposes of horizontal decimation, the pixel values are organized into an even and an odd group, which groups are stored in the memory buffer in two separate regions separated by an address offset K.

Abstract: A filter selector generates a filter address value to select one of a number of frequency characteristics of a filter to resample a first data signal from a first segment of data in order to generate second sampled data signal in a second segment of data. The filter selector includes an adder which adds a resampling factor to a previous address value to generate a current address value if the previous address value is less than a comparator value and which subtracts the comparator value from the previous address value to generate the current address value if the previous address value is greater than or equal to the comparator value. The current address value is shifted by n bits, where n is an integer, to generate the filter address value.

Abstract: An analog image signal is converted into a digital image signal which is in turn subjected to various types of processing procedures. The resulting digital image data is added to synchronizing data having the same range of data change as that of the image data to generate image data containing the synchronizing data. This image data is then converted into an analog image signal. An offset signal is applied to the analog image signal to adjust the voltage level of the synchronizing signal for obtaining an image signal containing a correct synchronizing signal.

Abstract: As processing a digital information signal (a digital video signal etc), the improvement in the accuracy of the signal process can be made by integrating the time region process and the frequency region process. An input digital video signal is supplied to a DCT circuit 3. The DCT circuit 3 converts the input video digital signal into coefficient data. A categorizing circuit 5 separates a flat component 6a and an impulse component 6b in a frequency region from the input signal. The flat component 6a is supplied to an inverse DCT circuit 7. The inverse DCT circuit 7 converts the input signal into a signal on a time axis. A class categorizing adaptive processing circuit 9 compensates a resolution in a time region. The impulse component 6a is supplied to a gain converting circuit 10. The gain converting circuit 10 compensates the high band in a frequency region. The output signal of the gain converting circuit 10 is supplied to an inverse DCT circuit 11.

Abstract: CRT control apparatus for use in high-resolution graphic display equipment of the type including a frame buffer having storage banks for storing digital signals representing the color intensities of red, green and blue colors of pixels on the CRT screen. The control apparatus is formed in a single MOS integrated-circuit (IC) chip which incorporates three multiplexers for the three 8-bit sets of color digital signals from the frame buffer. The 8-bit outputs of the multiplexers are directed to digital-signal-transformation devices which, in response to each 8-bit signal, produce a corresponding 10-bit signal incorporating the color-intensity information of the original 8-bit signal, and also incorporating a gamma correction factor for the particular intensity represented by the original 8-bit signal. The 10-bit signals are directed to 10-bit DACs, one for each color, to produce corresponding analog control signals for the corresponding electron guns of the CRT.

Abstract: A processor comprises a plurality of parallel channels having an upstream end and a downstream end, Each channel comprises a video data bus for continuously transferring video data from the upstream end to the downstream end, a plurality of modules serially connected along the video data bus and a host computer connected to the downstream end of the plurality of channels for receiving the video data. Each module comprises a crossbar switch, a pixel processing element connected to the crossbar switch, a delay resource connected across the crossbar switch and a microprocessor operably integrated within each module for controlling the operation thereof. The microprocessors of each module are serially connected together for transmitting and undertaking commands. The host computer is also connected to the microprocessor of each module for issuing commands for controlling the operation of the processor.

Abstract: The present invention relates to a method of enhancing a digital color video image comprised of separating a source pixel into individual component parts, for each component part, generating a random number having the same length as the corresponding component part, adding each random number to its corresponding component part to form resultant component parts, and combining the resultant component parts to form a destination pixel.

Abstract: Under one embodiment, a first and a second similarly constituted detector, and an OR gate coupled to the two detectors, are provided to a digital video system. The first detector detects quantization errors of numerically adjacent values in vertically adjacent pixels of a current frame. The second detector detects quantization errors of numerically adjacent values in horizontally adjacent pixels in the current frame. The OR gate is used to determine whether quantization errors of numerically adjacent values are detected in at least one of the two spatial dimensions of pixel adjacency in the current frame. In one variation of this embodiment, a potential quantization error lookup table that supports concurrent lookups for vertically and numerically adjacent quantization error detection as well as horizontally and numerically adjacent quantization error detection is used and shared between the two detectors.

Abstract: A programmable device for storing digital video lines, being of a type intended for use in TV sets with digital frame scan features whereby a video line is sample coded in a digital signal, comprises at least one pair of memories each adapted to contain the code of one video line, and a bank of registers connected in series to one another and to each of the memories, at least one of the registers being fed, at its input terminals, with the digital signal to parallel the samples to be input to the memories.