Abstract: In an embodiment, an amplifier includes first, second, and third stages, and a feedback network. The first stage has a first passband and is configured to generate a first output signal in response to first and second input signals, and the second stage has a second passband that is higher in frequency than the first passband and is configured to generate a second output signal in response to third and fourth input signals. The third stage has a first input node coupled to receive the first output signal, a second input node coupled to receive the second output signal, and an output node. And the feedback network is coupled between the second input node and the output node of the third stage. For example, where the first, second, and third stages are respective operational-transconductance-amplifier stages, such an amplifier may be suitable for low-power applications.

Abstract: A method and apparatus are provided for encoding an information object. The method includes storing the information object in a buffer; generating a sampling set including bits selected from the buffer according to a predetermined rule and bits randomly selected from the buffer; generating control channel data including information on the sampling set; and modulating the sampling set and the control channel data.

Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. A first data track is read to generate a first read signal, the first read signal is sampled to generate first read signal samples, a first data sequence is detected based on the first read signal samples, and the first data sequence is converted into corresponding first expected samples. A second data track adjacent the first data track is read to generate a second read signal, the second read signal is sampled to generate second read signal samples, and a second data sequence is detected based on the second read signal samples and the first expected samples.

Abstract: A method for reading a track of data may include positioning a read head at an initial position relative to the track of data and obtaining initial track signals, filtering the initial track signals, positioning the read head at an initial subsequent position relative to the track of data and obtaining initial subsequent track signals, and filtering the initial subsequent track signals. In an initial equalization, the filtered initial track signals and the filtered initial subsequent track signals are equalized to obtain equalized track signals. The read head is positioned at a further subsequent position relative to the track of data and further subsequent track signals are obtained The further subsequent track signals are filtered. In a subsequent equalization, previously obtained equalized track signals and the filtered further subsequent track signals are equalized. A storage device operating according to the method may have an equalizer in hardware or firmware.

Abstract: A data storage device includes a storage medium on which data is stored in overlapping tracks, and a medium controller that directs storage of data on, and reading of data from, the storage medium, including encoding data being stored and decoding data being read. The decoding includes, when reading a first track, cancelling interference from a second track that overlaps the first track. The data storage device also includes a host controller in communication with the medium controller. The host controller includes memory that stores data decoded, and data to be written, by the medium controller. Communication between the medium controller and the host controller includes signals derived from data on said first and second tracks for facilitating the cancelling. A method of operating a data storage device includes, when reading a first track, facilitating the cancelling by communicating signals derived from the data on the first and second tracks.

Abstract: A disk drive is disclosed comprising a head actuated over a disk. A test pattern is written to the disk and read from the disk to generate a read signal. The read signal is sampled to generate signal samples, the signal samples are filtered with an equalizer filter to generate a first output, and the test pattern is filtered with a target filter to generate a second output. An error signal is generated based on a difference between the first output and the second output. Coefficients of the target filter are adapted in response to the error signal, and after adapting the coefficients of the target filter, a sequence detector is configured based on the coefficients of the target filter.

Abstract: A method and apparatus for reducing noise in a communication signal is provided. The method includes converting raw channel data from the communication signal to a sequence of transition code symbols, each symbol having a plurality of bits, each bit having a position within the symbol. The method also includes sending the bits of each symbol to a plurality of bins, each bin corresponding to the position of each bit within the symbol. For each bin having a number of transitions greater than a number of non-transitions, the method also includes flipping every bit in the bin and setting a corresponding bit in a flip control word to a first value. The method still further includes binary adding the flip control word to each transition code symbol.

Abstract: A disk drive is disclosed comprising a disk and a head actuated radially over the disk, wherein the head generates a read signal. A sampling device samples the read signal to generate a sequence of read signal samples when reading a training data sequence recorded on the disk, and an equalizer comprising a plurality of coefficients equalizes the read signal samples to generate a sequence of equalized samples. A sequence detector detects an estimated data sequence from the equalized samples, wherein the sequence detector operates according to a target response comprising a plurality of target values. Control circuitry adapts the target values by computing error values in response to a difference between expected samples and the equalized samples, computing a gradient in response to a correlation of the training data sequence with the error values, and adjusting at least one of the target values in response to the gradient.

Abstract: A disk controller for a hard disk drive includes a disk formatter interfaced via an NRZ bus to a read channel for the disk. The disk formatter includes an LFSR accumulator coupled to the NRZ bus, as well as an LSFR generator that generates synthetic test data for the disk formatter. Under control of a test flag which signifies a test mode, the LSFR generator generates synthetic test data, which is used by the disk formatter to drive the NRZ bus. The LSFR accumulator accumulates data on the NRZ bus, together with data on servo information and sector information. An interface is provided through which the accumulated information is provided to test equipment, for offline analysis of the accumulated information, so as to confirm proper operation of the disk subsystem and/or to detect failures therein.

Abstract: A technique to perform a guided partial response target search for characterizing a read channel of a disk drive. A target adaptation scheme pre-selects a plurality of targets from a pool of potential targets based on certain criteria and the selected targets are sorted in linear gradient orders. When target adaptation is being performed by comparing the equalizer output with an ideal reconstructed signal, a difference value sets a gradient vector that is used to determine which direction to move along the sorted list of targets to select the next target.

Abstract: An apparatus and associated method are described for use in a disk drive including a disk that that is supported for controlled rotation and for cooperating with a transducer arrangement for accessing the disk in performing a data operation. The disk includes an arrangement of servo track wedge segments for storing servo data such that a set of servo data is periodically available as the disk is rotated in relation to the transducer arrangement and the servo track wedges are separated by an arrangement of user data wedge segments for use in storing user data. Generally, a controller IC and a channel IC are provided. The servo data is transferred from the channel IC to the controller IC using one data protocol and user data is bidirectionally transferred between the channel IC and the controller IC using a different data protocol.

Abstract: An EFM/EFM+ encoder and a method thereof, performing digital sum value (DSV) protection in an Eight-to-Fourteen/Eight-to-Fourteen Plus (EFM/EFM+) encoding system to generate a data frame to be recorded on a recording medium. The method comprises modulating source data to the data frame having a predetermined number of channel bits, determining merging bits and DSV based on the channel bits, and changing the predetermined number of the channel bits in the data frame based on the DSV and the merging bits. The changing the predetermined number of the channel bits comprises inserting or removing a channel bit at the end of the data frame.

Abstract: A digital modulation apparatus capable of generating a modulated code so that binary slice is correctly performed when reproducing is provided. To achieve this, in a digital modulation apparatus (10A), a DSV change amount calculator (15) calculates change amounts (?DSVa, ?DSVb) in DSVs of candidate modulated codes (CODEa, CODEb) generated by a modulated code generator (11). A modulated code determinator (13) compares the change amounts (?DSVa, ?DSVb), and determines that the candidate modulated code having a smaller absolute value should be selected as a modulated code (CODE). A modulated code selector (14) selects one of the candidate modulated codes (CODEa, CODEb) which is determined by the modulated code determinator (13), and outputs the selected code as a modulated code (CODE) for source data (DATA).

Abstract: A recording method for converting m-bit data into n-bit (where n>m) data whose run length is restricted and recording the converted data on a recording medium, the recording method comprising the step of selecting first n-bit data according to an immediately preceded n-bit data, first n-bit data immediately followed thereby, and second n-bit data immediately followed thereby so that the cumulative value of DC components per unit time becomes small.

Abstract: A data storage device such as a disc drive is described that has a controller chip with an integral embedded read/write channel on the chip. The chip includes a built in test capability for testing the controller logic via the device microprocessor and a nonreturn to zero test FIFO and control logic module. The module includes an internal first in/first out buffer (FIFO) that has variable data speeds and is provided on the chip to provide the test capability thereby permitting testing that would otherwise be difficult to perform.

Abstract: A signal sampler digitally samples magnetic signals detected by read head(s) of a magnetic tape drive, and a signal quality system extracts from the digital samples of a format required signal of the magnetic signals, such as a data set separator pattern, an estimated amplitude of write equalization transitions of the format required signal; and compares the extracted estimated amplitude to acceptable amplitude.

Abstract: The DVD recording method is intended to increase the number of cycles allowed for recording on the disk an enormous number of times. This method comprises generating two data streams by using a plurality of code mapping variants prepared for coding input data, quasi-randomly selecting one of the plurality of code mapping variants, if absolute DSVs of the two streams are substantially equal, and converting into recording code sequences. This method prevents deterioration of the disk particularly in the management area and increases the number of cycles allowed for rewriting.

Abstract: Provided is a method, system, and program for storing input groups of uncoded binary data on a storage medium. A plurality of uncoded data blocks in a data stream are received. An encoded data stream is obtained from concatenating successive encoded blocks such that the encoded data stream includes a predetermined bit pattern comprising a plurality of bits. The bit pattern always occurs within a first number of bits and two occurrences of a “1” or “0” occur within a second number of bits. The encoded data blocks are stored on the storage medium.

Abstract: In a code modulating method and a code modulating apparatus, a run length has an encoding rate of ? which is equal to that of (1, 7) modulation, and indicates the number of “0” bits between adjacent ones of “1” bits in the channel bit train. A data bit train is converted into the channel bit train so that the run length has a minimum value 1 and a maximum value 10. Further, upon converting any data bit train, the channel bit train does not include a pattern “1010101010101” in which the run length 1 is continuously repeated six times or more. The channel bit train has a DSV (Digital Sum Value) control bit which selects the “0” bit or “1” bit in accordance with a DSV. The channel bit train obtained by using random data for the data bit train is NRZI converted into a signal. A frequency component of the signal is reduced from a maximum value of the frequency component by 20 dB or less as a power density at a frequency of {fraction (1/10,000)} or less of a channel clock frequency.

Abstract: A programmable write equalization circuit includes a first digital clock that is used as a reference to indicate data rate, a second digital clock used to indicate write equalization quantization, a look-up table used to store waveforms used in equalizing the input from the first digital clock domain to the second digital clock domain, a counter used to indicate the number of bits within the look-up table that are to be used for each translation, a polarity detector used to detect the current state of the input data, a non-return-to-zero (NRZ) filter used to indicate the placement of data transitions and non-transitions, and a software interface including programmable registers to control each one of the parameters within the equalization circuit.

Abstract: Disclosed is a method for satisfying both high reliability and low error rate when in recording and reproducing information by making the average run length of the RLL code for recording a crystal state shorter than that for recording an amorphous state on a recording film, although the consistence of both high reliability and low error rate has been difficult in the case of conventional optical disks.

Abstract: A signal received in a wavelength division multiplexing system is delayed and an exclusive OR logical operation is performed on the received signal and the delayed received signal. Then, the direct current voltage of a selection signal which is a result of the operation is measured to identify the bit-rate of the received signal. When a mixture of various signals having different bit-rates are used over a network in the wavelength division multiplexing system, a receiving terminal can automatically recognize information on the bit-rate of a received optical signal and extract a reference clock signal from the received signal, thereby reproducing the received optical signal without distortion, using the clock signal.

Abstract: How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit.

Abstract: A system and method for correcting interference errors in data encoded on storage media comprising position marks disposed on a storage medium, the position marks being configured to encode a plurality of track addresses and at least four track types. A correction module detects and corrects errors in the track addresses by combining each of the track addresses with one of the track types and then recognizing incorrect addresses. The correction module replaces incorrect addresses with correct addresses using a look-up table, wherein each incorrect address is not identical to one of the correct addresses. The plurality of position marks that encode the track types are also used to generate a position error signal for position correction of a head device.

Abstract: A DSV control bit determining/inserting unit inserts DSV control bits into an input data string and outputs the string including the DSV control bits to a modulation unit which converts the string with basic data length of 2 bits into variable length code with basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table includes substitution codes for limiting the number of consecutive appearances of a minimum run and substitution codes for keeping a run length limit. The conversion table enforces a conversion rule: the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 equals the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

Abstract: A timing recovery system encodes data while impressing recognizable patterns thereon, enabling precise timing during subsequent readback operations. An uncoded binary sequence is encoded using an m/n rate block coded sequence, incorporating a unique predetermined binary bit pattern that occurs with a selected level of frequency. The encoded sequence is stored on the recording medium as a series of flux transitions. To read back the stored data, a read head measures the flux transitions stored on the medium and generates a representative analog waveform. A sampler samples the waveform in accordance with a timing scheme provided by a timing circuit. The timing circuit adjusts the timing of the samples to ensure that the analog waveform is sampled at appropriate times to yield the most accurate results. The timing circuit evaluates two consecutive samples to identify samples associated with features of the analog readback waveform that corresponds to the predetermined bit patterns.

Abstract: The present invention provides for the compression of digital and analog data for storage and transmission. Analog data in the form of an analog signal is converted into a digital signal by an analog-to-digital converter. The digital signal is then converted into an analog signal having an alternating frequency by a first converter processor and an alternating frequency generator according to a predetermined conversion table. To reproduce the original analog signal, the analog signal having an alternating frequency is first converted back into a digital signal by an alternating frequency measurement means connected to a second converter processor, also in accordance with the predetermined conversion table. The digital signal is then converted to the original analog signal by a digital-to-analog converter.

Abstract: In digital signal recording apparatus using I-NRZI modulation for recording, the need for intermittently reading or intermittently writing buffer storage is eliminated by using parallel-bit precoding to generate the channel words that are selected between for recording. The precoders perform preceding on an accelerated basis using ripple-through integration of the alternate successive bits used to form each channel word. Two precoders generate (n+1)-parallel-bit channel words at a channel word rate slower by a factor of (n+1) than the rate of a system clock for the I-NRZI modulation. This leaves additional time during each channel word interval to carry out a decision procedure, which determines which of the channel words generated by the two precoders is to be selected for recording.

Abstract: In order to implement encoding which is proof against noise and distortion, there is provided an encoder for coding a train of input codes characterized in that 3 consecutively transiting consistent codes starting from either an odd-numbered or an even-numbered channel clock pulse of a channel clock signal and all 4 consecutively transiting consistent codes are restricted to produce a train of output codes and the number of produced codes in the train is made even.

Abstract: A data storage device 15 comprises a recording head 35 and a recording media comprising a layer of magnetic material having an anisotropy that is substantially perpendicular to a plane of the layer. The device encoder 80 is adapted to provide an encoded data signal for recording data in encoded bit cells on the magnetic media 30, the encoded data signal comprising a sequence of signal transitions comprising added equalization signal transitions, the equalization signal transitions being added so that a plurality of the encoded bit cells comprises an average magnetization field strength that is substantially null.

Abstract: The invention provides a high-speed interface that transfers user data and other data over a single unified interface between a read channel integrated circuit and another integrated circuit, such as the drive control integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data and other data which speeds up the data transfer. Examples of the other data include read channel settings, read channel performance data, and servo data. A read channel integrated circuit exchanges the user data with a data bus when the disk drive system is reading or writing the user data. The read channel integrated circuit exchanges the other data with the data bus when the disk drive system is reading servo data. The other integrated circuit exchanges the user data with the data bus when the disk drive system is reading or writing the user data.

Abstract: This invention relates to improvements in servo Gray code detection techniques in rotating data storage drives such as hard disk drives, or the like. The detection technique uses a rate ¼ Gray code servo signals equalized to a PR4 target, and a matched filter detector, and can realize a servo Gray code detector having high speed and performance. The Gray code detector (30) has an input (44) for receiving an input signal containing a Gray code that has been equalized to a PR4 target and a circuit (40-42, 46) for processing said input signal to determine a maximum Euclidean distance from zero to a value of the Gray code. The construction of the detector (30) depends upon the particular Gray code that is employed.

Abstract: A frequency comparator for comparing the frequency of a predetermined clock signal with the clock frequency of a non-return-to-zero (NRZ) signal having a detector circuit for detecting a data change of the NRZ signal in an interval of one time period of the clock signal, and a comparator circuit for generating a comparison result only when a data change is detected by the detector. The detector includes a data change circuit for detecting a data change of the NRZ signal and a change position detector for detecting a data change position of the NRZ signal in a time period of the clock signal CLK by taking in the logic of a clock signal and an auxiliary clock signal having the phase delayed 90 degrees from that of the clock signal when a data change of the NRZ signal is detected. The comparator circuit has a setting circuit for setting a reference point for detecting the time period subsequent to the clock signal to generate the comparison result based on the reference point set by the setting circuit.

Abstract: A data symbol sequence detector for choosing data symbol sequences likely to be represented by corresponding sequences of samples received by the detector with these sample sequences formed by sampling data signals obtained from magnetically stored data through a data retrieval channel which asymmetrically affects the magnitudes of the data signals. An expected sample value estimator provides estimated expected magnitude values for a selected set of samples in the sequence, and a magnitude difference determiner is used for obtaining representations of differences between values of the samples in the sequence and the corresponding estimated expected values. These differences representations can be limited in algebraic form.

Abstract: A data recording device such as a hard disk apparatus has an orthogonal coding circuit and a modulation circuit. The orthogonal coding circuit encodes recording data to be recorded to adjacent two tracks as two orthogonal code streams which are included in an Hadamard matrix. The modulation circuit outputs recording signals, which are obtained by modulating the code streams using the NRZI system, to a magnetic head. Reproduction signals read out from a magnetic disk by the magnetic head are decoded as recording data based upon given decoding rules according to the two code streams.

Abstract: A signal recording apparatus for a video instrument using a magnetic recording medium which is capable of more accurately computing the signal to be recorded on the tape by correcting the output signal when affixing "1" or "0" after computing the output signal to which the pilot tone is affixed. In addition, one line block is used on the assumption that "1" or "0" is always affixed to the code word.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems employing a run-length limited (RLL) d=1 channel code which compensates for partial erasure, and a parity channel code for enhancing the operation of a remod/demod sequence detector. During a write operation, after encoding the user data into codewords comprising the RLL d=1 constraint, the parity over one interleave of a block of NRZI bits is computed and two parity bits appended to form a parity codeword. For an even number of "1" bits in the block, the parity bits are set to "00". For an odd number of "1" bits in the block, the parity bits are set to "10" if the codeword ends with a "0" bit and to "01" if the codeword ends with a "1" bit, thereby maintaining the RLL d=1 constraint. Thus, a parity codeword will always comprise an even number of "1" bits (even parity).

Abstract: A magnetic disk drive includes redundant data written at a plurality of out of phase angular locations to reduce the latency and enhance performance during a read operation. The loss of recording capacity is reduced by increasing the data density to achieve the same soft error rate standard required for single recording. Dual recording also allows different recording codes to be used at the duplicated locations to thereby have the more highly stressed code words occur at different locations in the data to further reduce the possibility of an error. The redundant recording can be used in one portion of the media and normal recording used in another media portion to enable selection of the recording technique in accordance with the type of data being stored. The size of the normal and redundant recording portions can be controlled by the format operation and the user of the disk drive can intervene to designate the size of the redundant and normal media recording portions effected during the format operation.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs an EPR4 remod/demod sequence detector. To reduce the complexity of timing recovery, gain control and adaptive equalization, the channel samples are initially equalized into a PR4 partial response so that a simple slicer circuit can generate estimated sample values. The PR4 equalized channel samples are then passed through a 1+D filter to generate EPR4 equalized channel samples which are processed by an EPR4 Viterbi sequence detector to generate a preliminary binary sequence. The preliminary binary sequence is remodulated into an estimated or ideal PR4 sample sequence which is subtracted from the PR4 equalized channel samples to generate an error sample sequence. An error pattern detector processes the error sample sequence to detect the dominant error events associated with the EPR4 Viterbi sequence detector.

Abstract: A data transmission apparatus for transmitting an original data has a converter for converting the original data to sequential data codes. The data code is formed by a combination of HIGH level binary codes and LOW level binary codes. The maximum length of a continuous binary codes of one level, such as HIGH level, in the data codes is limited to T.sub.max, e.g., to 14T, in which T is a unit length representing one binary code, and the minimum length of a continuous binary codes of one level, such as HIGH level, in the data codes is limited to T.sub.min, e.g., 3T. A generator generates a synchronization code. The synchronization code is formed by a combination of HIGH and LOW level binary codes. The synchronization code comprises an identifier having a continuous binary codes of one level, such as HIGH level, with a predetermined length 16T which is 2T greater than T.sub.max. An inserter inserts the synchronization code intermittently in the sequential data codes.

Abstract: Input data is modulated, a two-valued signal regarding a signal of a specific frequency is generated, and a logical arithmetic operation between the modulation data and the two-valued signal is executed. In accordance with the result of the logical arithmetic operation, the specific frequency component in the modulation data is detected. The modulating operation is controlled in accordance with the detection result. As mentioned above, the specific frequency component in the modulation data is detected by the logical arithmetic operation between the modulation data and the two-valued signal. By controlling the modulator on the basis of the detection result, the specific frequency component in the modulation data can be detected by a simple construction. For example, an amount of specific frequency component in the modulation data can be adjusted.

Abstract: In digital signal recording apparatus using I-NRZI modulation for recording, the need for intermittently reading or intermittently writing buffer storage is eliminated by using parallel-bit preceding to generate the channel words that are selected between for recording. The precoders perform precoding on an accelerated basis using ripple-through integration of the alternate successive bits used to form each channel word. Two precoders generate (n+1)-parallel-bit channel words at a channel word rate slower by a factor of (n+1) than the rate of a system clock for the I-NRZI modulation. This leaves additional time during each channel word interval to carry out a decision procedure, which determines which of the channel words generated by the two precoders is to be selected for recording.

Abstract: A data conversion method from m bits of data words into n bits of code words in recording or transmission, in which n is larger than m. A number of bit "0" arranged between one bit "1" and a next bit "1" is restricted to at most 4 in a code string of each code word, and a pair of groups of the n bits of code words corresponding to CDSs (code word digital sum) of two codes +1 and -1 are allowed to correspond to the m bits of data words. One of the two codes +1 and -1 is selectively used according to a DSV (digital sum variation) control signal to convert the m bits of data word into the n bits of code word. A pilot signal formation method using the data conversion method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus, and a rotary magnetic head device for use in a magnetic recording and reproducing apparatus are also disclosed.

Abstract: When modulating by an interleaved NRZI technique by inserting one bit per every m bits of input data series, the frequency characteristics of bit rows varying by the polarity ("0" or "1") of the bit to be inserted are compared, and the bit row closer to the desired frequency characteristic is selected as the output series, so that recording is effected by controlling the frequency characteristics of the digital signal.

Abstract: A digital signal detector for a digital magnetic recording/reproducing device detects corrected signals using a differentiation feature of a recording/reproducing segment of the device, to reduce performance degradation due to signal distortion. The detector includes a precoder for converting an input digital signal into a non-return-to-zero-inverter (NRZI) waveform signal; a recording/reproducing portion for recording the signal output from the predecoder and reproducing the recorded signal; a linear equalizer for compensating the distorted amplitude of the signal reproduced by the recording/reproducing portion; a signal corrector for correcting a signal output from the linear equalizer using a signal correlation process; an integration detector for integrating the signal corrected by the signal corrector; and a predecoder for decoding the signal integrated by the integration detector into its original signal.

Abstract: The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform.

Abstract: A PR4 sampled amplitude read channel is disclosed which employs an NRZI modulator for writing encoded user data directly to a magnetic disc storage medium instead of using a conventional 1/(1+D.sup.2) precoder. This avoids the ambiguous initial state of the precoder and allows the read channel to directly control the magnetic flux transitions written onto the disc. Upon read back, a PR4 sequence detector outputs a preliminary data sequence which is converted back into the NRZI domain and then decoded into an estimated user data sequence.

Abstract: In digital signal recording apparatus using I-NRZI modulation for recording, the need for intermittently reading or intermittently writing buffer storage is eliminated by using parallel-bit precoding to generate the channel words that are selected between for recording. The precoders perform preceding on an accelerated basis using ripple-through integration of the alternate successive bits used to form each channel word. Two precoders generate (n+1)-parallel-bit channel words at a channel word rate slower by a factor of (n+1) than the rate of a system clock for the I-NRZI modulation. This leaves additional time during each channel word interval to carry out a decision procedure, which determines which of the channel words generated by the two precoders is to be selected for recording.

Abstract: The present invention is directed to a decoder circuit that can be operated at higher frequencies of a RLL clock. RLL data input from a disk drive is shifted through a first stage of the decoder circuit by the standard RLL clock. The RLL data is shifted from the first stage through a second stage of the decoder circuit by a modified RLL' clock that operates at a lower frequency than the RLL clock. In a preferred embodiment, RLL' clock operates at one-third the frequency of the RLL clock. The decoding step is accomplished within the period of one clock cycle of the slower RLL' clock, which affords the decoder circuit of the present invention a sufficient amount of time to decode the RLL data from the disk drive into NRZ data for the host. Since RLL' clock used in the decoding step is slower, the RLL clock used to generate RLL' clock and to clock data into the decoder circuit from the disk drive can be operated at a higher frequency than currently possible.