Abstract: A system basis chip is described. The system basis chip comprises a power supply circuit configured to receive an input voltage and generate a plurality of voltages, and a control circuit. Specifically, the power supply circuit is configured to selectively switch on a first and a second voltage of the voltages as a function of a control signal. The control circuit measures a resistance value of an external resistor connected to a terminal and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration indicates that said first voltage should be switched on before said second voltage and a second configuration indicates that said second voltage should be switched on before said first voltage. Accordingly, the control circuit may generate the control signal in order to switch on in sequence the first and the second voltage according to the selected configuration.

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

Abstract: A method and system for maintaining command queue order are disclosed. According to certain embodiments, commands are read from a host, storing command queue IDs in an array that will keep the queue IDs in order. After having the queue IDs stored in the array, the commands are processed in the data storage device (DSD). After processing, the commands are provided to a completion order adjustment module that will order the commands in queue ID order for sequential commands to be returned to the host. In certain embodiments, for a sequential command, other commands of the same sequence are searched for the array and ordered with the sequential command. If a particular command of the sequence is not found, the completion order adjustment module will wait to transfer the sequence until each command of the sequence is found. For commands not part of a sequence, these commands are transferred to the host.

Abstract: An analog signal generating source comprising two or more digital-to-analog converters (DAC) combined to generate one or more frequency components. The analog signal source comprises a first path for generating substantially low frequency signals, the first path comprising a first one of the DACs; and a second path for generating substantially high frequency signals, the second path comprising a second one of the DACs. The analog signal source also comprises a data processor for processing an input signal and providing the processed input signal to the first and second paths; a combining circuit configured to combine outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; and a servo loop configured to use the sensed source signal to adjust as need to maintain the source signal to substantially agree with the input signal.

Abstract: A method of reading servo wedge data from a rotating constant-density magnetic storage medium having a plurality of tracks, where each track is written at a track pattern frequency, the respective track pattern frequencies varying from a lowest frequency at an innermost one of the tracks to a highest frequency at an outermost one of the tracks, includes, for each respective track, determining, based on the pattern frequency of the respective track, a desired sampling position, sampling actual samples of servo wedge data based on a sampling clock used for all tracks, having a sampling frequency at least equal to the track pattern frequency of the outermost track, determining a phase relationship of the desired sampling position to the sampling clock, and, depending on the phase relationship between the sampling position and the sampling clock, interpolating a sample, or omitting interpolation of a sample and squelching the interpolation clock.

Abstract: The present disclosure generally relates to a multi-disk drive comprising a plurality of media surfaces and a plurality of heads, wherein a head of the plurality of heads is configured to be actuated over each surface of the plurality of media surfaces. The multi-disk drive further comprises control circuitry configured to write data to a first media surface of the plurality of media surfaces using a first head of the plurality of heads, and after all of an available memory of the first media surface has been filled, write data to a second media surface of the plurality of media surfaces using a second head of the plurality of heads. The control circuitry is further configured to permanently disable write access to one or more media surfaces of the plurality of media surfaces, while continuing to permit read access to the plurality of media surfaces.

Abstract: Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.

Abstract: A method for designing an enclosure by predicting hard drive disk (HDD) performance in an experimental enclosure, where the enclosure is a modified version of the experimental enclosure. The method includes obtaining, by an HDD performance data generator, an experimental enclosure vibration dataset from a vibration measurement apparatus, obtaining an ideal HDD vibration threshold; making a first comparison between the experimental enclosure vibration dataset and the ideal HDD vibration threshold, calculating, based on the first comparison, an experimental enclosure HDD performance dataset, making a first determination that the experimental enclosure HDD performance dataset exceeds an acceptable threshold, and performing a design action on the experimental enclosure based on the first determination to generate a design of the enclosure.

Abstract: A signal interpolation method is described. The method includes: receiving an analog input signal; digitizing the analog input signal received, thereby obtaining a digitized input signal having samples; determining a crossing of the digitized input signal with respect to a threshold that was set; and interpolating a signal between at least two successive samples, wherein the signal interpolated has two signal portions each having a linear slope, and wherein one of the signal portions crosses the threshold. A measurement instrument is also described.

Abstract: A method according to one embodiment includes measuring a baseline servo band difference (SBD) from a beginning of a tape (BOT) to an end of the tape (EOT), and storing values of the baseline SBD measurements in a memory. A shorter length of the tape that is less than an entire length of the tape is cycled a plurality of times to acclimate the shorter length of the tape. A post cycling SBD of the shorter length of the tape is determined and an acclimation change amount of the shorter length of the tape that is a difference between the baseline SBD of the shorter length and the post cycling SBD of the shorter length is determined. The method further includes adjusting the baseline SBD values based on the determined acclimation change amount.

Abstract: Embodiments provide an interleaver for interleaving an LDPC encoded bit sequence, wherein the interleaver includes a segmentation stage configured to segment the LDPC encoded bit sequence into a plurality of chunks including a first chunk and one or more other chunks, a first interleaver stage, configured to interleave the one or more other chunks or a concatenated version thereof, a second interleaver stage, configured to block wise interleave the first chunk and an interleaved bit sequence provided by the first interleaver stage, to obtain an interleaved version of the LDPC encoded bit sequence, wherein the first chunk consists of bits of a first type being, which are error correcting bits or repeat accumulate bits of the LDPC encoded bit sequence, or are represented, in a Tanner graph representation of the LDPC encoded bit sequence, by variable nodes that include non-random connections to at least two error correcting check nodes.

Abstract: The present disclosure is generally related to a tape drive including a tape head configured to read shingled data tracks on a tape. The tape head comprises a first module head assembly aligned with a second module head assembly. Both the first and second module head assemblies comprises one or more servo heads and a plurality of data heads. Each data head comprises a write head, a first read head aligned with the write head, and a second read head offset from the first read head in both a cross-track direction and a down-track direction. The first read heads and the second read heads are configured to read data from a shingled data track of the tape simultaneously. In some embodiments, the tape head is able to be dynamically tilted in order to tilt the first and second reads heads when reading curved portions of shingled data tracks.

Abstract: Systems and methods are disclosed for hardware-based read sample averaging in a data storage device. In one example, a read channel circuit including a buffer memory is configured to receive a read instruction to read a selected sector, obtain detected sample values for the selected sector, and determine whether the read instruction corresponds to a re-read operation for the selected sector based on determining whether there are stored samples for the selected sector already stored to a locked buffer entry of the buffer memory. When there are stored sample values stored to the locked buffer entry, the example read channel circuit determines the re-read operation is occurring, and performs read sample averaging based on the detected sample values and the stored sample values to produce averaged sample values. Other examples and configurations are also described.

Abstract: An operating method of a memory system may include: searching for, in a memory, target map data corresponding to the read request; loading the target map data from a memory device when the target map data are not searched; compressing the loaded target map data using a predetermined compression ratio depending on an available capacity of the memory; caching the compressed target map data in the memory; parsing the compressed target map data; reading target user data corresponding to the read request from the memory device based on the parsed target map data; and outputting the read target user data.

Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a write element and a first read element. A preamp circuit comprising an interface includes at least a write line associated with the write element of the head and a first read line associated with the first read element of the head. A first read signal is received from the preamp circuit over the first read line during a read operation, and configuration data is transmitted to the preamp circuit over the first read line during a write operation.

Abstract: The present disclosure generally relates to a magnetic media drive employing a magnetic recording head. The magnetic recording head comprises a main pole, an EAMR stack disposed on the main pole, and a trailing shield disposed on the EAMR stack. The EAMR stack comprises a seed layer disposed on the main pole, a spin torque layer disposed on the seed layer, and a spacer layer disposed on the spin torque layer. At least one surface of the spacer layer in contact with the spin torque layer has a smaller or reduced area than the spin torque layer. The at least one surface of the spacer layer in contact with the spin torque layer is recessed from a media facing surface and has a smaller cross-track width than the spin torque layer and a smaller width in the stripe height direction than the spin torque layer.

Abstract: An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal and receive a second signal corresponding to second underlying data. The circuit may determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal, determine estimated decisions corresponding to the second signal based on the second signal, and determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal. The circuit may then generate a remaining signal based on the estimated signal and the second signal, generate an error signal based on the interference component signal and the remaining signal, and adapt one or more parameters of the first channel pulse response shape based on the error signal.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Abstract: The present disclosure describes aspects of codeword interleaving for magnetic storage media. In some aspects, segments of a codeword are spread or interleaved across multiple sectors of magnetic storage media. Data for one or more codewords may be received by a read channel and, for each codeword, a respective indicator is selected or received. The indicator may indicate which partitions of the multiple sectors that segments of one of the codewords are to be written. The data is then encoded to provide the codewords and segments of the codewords are placed in an interleaver based on the respective indicator corresponding to the codeword. The codeword segments are written from the interleaver to partitions of the multiple sectors of the magnetic storage media. By so doing, codewords may be spread across multiple sectors, such that a loss of a few sectors does not prevent readback and decoding of the codewords.

Abstract: A memory system may include: a nonvolatile memory; a volatile memory; and a controller suitable for repeatedly entering and exiting from an automatic exclusive mode for each predetermined size of write data transferred from the host in a start period of the automatic exclusive mode, and allocating the volatile memory exclusively for performing a merge operation on the nonvolatile memory during an entry period of the automatic exclusive mode, the controller may include a command queue for storing plural commands transferred from the host, may use a predetermined operation in the start period of the automatic exclusive mode to calculate a processing time of write commands among the commands stored in the command queue and an entry time of the entry period of the automatic exclusive mode, and may schedule a processing order of the commands stored in the command queue according to the calculation result.

Abstract: Embodiments for optimizing dual-layered data compression in a storage environment. In a data storage system having a primary compressor implemented in a storage controller and a secondary compressor implemented within a drive-enclosure, the primary compressor is selectively used to perform a first one of a plurality of actions on input/output (I/O) data while a second one of the plurality of actions is performed on the I/O data by the secondary compressor, thereby reducing latency and improving an overall compression performance while processing the I/O data.

Abstract: Zone self-servo write (SSW) technology is disclosed that leverages two clock signals synchronized in parallel to transition between zones to write servo patterns at different frequencies while minimizing error rate despite the different frequencies. Two separate clock signals (“clocks”) are used to locate and lock to different reference spirals. By updating both clocks in parallel instead of in series, error rate for writing while stepping up frequency across zones is reduced.

Abstract: An apparatus according to one embodiment includes a controller configured to control writing operations to a magnetic recording tape. The apparatus further includes logic integrated with and/or executable by the controller for causing the controller to write user data to the magnetic recording tape in a user data area of the magnetic recording tape. Furthermore, the logic is integrated with and/or executable by the controller for causing the controller to create a housekeeping data set (HKDS) that includes location information for the user data written in the user data area, and write several copies of the HKDS in a non-user data area of the magnetic recording tape.

Abstract: An operating method of a memory system may include: searching for, in a memory, target map data corresponding to the read request; loading the target map data from a memory device when the target map data are not searched; compressing the loaded target map data using a predetermined compression ratio depending on an available capacity of the memory; caching the compressed target map data in the memory; parsing the compressed target map data; reading target user data corresponding to the read request from the memory device based on the parsed target map data; and outputting the read target user data.

Abstract: A method includes moving a heat-assisted magnetic recording (HAMR) slider relative to a magnetic recording medium. The slider comprises a writer, a writer heater, and a near-field transducer (NFT). For each of a plurality of different head-to media spacings a test tone is written to a track of the medium, the test tone is read and a Discrete Fourier Transform (DFT) of an amplitude of the read test tone is captured. A first DFT curve is generated at a beginning of writing the test tones. A second DFT curve is generated at a saturated state of writing the test tones. An amount of horizontal shift between the first and second DFT curves is computed. The amount of horizontal shift corresponding to writer heater power required to compensate for NFT clearance offset due to laser induced writer protrusion.

Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader so that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.

Abstract: Embodiments for optimizing dual-layered data compression in a storage environment. In a data storage system having a primary compressor and a secondary compressor, the primary compressor is selectively used to perform a first one of a plurality of actions on Input/Output (I/O) data while a second one of the plurality of actions is performed on the I/O data by the secondary compressor, thereby reducing latency and improving an overall compression performance while processing the I/O data.

Abstract: A signal transmission circuit includes a first photocoupler to which a transmission signal is input, an edge detection circuit which is disposed in a primary side of the first photocoupler, the edge detection circuit being configured to detect a rising edge and a falling edge of the transmission signal, and an edge demodulation circuit which is disposed in a secondary side of the first photocoupler, the demodulation circuit being configured to demodulate the transmission signal by using only one of the rising edge and the falling edge of an edge detection signal output from the edge detection circuit via the first photocoupler.

Abstract: For efficient centralized stream initiation and retry control in a computing environment, using a centralized data streams management module for both managing when data streams should be opened and sent from a source location to a destination and for determining when to reattempt opening data streams sent from the source location to the destination after an nth number of consecutive failed attempts using an incrementing time calculation. The incrementing time calculation computes a dynamically calculated time period.

Abstract: A controller includes a memory suitable for storing valid data of first data in a first data region and storing second data in a second data region, wherein the first data includes the valid data and dummy data; a translation unit suitable for performing a first translation operation of changing the first data to the valid data by eliminating the dummy data from the first data, performing a second translation operation of changing the valid data to the first data by adding the dummy data to the valid data, and exchanging the valid data with the memory; and a processor suitable for exchanging the first data with the translation unit, and exchanging the second data with the memory.

Abstract: Repeatable distributed pseudorandom number generation is disclosed. For example, a system has a plurality of pseudorandom number generators (“PRNGs”) including a first and second PRNGs and a randomization engine including a seed engine configured to control the plurality of PRNGs by executing to generate a plurality of seed values equal in quantity to the plurality of PRNGs, including first and second seed values. The first seed value is assigned to the first PRNG and the second seed value to the second PRNG. A first pseudorandom number (“PRN”) set is received from the first PRNG and a second PRN set from the second PRNG. A plurality of PRN sets from the plurality of PRNGs is combined into a combined number set.

Abstract: Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.

Abstract: An apparatus according to one embodiment includes a hardware based controller that is configured to perform operations. The operations include performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude is measured of each of the signals after the anti-aliasing filtering. Moreover, the operations include determining whether the measured amplitudes of the signals are within a predefined range. Anti-aliasing settings used during the anti-aliasing filtering are stored in response to a determination that the amplitudes of the signals are within the predefined range. The anti-aliasing settings are changed in response to a determination that the amplitudes of the signals are outside the predefined range.

Abstract: A method for writing data in a buffer to a magnetic recording tape includes identifying a size of an unused area of the magnetic recording tape based on a current writing position on the magnetic recording tape. An upper limit of a capacity for data that can be stored in the buffer is determined based on the size of the unused area. The predetermined data is stored, according to a command for storing predetermined data in the buffer, in the buffer on condition that the capacity for data in the buffer does not exceed the upper limit.

Abstract: A method includes moving a heat-assisted magnetic recording (HAMR) slider relative to a magnetic recording medium. The slider comprises a writer, a writer heater, and a near-field transducer (NFT). For each of a plurality of different head-to media spacings a test tone is written to a track of the medium, the test tone is read and a Discrete Fourier Transform (DFT) of an amplitude of the read test tone is captured. A first DFT curve is generated at a beginning of writing the test tones. A second DFT curve is generated at a saturated state of writing the test tones. An amount of horizontal shift between the first and second DFT curves is computed. The amount of horizontal shift corresponding to writer heater power required to compensate for NFT clearance offset due to laser induced writer protrusion.

Abstract: A method and nodes for wireless timing synchronization of a target node and a source node. In some embodiments, a request is sent to a source node for time synchronizing the target node with the source node. A first time, T1, indicative of time of transmission of a first radio signal from the source node to the target node is determined. A second time, T2, indicative of time of receipt of the first radio signal at the target node is determined. A third time, T3, indicative of time of transmission of a second radio signal from the target node to the source node is determined. A fourth time, T4, indicative of time of receipt of the second radio signal at the source node is determined. A clock offset based on T1, T2, T3 and T4 for use in time synchronizing the target node with the source node is determined.

Abstract: First and second tracks of a magnetic recording medium are read simultaneously via a first reader that provides a first signal based on detecting a total perpendicular field of the first and second tracks. The first and second tracks are read simultaneously via a second reader that provides a second signal based on detecting a total longitudinal field of the first and second tracks. Data is detected from the first and second signals.

Abstract: An audio signal (X) is represented by a bitstream (B) segmented into frames. An audio processing system (500) comprises a buffer (510) and a decoding section (520). The buffer joins sets of audio data (D1; D2, . . . , DN) carried by N respective frames (F1, F2, . . . , FN) into one decodable set of audio data (D) corresponding to a first frame rate and to a first number of samples of the audio signal per frame. The frames have a second frame rate corresponding to a second number of samples of the audio signal per frame. The first number of samples is N times the second number of samples. The decoding section decodes the decodable set of audio data into a segment of the audio signal by at least employing signal synthesis, based on the decodable set of audio data, with a stride corresponding to the first number of samples of the audio signal.

Abstract: A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.

Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

Abstract: According to one embodiment, a storage device includes a detector, a demodulator, a controller, and a recorder. When a user data item is split data including first data being at least part of a first code word and second data being at least part of a second code word, the controller sets a start position of the second data for forced search of the second code word on the basis of the position of a sync mark recorded in the recorder when the forced search of the first code word has succeeded.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for parity storage management. A system includes a plurality of storage elements. A system includes a controller that selects a parity storage element from a plurality of storage elements. A parity storage element has an error rate higher than other elements of a plurality of storage elements, and the parity storage element stores parity data for the plurality of storage elements.

Abstract: According to one embodiment, a magnetic disk device including a disk, a head which reads data from the disk, a memory which records data, and a controller which includes a table, and records, at a first time point at which a read gate is open, a first area number of a first area of the table in which first information related to first data is recorded, a first serial number of the first data added when the read gate is open, and a first count value of the first data, in the first area.

Abstract: First tracks of a disk are read via a first read transducer. The first read transducer has a first crosstrack width and a first shield-to-shield spacing that are optimized to read a first track width and a first linear bit density of the first tracks. Second tracks interlaced between the first tracks are read via a second read transducer. The second read transducer has a second crosstrack width different from the first crosstrack width and second shield-to-shield spacing different than the first shield-to-shield spacing. The second crosstrack width and the second shield-to-shield spacing are optimized to read a second track width different from the first track width and a second linear bit density different from the first linear bit density.

Abstract: A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.

Abstract: The present disclosure relates to a method and apparatus for processing of multi-dimensional readback signal from magnetic recording or optical, physical data recording so as to reduce/control Inter Symbol Interference (ISI) and noise within acceptable limits. The method is based on Partial Response Maximum Likelihood (PRML) detection and takes care of time varying channel conditions. In an embodiment, the filter coefficients of both the equalizer and the partial response (PR) target are jointly adapted to account for the channel condition for both separable and non-separable targets thus reducing signal detection complexity. In an aspect, the disclosure provides an apparatus that incorporates an adaptation engine along with the equalizer and the PR target that updates filter coefficients of both the equalizer and the PR target following the formulated mathematical equations.

Abstract: This disclosure relates to a memory device that includes at least one magnetic track on a substrate, wherein the at least one magnetic track comprises one or more magnetic domains. Contacts can be disposed on the at least one magnetic track according to a predetermined arrangement to form a plurality of bitcells on the at least one magnetic track, wherein each one of the plurality of bitcells is configured to store at least one magnetic domain. The device can include a timing circuit connected to the contacts, with the timing circuit being configured to apply to the contacts multiple phases of electric currents according to a predetermined timing sequence to cause the at least one magnetic domain to shift from the each one of the plurality of bitcells to an adjacent one of the plurality of bitcells on the at least one magnetic track.

Abstract: Switched memristor analog tuning employs a switch-selectable programmed resistance to tune a resistance-tunable analog circuit. A plurality of switched memristors is to provide the switch-selectable programmed resistance. The resistance-tunable analog circuit is connected to the plurality of switched memristors. The switch-selectable programmed resistance is to tune an analog attribute of the resistance-tunable analog circuit.

Abstract: First and second servo control processors are coupled to respective first and second actuators that independently position first and second heads over one or more disks of a data storage drive. The first and second servo control processors are further coupled to first and second low-latency ports. First and second unidirectional buses couple the first and second low-latency ports. The first and second unidirectional busses are operable to isochronously exchange servo positioning data between the first and second servo control processors. The first and second servo control processors each use the servo positioning data to compensate for movement caused by another of the first and second servo control processors.

Abstract: A drive circuit of a light emitting element, the drive circuit includes: an input terminal configured to receive an input signal; an output terminal configured to output a signal based on the input signal as a drive signal to the light emitting element; and a main body circuit configured to generate the drive signal by carrying out timing correction to reduce a difference from a standard delay value for rising or falling of a plurality of signal patterns of the input signal regarding a timing of rising of a first signal subsequent to a first signal pattern in the plurality of signal patterns or a timing of falling of a second signal subsequent to a second signal pattern in the plurality of signal patterns.