General Processing Of A Digital Signal Patents (Class 360/39)
  • Patent number: 10832716
    Abstract: Zone self-servo write (SSW) technology is disclosed that leverages two clock signals synchronized in parallel to transition between zones to write servo patterns at different frequencies while minimizing error rate despite the different frequencies. Two separate clock signals (“clocks”) are used to locate and lock to different reference spirals. By updating both clocks in parallel instead of in series, error rate for writing while stepping up frequency across zones is reduced.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 10, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventor: Supaket Katchmart
  • Patent number: 10831412
    Abstract: Embodiments for optimizing dual-layered data compression in a storage environment. In a data storage system having a primary compressor implemented in a storage controller and a secondary compressor implemented within a drive-enclosure, the primary compressor is selectively used to perform a first one of a plurality of actions on input/output (I/O) data while a second one of the plurality of actions is performed on the I/O data by the secondary compressor, thereby reducing latency and improving an overall compression performance while processing the I/O data.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Danny Harnik, Sergey Marenkov, Yosef Shatsky
  • Patent number: 10818314
    Abstract: An apparatus according to one embodiment includes a controller configured to control writing operations to a magnetic recording tape. The apparatus further includes logic integrated with and/or executable by the controller for causing the controller to write user data to the magnetic recording tape in a user data area of the magnetic recording tape. Furthermore, the logic is integrated with and/or executable by the controller for causing the controller to create a housekeeping data set (HKDS) that includes location information for the user data written in the user data area, and write several copies of the HKDS in a non-user data area of the magnetic recording tape.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 27, 2020
    Assignee: International Business Machines Corporation
    Inventors: Tsuyoshi Miyamura, Setsuko Masuda
  • Patent number: 10698811
    Abstract: An operating method of a memory system may include: searching for, in a memory, target map data corresponding to the read request; loading the target map data from a memory device when the target map data are not searched; compressing the loaded target map data using a predetermined compression ratio depending on an available capacity of the memory; caching the compressed target map data in the memory; parsing the compressed target map data; reading target user data corresponding to the read request from the memory device based on the parsed target map data; and outputting the read target user data.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Ick Cho
  • Patent number: 10607648
    Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader so that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 31, 2020
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wu, Marcus Marrow, Jason Bellorado
  • Patent number: 10607646
    Abstract: A method includes moving a heat-assisted magnetic recording (HAMR) slider relative to a magnetic recording medium. The slider comprises a writer, a writer heater, and a near-field transducer (NFT). For each of a plurality of different head-to media spacings a test tone is written to a track of the medium, the test tone is read and a Discrete Fourier Transform (DFT) of an amplitude of the read test tone is captured. A first DFT curve is generated at a beginning of writing the test tones. A second DFT curve is generated at a saturated state of writing the test tones. An amount of horizontal shift between the first and second DFT curves is computed. The amount of horizontal shift corresponding to writer heater power required to compensate for NFT clearance offset due to laser induced writer protrusion.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 31, 2020
    Assignee: Seagate Technology LLC
    Inventors: Zhen Wei, Hua Liu
  • Patent number: 10592170
    Abstract: Embodiments for optimizing dual-layered data compression in a storage environment. In a data storage system having a primary compressor and a secondary compressor, the primary compressor is selectively used to perform a first one of a plurality of actions on Input/Output (I/O) data while a second one of the plurality of actions is performed on the I/O data by the secondary compressor, thereby reducing latency and improving an overall compression performance while processing the I/O data.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Danny Harnik, Sergey Marenkov, Yosef Shatsky
  • Patent number: 10558202
    Abstract: A signal transmission circuit includes a first photocoupler to which a transmission signal is input, an edge detection circuit which is disposed in a primary side of the first photocoupler, the edge detection circuit being configured to detect a rising edge and a falling edge of the transmission signal, and an edge demodulation circuit which is disposed in a secondary side of the first photocoupler, the demodulation circuit being configured to demodulate the transmission signal by using only one of the rising edge and the falling edge of an edge detection signal output from the edge detection circuit via the first photocoupler.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: February 11, 2020
    Assignee: Yokogawa Electric Corporation
    Inventors: Tatsuro Endo, Masami Wada
  • Patent number: 10536565
    Abstract: For efficient centralized stream initiation and retry control in a computing environment, using a centralized data streams management module for both managing when data streams should be opened and sent from a source location to a destination and for determining when to reattempt opening data streams sent from the source location to the destination after an nth number of consecutive failed attempts using an incrementing time calculation. The incrementing time calculation computes a dynamically calculated time period.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yariv Bachar, Ron Edelstein, Alon Horowitz, Oded Sonin
  • Patent number: 10534704
    Abstract: A controller includes a memory suitable for storing valid data of first data in a first data region and storing second data in a second data region, wherein the first data includes the valid data and dummy data; a translation unit suitable for performing a first translation operation of changing the first data to the valid data by eliminating the dummy data from the first data, performing a second translation operation of changing the valid data to the first data by adding the dummy data to the valid data, and exchanging the valid data with the memory; and a processor suitable for exchanging the first data with the translation unit, and exchanging the second data with the memory.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Byeong-Gyu Park, Kyu-Min Lee
  • Patent number: 10474432
    Abstract: Repeatable distributed pseudorandom number generation is disclosed. For example, a system has a plurality of pseudorandom number generators (“PRNGs”) including a first and second PRNGs and a randomization engine including a seed engine configured to control the plurality of PRNGs by executing to generate a plurality of seed values equal in quantity to the plurality of PRNGs, including first and second seed values. The first seed value is assigned to the first PRNG and the second seed value to the second PRNG. A first pseudorandom number (“PRN”) set is received from the first PRNG and a second PRN set from the second PRNG. A plurality of PRN sets from the plurality of PRNGs is combined into a combined number set.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: November 12, 2019
    Assignee: RED HAT, INC.
    Inventors: William Christian Benton, Erik Jordan Erlandson
  • Patent number: 10467367
    Abstract: Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 5, 2019
    Assignee: CHRONOS TECH LLC
    Inventors: Stefano Giaconi, Giacomo Rinaldi
  • Patent number: 10418061
    Abstract: An apparatus according to one embodiment includes a hardware based controller that is configured to perform operations. The operations include performing anti-aliasing filtering on each of a plurality of signals, each signal having a frequency that is a different fraction of a frequency of a data read clock. An amplitude is measured of each of the signals after the anti-aliasing filtering. Moreover, the operations include determining whether the measured amplitudes of the signals are within a predefined range. Anti-aliasing settings used during the anti-aliasing filtering are stored in response to a determination that the amplitudes of the signals are within the predefined range. The anti-aliasing settings are changed in response to a determination that the amplitudes of the signals are outside the predefined range.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Larry L. Tretter, Matthew M. Viens
  • Patent number: 10353624
    Abstract: A method for writing data in a buffer to a magnetic recording tape includes identifying a size of an unused area of the magnetic recording tape based on a current writing position on the magnetic recording tape. An upper limit of a capacity for data that can be stored in the buffer is determined based on the size of the unused area. The predetermined data is stored, according to a command for storing predetermined data in the buffer, in the buffer on condition that the capacity for data in the buffer does not exceed the upper limit.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Yutaka Oishi
  • Patent number: 10321424
    Abstract: A method and nodes for wireless timing synchronization of a target node and a source node. In some embodiments, a request is sent to a source node for time synchronizing the target node with the source node. A first time, T1, indicative of time of transmission of a first radio signal from the source node to the target node is determined. A second time, T2, indicative of time of receipt of the first radio signal at the target node is determined. A third time, T3, indicative of time of transmission of a second radio signal from the target node to the source node is determined. A fourth time, T4, indicative of time of receipt of the second radio signal at the source node is determined. A clock offset based on T1, T2, T3 and T4 for use in time synchronizing the target node with the source node is determined.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 11, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Chunhui Zhang, Angelo Centonza, Garry Irvine, Mikael Olofsson, Magnus Sandgren
  • Patent number: 10319400
    Abstract: A method includes moving a heat-assisted magnetic recording (HAMR) slider relative to a magnetic recording medium. The slider comprises a writer, a writer heater, and a near-field transducer (NFT). For each of a plurality of different head-to media spacings a test tone is written to a track of the medium, the test tone is read and a Discrete Fourier Transform (DFT) of an amplitude of the read test tone is captured. A first DFT curve is generated at a beginning of writing the test tones. A second DFT curve is generated at a saturated state of writing the test tones. An amount of horizontal shift between the first and second DFT curves is computed. The amount of horizontal shift corresponding to writer heater power required to compensate for NFT clearance offset due to laser induced writer protrusion.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 11, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhen Wei, Hua Liu
  • Patent number: 10311897
    Abstract: First and second tracks of a magnetic recording medium are read simultaneously via a first reader that provides a first signal based on detecting a total perpendicular field of the first and second tracks. The first and second tracks are read simultaneously via a second reader that provides a second signal based on detecting a total longitudinal field of the first and second tracks. Data is detected from the first and second signals.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 4, 2019
    Assignee: Seagate Technology LLC
    Inventors: Walter R. Eppler, Mehmet Fatih Erden, Stephanie Hernandez
  • Patent number: 10304471
    Abstract: An audio signal (X) is represented by a bitstream (B) segmented into frames. An audio processing system (500) comprises a buffer (510) and a decoding section (520). The buffer joins sets of audio data (D1; D2, . . . , DN) carried by N respective frames (F1, F2, . . . , FN) into one decodable set of audio data (D) corresponding to a first frame rate and to a first number of samples of the audio signal per frame. The frames have a second frame rate corresponding to a second number of samples of the audio signal per frame. The first number of samples is N times the second number of samples. The decoding section decodes the decodable set of audio data into a segment of the audio signal by at least employing signal synthesis, based on the decodable set of audio data, with a stride corresponding to the first number of samples of the audio signal.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: May 28, 2019
    Assignee: Dolby International AB
    Inventors: Kristofer Kjoerling, Alexander Groeschel, Heiko Purnhagen, Holger Hoerich, Kurt Krauss
  • Patent number: 10270445
    Abstract: A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kallol Mazumder
  • Patent number: 10157637
    Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: December 18, 2018
    Assignee: Seagate Technology LLC
    Inventors: Marcus Marrow, Jason Bellorado, Zheng Wu
  • Patent number: 10108470
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for parity storage management. A system includes a plurality of storage elements. A system includes a controller that selects a parity storage element from a plurality of storage elements. A parity storage element has an error rate higher than other elements of a plurality of storage elements, and the parity storage element stores parity data for the plurality of storage elements.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Gulzar A. Kathawala, Shuenghee Park, Jingfeng Yuan, Mark Dancho
  • Patent number: 10109314
    Abstract: According to one embodiment, a storage device includes a detector, a demodulator, a controller, and a recorder. When a user data item is split data including first data being at least part of a first code word and second data being at least part of a second code word, the controller sets a start position of the second data for forced search of the second code word on the basis of the position of a sync mark recorded in the recorder when the forced search of the first code word has succeeded.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 23, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Manabu Kobayashi
  • Patent number: 10102869
    Abstract: According to one embodiment, a magnetic disk device including a disk, a head which reads data from the disk, a memory which records data, and a controller which includes a table, and records, at a first time point at which a read gate is open, a first area number of a first area of the table in which first information related to first data is recorded, a first serial number of the first data added when the read gate is open, and a first count value of the first data, in the first area.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 16, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kazuya Takada, Kenji Yoshida
  • Patent number: 10068597
    Abstract: First tracks of a disk are read via a first read transducer. The first read transducer has a first crosstrack width and a first shield-to-shield spacing that are optimized to read a first track width and a first linear bit density of the first tracks. Second tracks interlaced between the first tracks are read via a second read transducer. The second read transducer has a second crosstrack width different from the first crosstrack width and second shield-to-shield spacing different than the first shield-to-shield spacing. The second crosstrack width and the second shield-to-shield spacing are optimized to read a second track width different from the first track width and a second linear bit density different from the first linear bit density.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 4, 2018
    Assignee: Seagate Technology LLC
    Inventors: Jason Charles Jury, Steven Douglas Granz
  • Patent number: 10063234
    Abstract: A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kallol Mazumder
  • Patent number: 10026431
    Abstract: This disclosure relates to a memory device that includes at least one magnetic track on a substrate, wherein the at least one magnetic track comprises one or more magnetic domains. Contacts can be disposed on the at least one magnetic track according to a predetermined arrangement to form a plurality of bitcells on the at least one magnetic track, wherein each one of the plurality of bitcells is configured to store at least one magnetic domain. The device can include a timing circuit connected to the contacts, with the timing circuit being configured to apply to the contacts multiple phases of electric currents according to a predetermined timing sequence to cause the at least one magnetic domain to shift from the each one of the plurality of bitcells to an adjacent one of the plurality of bitcells on the at least one magnetic track.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 17, 2018
    Assignee: Carnegie Mellon University
    Inventors: David M. Bromberg, Lawrence Pileggi, Jian-Gang Zhu
  • Patent number: 10026474
    Abstract: Switched memristor analog tuning employs a switch-selectable programmed resistance to tune a resistance-tunable analog circuit. A plurality of switched memristors is to provide the switch-selectable programmed resistance. The resistance-tunable analog circuit is connected to the plurality of switched memristors. The switch-selectable programmed resistance is to tune an analog attribute of the resistance-tunable analog circuit.
    Type: Grant
    Filed: April 26, 2014
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Brent Buchanan
  • Patent number: 10026441
    Abstract: The present disclosure relates to a method and apparatus for processing of multi-dimensional readback signal from magnetic recording or optical, physical data recording so as to reduce/control Inter Symbol Interference (ISI) and noise within acceptable limits. The method is based on Partial Response Maximum Likelihood (PRML) detection and takes care of time varying channel conditions. In an embodiment, the filter coefficients of both the equalizer and the partial response (PR) target are jointly adapted to account for the channel condition for both separable and non-separable targets thus reducing signal detection complexity. In an aspect, the disclosure provides an apparatus that incorporates an adaptation engine along with the equalizer and the PR target that updates filter coefficients of both the equalizer and the PR target following the formulated mathematical equations.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 17, 2018
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Shayan Srinivasa Garani, Chaitanya Kumar Matcha, Arnab Dey
  • Patent number: 10020012
    Abstract: First and second servo control processors are coupled to respective first and second actuators that independently position first and second heads over one or more disks of a data storage drive. The first and second servo control processors are further coupled to first and second low-latency ports. First and second unidirectional buses couple the first and second low-latency ports. The first and second unidirectional busses are operable to isochronously exchange servo positioning data between the first and second servo control processors. The first and second servo control processors each use the servo positioning data to compensate for movement caused by another of the first and second servo control processors.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 10, 2018
    Assignee: Seagate Technology LLC
    Inventors: Aaron P. Weyer, Bruce Douglas Buch, Kyaw Sin Maung, Jon D. Trantham, Nicholas Paul Mati
  • Patent number: 9979155
    Abstract: A drive circuit of a light emitting element, the drive circuit includes: an input terminal configured to receive an input signal; an output terminal configured to output a signal based on the input signal as a drive signal to the light emitting element; and a main body circuit configured to generate the drive signal by carrying out timing correction to reduce a difference from a standard delay value for rising or falling of a plurality of signal patterns of the input signal regarding a timing of rising of a first signal subsequent to a first signal pattern in the plurality of signal patterns or a timing of falling of a second signal subsequent to a second signal pattern in the plurality of signal patterns.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: May 22, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yukito Tsunoda
  • Patent number: 9899053
    Abstract: Method and apparatus for data security in a data storage device. In some embodiments, a first version of firmware is installed in a memory of the device. The firmware is used by a programmable processor to control accesses to a rotatable data recording medium on which is written pre-recorded servo positioning data used to position a data transducer. A newer, second version of the firmwave is subsequently installed in the memory to replace the first version of firmware. The second version of the firmware includes an instruction to corrupt a selected portion of the servo positioning data on the medium in order to authenticate the second version of the firmware. During a subsequent initialization of the device, host access is granted based on detection of the corruption of the selected portion of the servo positioning data.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: February 20, 2018
    Assignee: Seagate Technology LLC
    Inventors: Leroy L. Leach, Todd D. Baumann
  • Patent number: 9899056
    Abstract: A computer-implemented method, according to one embodiment, includes, performing anti-aliasing filtering on each of a plurality of symmetrical square wave signals, each symmetrical square wave signal having a frequency that is a different fraction of a frequency of a data read clock. The filtered symmetrical square wave signals are passed through a band pass filter. An amplitude of each of the symmetrical square wave signals is measured after the band pass filtering. In response to the amplitudes of the symmetrical square wave signals being within a predefined range, anti-aliasing settings used during the anti-aliasing filtering are stored. In response to the amplitudes of the symmetrical square wave signals being outside the predefined range, the anti-aliasing settings are changed.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Larry L. Tretter, Matthew M. Viens
  • Patent number: 9886970
    Abstract: In certain embodiments, an apparatus may comprise a first output driver connected to a first output via a first trace and a second output driver connected to a second output via a second trace. The first output driver may be configured to output a first drive signal to the first output to drive the first output and the first drive signal may cause first induced noise in the second trace. Further, the second output driver may be configured to output a second drive signal based on the first drive signal where the second drive signal may reduce the magnitude of the first induced noise at the second output.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 6, 2018
    Assignee: Seagate Technology LLC
    Inventors: Todd Michael Lammers, JianHua Xue, Javier I Guzman, Andrew Thomas Jaeb, Bruce Douglas Buch
  • Patent number: 9882577
    Abstract: There is disclosed herein charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 30, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Ian Juso Dedic, Prabhu Ashwin Harold Rebello, John James Danson
  • Patent number: 9858962
    Abstract: According to one embodiment, there is provided a disk apparatus including a disk medium and a controller. The disk medium is able to store a signal with three levels in a track. The track includes a first subtrack and a second subtract. The second subtrack is adjacent to the first subtract. The controller performs a first operation based on a selected level among the three levels, a first bit written in the first subtract corresponding to the selected level, and a second bit written in the second subtrack corresponding to the selected level. The first operation is an operation to correct displacement between a write position of a third bit in the first subtrack and a write position of a fourth bit in the second subtrack in a circumferential direction of the disk medium.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 2, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomokazu Okubo
  • Patent number: 9841916
    Abstract: A memory system includes a plurality of channels; a plurality of semiconductor memory devices connected to the channels; and a controller that controls the semiconductor memory devices through the channels, wherein the controller writes program data in a first semiconductor memory device of the plurality of semiconductor memory devices, and wherein, when the writing of the program data fails, the program data is temporarily stored in a page buffer unit of a second semiconductor memory device of the plurality of semiconductor memory devices connected to a channel other than the channel corresponding to the first semiconductor memory device.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: December 12, 2017
    Assignee: SK Hynix Inc.
    Inventor: Sung Yeob Cho
  • Patent number: 9824703
    Abstract: According to one embodiment, a magnetic recording and reproducing device includes a magnetic recording medium, a magnetic head, and a processor. The magnetic head includes a first reproducing element portion and a second reproducing element portion. The processor is configured to acquire a first signal and a second signal, and to output an output signal according to either one of the first signal and the second signal. The first signal is obtained by reproducing information recorded on a first recording region by the first reproducing element portion. The second signal is obtained by reproducing the information recorded on the first recording region by the second reproducing element portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuya Sugawara, Tomoyuki Maeda, Kenichiro Yamada
  • Patent number: 9823987
    Abstract: Implementations disclosed herein provide a method comprising iteratively reading data from a failing media sector prior to a an error minimization operation, analyzing read data at each iteration using an error minimization operation to determine sections of read data as good data, storing the good data in a buffer during each iteration, and using the good data as input for the read data during a subsequent error retry operation. In another implementation, the method further comprises comparing new read data with stored good data in the buffer, and replacing the stored good data with the new read data if the new read data has a higher quality than the stored good data.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: November 21, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Mingyeong Son, Seungyoul Jeong, Seokhun Jeon
  • Patent number: 9818445
    Abstract: Implementations described and claimed herein includes a storage device comprising a plurality of readers, including a first subset of readers configured to read a first subset of tracks and a second subset of readers configured to read a second subset of tracks, the first subset of tracks being wider than the second subset of tracks. In another implementation, the readers in the first subset of readers are wider than the readers in the second subset of readers. The wider readers may be configured to recover servo information and the narrow readers may be configured to recover data information. The storage devices may include two-dimensional magnetic recording, conventional perpendicular magnetic recording, shingled magnetic recording, multi-sensor magnetic recording, and interlaced magnetic recording.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: November 14, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Wenzhong Zhu, Mehmet F. Erden, Kenneth A. Haapala, Wei Tian, Edward Gage
  • Patent number: 9786319
    Abstract: This disclosure describes codes and techniques for magnetic recording. The coding schemes decrease bit error rates by decreasing total transitions in the encoded binary data compared to conventional codes. Additionally, instead of relying on a single coding scheme, an encoder and decoder are configured to switch between different coding schemes. By so doing, a variety of the coding schemes allows the encoded binary data to have a smaller bit error rate than a single coding scheme and have a maximum run-length less than or equal to a maximum run-length limitation of a magnetic disk.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 10, 2017
    Assignee: Marvell International Ltd.
    Inventors: Seyed Mehrdad Khatami, Gregory Burd, Byung-Hak Kim
  • Patent number: 9747161
    Abstract: The invention provides a signal processing device, including: an extraction section that extracts, from an input digital signal, a decoding target signal at an extraction timing that has been determined as a timing for extracting the decoding target signal; a decoding section that decodes the decoding target signal by estimating, by a maximum likelihood decoding, a candidate for a decoding result of the decoding target signal extracted by the extraction section and detecting a maximum likelihood decoding result; and an adjustment section that adjusts the extraction timing using a likelihood of the candidate for the decoding result estimated by the decoding section.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 29, 2017
    Assignee: FUJIFILM CORPORATION
    Inventors: Atsushi Musha, Osamu Shimizu
  • Patent number: 9733859
    Abstract: A method, computer program product, and system for dividing a file and writing the file to a plurality of tapes in a tape library system comprising a plurality of tape apparatuses. A request to write a file to a plurality of tapes is received. The file comprises data. A number of available tapes is predicted with respect to a number of drives available at a time when the file requested to be written is written to the plurality of tapes. The data of the file is divided into a predetermined number of segments to reduce a time period for reading the file. The predetermined number of segments is based on the predicted number of tape drives. The data segments are written to the available tape drives.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Masayuki Iwanaga, Yutaka Oishi
  • Patent number: 9728206
    Abstract: A storage device includes a transducer head including a first write element configured to write data at a first write width and a second write element configured to write data at a second write width less than the first write width. According to one implementation, the first write element writes data at a first linear density and to alternating data tracks and the second write element writes data at a second linear density and to data tracks interlaced with the alternating data tracks.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: August 8, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Kaizhong Gao, Wenzhong Zhu, Edward Gage
  • Patent number: 9728221
    Abstract: This application includes systems and techniques relating to storage devices, such as a device including: a first read channel to process a first input signal obtained from a storage medium using a first read head; a second read channel to process a second input signal obtained from the storage medium using a second read head, which is offset from the first read head in each of two dimensions; a single digital timing loop configured to control interpolation of timing of sampling for first and second analog to digital converters in the first and second read channels; and a two dimensional equalizer coupled with output lines of the first and second read channels; the device being configured to account for a fractional timing difference between the first input signal and the second input signal, the fractional timing difference being a fractional amount of a single clock cycle of the device.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: August 8, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Mats Oberg, Nitin Nangare
  • Patent number: 9679597
    Abstract: An apparatus and method involves a writer configured for heat-assisted magnetic recording of data to a magnetic storage medium. A controller is coupled to the writer. The controller and writer are configured to write data to a plurality of concentric bands of the medium each comprising a plurality of partially overlapping narrow data tracks and a wide track. The wide tracks of successive bands are positioned adjacent to one another with no intervening narrow data track therebetween.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 13, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Wenzhong Zhu, Alfredo Sam Chu
  • Patent number: 9666213
    Abstract: In response to a command to update a target track, two tracks or more are concurrently read. The two tracks or more tracks include a top track that partially overlaps the target track. Data of the top track is stored in a memory, and the update data is written over at least part of the target track. The stored data is written on the recording medium over the top track or at a different location.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 30, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Mehmet Fatih Erden, Steven Douglas Granz
  • Patent number: 9640217
    Abstract: Systems and methods relating generally to determining flaws on a storage medium.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 2, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventor: Jefferson Singleton
  • Patent number: 9607642
    Abstract: An AC signal having a specified frequency and a DC offset voltage is applied to a slider substrate or a magnetic recording medium. A low- or non-modulation interface is defined between the slider and medium. In response to applying the AC signal, an oscillation in an electrostatic force occurs between the slider and the medium at the specified frequency, which causes an oscillation in thermal sensor signal at the slider, which oscillates at the specified frequency. A heater of the slider is adjusted to decrease spacing between the slider and medium during oscillation of the electrostatic force. For each heater adjustment, thermal sensor resistance is measured over a specified number of medium revolutions. Head-medium contact is detected using one of an amplitude of a harmonic of the thermal sensor signal and a summation of amplitudes of all frequency components at the specified frequency.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: March 28, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Won Choul Yang, Jin Pil Kim, Shi Jung Kim
  • Patent number: 9576594
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a first output signal from a write driver, the write driver having an operating voltage applied thereto, receiving a second output signal from a comparator circuit, the comparator circuit having a reference voltage applied thereto, comparing a voltage of the first output signal with a voltage of the second output signal, and detecting a high resistance condition in response to determining that the voltage of the first output signal is less than the voltage of the second output signal. According to the present embodiment, the high resistance condition indicates open and/or partially open circuitry in the write driver. Moreover, the operating voltage is equal to the reference voltage. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 21, 2017
    Assignee: International Business Machines Corporation
    Inventor: Larry L. Tretter
  • Patent number: 9570105
    Abstract: Systems and methods are disclosed for data processing, and more particularly for equalizing a data signal during both real time (i.e., on the fly) and retry operation. The system may include a first equalizer circuit operable to equalize a first sample set, and a second equalizer circuit operable to equalize a second sample set. The system may include a third equalizer circuit operable to equalize a summed data set to yield a third equalized output. The system may include a summation circuit connected to the first equalizer circuit, the second equalizer circuit, and a switch circuit. The summation circuit is operable to sum at least the first equalized data set and the second equalized data set to yield the summed data set. The switch circuit selectively provides the third equalized data set to the summation circuit.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 14, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: George Mathew, Jongseung Park, Han Fang, Richard Rauschmayer