Abstract: Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

Abstract: When writing data to a magnetic data storage medium, it is detected whether duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold. When the duration, before the transition, of the data to be written exceeds the predetermined threshold, the data is written by applying an initial pulse and then maintaining, until a shut-off pulse, a steady-state write current having an amplitude less than the initial pulse. A shut-off adjustment is determined based on a predetermined delay. The shut-off pulse is initiated at a time based on one bit period prior to the transition, adjusted by the shut-off adjustment. When the duration, before the transition, of the data to be written is at most equal to the predetermined threshold, the data is written by applying the initial pulse without applying a steady-state write current before the transition.

Abstract: Various embodiments include an error correction code (ECC) system that provides protection against various errors in addition to data bit errors. In general, ECC codes protect against data bit errors, where one or more data bits in a data word contain the wrong value. The ECC code is based on the original data bits, such that a data bit error results in a data word that is inconsistent with the ECC code generated for and stored with the data word. The present embodiments generate ECC codes based on address information and/or sequencing information in addition to the data bits in the data word. As a result, the present embodiments detect bit errors in this address information and/or sequencing information. Such errors include write address decoding errors, read address decoding errors, write enable errors, and stale data errors.

Abstract: Various illustrative aspects are directed to a data storage device. The data storage device comprises a first actuator; a second actuator; a first set of disks, comprising one or more disks configured to correspond with the first actuator; a second set of disks, comprising one or more disks configured to correspond with the second actuator; and one or more processing devices. The one or more processing devices are configured to: write final spirals on the first set of disks; determine a time delta to implement cross-actuator alignment between the first set of disks and the second set of disks; and apply the time delta in writing final spirals for the second set of disks.

Abstract: A rechargeable battery includes at least an electrolyte layer, a cathode layer and an anode layer. The electrolyte layer includes a lithium salt compound arranged between a cathode surface of the cathode layer and an anode surface of the anode layer. The anode layer is a nanostructured silicon containing thin film layer including a plurality of columns, wherein the columns are directed in a first direction perpendicular or substantially perpendicular to the anode surface of the silicon thin film layer. The columns are arranged adjacent to each other while separated by grain-like column boundaries running along the first direction. The columns include silicon and have an amorphous structure in which nano-crystalline regions exist.

Abstract: A storage network operates by storing at least one data object in the SN as encoded data slices that are dispersed error encoded; detecting at least one storage error associated with storage of at least one of the encoded data slices in the storage network; and rebuilding the at least one of the encoded data slices associated with the storage error utilizing locally decodable code segments.

Abstract: Various embodiments of the present technology may provide methods and system for an integrated circuit. The system may provide a plurality of integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device. Each integrated circuit may comprise a register storing a common default address. Each integrated circuit may further comprise an interface circuit configured to overwrite the default address of one integrated circuit with a new address while preventing changes to the remaining integrated circuits.

Abstract: A method begins with a processing module of a dispersed storage network (DSN) receiving a first data object for storage in the DSN from a requesting entity based on an identifier associated with the first data object. The method continues with the processing module storing the first data object in the DSN, facilitating storage of the first data object in a cache memory using an address-based map and determining whether to transfer one or more data objects of a plurality of data objects from the cache memory. Based on a determination to transfer one or more data objects, the method continues by identifying a data object and another processing module to receive the data object, initiating a capacity query for the other processing module. The method continues with the processing module facilitating transfer of the second data object to the other processing module, receiving a transfer confirmation message; and facilitating updating the address-based map.

Abstract: A machine tool, which has a tool magazine for storing multiple tools and is for machining a workpiece with a tool held on a main shaft by moving the main shaft relative to the workpiece, wherein the machine tool is provided with: multiple feed shafts for moving the tool relative to the workpiece; a tool magazine drive motor for driving the tool magazine; and a manual pulse generator, which is for sending a positive or negative command pulse to the multiple feed shafts or tool magazine drive motor, the manual pulse generator being provided with a selection switch for selecting one of the multiple feed shafts or the tool magazine drive motor as the destination to which the command pulse is to be sent.

Abstract: A method for writing data in a disk drive having actuators each controlling arms extending over disk surfaces, including: receiving a write command from a host; receiving from the host data; dividing the data into data blocks; determining: a first surface from the disk surfaces where data is written by a first head of an arm controlled by a first actuator of the actuators; and a second surface from the disk surfaces where data is written by a second head of an arm controlled by a second actuator of the actuators; determining storage blocks of each of the first and the second surface; and writing first data blocks of the divided data blocks to the determined storage blocks of the first surface using the first head while writing second data blocks of the divided data blocks to the determined storage blocks of the second surface using the second head.

Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.

Abstract: A method for creating a volume that contains data from an original stream of multiple files, and which can be optimally deduplicated by an underlying deduplication storage system. The method comprises receiving data records representing metadata and file data, at least a part of which are already separated, separating the metadata and the file data into a first file and a second file, the first file and the second file being paired, the first file called Metadata Volume containing metadata, header data and references to the file data, and the second file called Aligned Volume containing file data only. A further part of the records which contain both metadata and file data are separated into metadata and file data and then subjected to the step of separating the metadata and the file data into the first file and the second file.

Abstract: A data storage device is disclosed wherein a first codeword is generated comprising first redundancy, and a second codeword is generated comprising second redundancy. At least part of the first codeword is written to a first data sector and a second data sector of a first data track on a disk, and at least part of the second codeword is written to a third data sector and a fourth data sector of the first data track different from the first data sector and the second data sector. When an anomaly is detected in the first data sector, first extended redundancy is generated over at least the first data sector and the second data sector of the first data track without generating second extended redundancy over the third data sector and the fourth data sector. Data is recovered from the first data sector based on the first extended redundancy.

Abstract: A control device includes a processor. The processor is configured to receive an execution request for write processing of writing data of logical volumes to second physical volumes. The data of the logical volumes is stored in first physical volumes. The processor is configured to generate write information on basis of data sizes of the respective logical volumes and free spaces of storage areas of the respective second physical volumes. The processor is configured to perform, on basis of the write information, control of writing first data of the logical volumes from a cache unit to the second physical volumes. The processor is configured to perform control of reading second data of the logical volumes from the first physical volumes to the cache unit. The processor is configured to optimize the write information in response to completion of the control of reading.

Abstract: One or more detectors detect data from respective one or more analog sources operable to read from a storage medium. A buffer pool is between the decoders and two or more detectors. The decoders are simultaneously operable, via the buffer pool, to independently decode the data from the one or more detectors.

Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.

Abstract: An apparatus and method are described for enforcement of reserved bits. For example, one embodiment of a processor comprises: a memory management unit to store a set of bits including a set of reserved bits to a system memory; reserved bit enforcement logic to generate a pseudo-random pattern in the reserved bits and an error correction code over the pseudo-random pattern prior to storing the reserved bits; the memory management unit to load the reserved bits including the pseudo-random pattern and the error correction code; the reserved bit enforcement logic to use the error correction code to determine whether the reserved bits have been modified by software; and if the reserved bits have been modified, then the processor to generate an error condition and if not modified, then the processor to continue normal execution.

Abstract: In at least one embodiment, an optical data storage tape is provided. The optical data storage tape includes a read/write data area including a plurality of writeable tracks for storing data thereon, each writeable track having a first track width. The optical data storage tape further includes a seam area positioned proximate to the read/write data area. The seam area including a plurality of non-writeable tracks, each non-writeable track including a second track width that is greater than the first track width for each writeable track.

Abstract: Embodiments described herein can avoid such speed degradations caused by performance monitoring. According to one embodiment, a media drive monitoring device can issue a command that does not penetrate reservations at the drive. If the drive is reserved, the drive will return a reservation conflict (“RC”) or other status indicating the previous reservation. The monitoring device can continue to issue the command to the drive until the drive responds in a manner that indicates that it is no longer reserved. The monitoring appliance can then issue a command to collect information from the drive (e.g., the Log Sense command or other command).

Abstract: In one general embodiment, a method includes determining a sampling interval for an interpolator using at least one parameter. The method further includes applying the sampling interval to the interpolator in response to determining the sampling interval. In another general embodiment, an apparatus includes an interpolator and a controller. The controller is configured to determine a sampling interval for the interpolator using at least one parameter. The controller is also configured to apply the sampling interval to the interpolator in response to determining the sampling interval.

Abstract: Embodiments are described for systems and methods that facilitate control of virtual endpoint failover/failback during an administrative SCSI target port disable or enable operation. In this case, SCSI target virtual endpoints may failover to a secondary SCSI target port when the primary port fails. When the primary port is corrected and enabled by the administrator the failover method pulls virtual endpoints on secondary ports back to the primary port under administrator control; and if an administrator wishes to manually disable a SCSI target port the failover operation pushes (failover) all virtual endpoints currently using the port as a primary to a secondary port.

Abstract: Upon receipt of an instruction to access a logical address of a storage medium, an information processing apparatus controls access to its corresponding physical address of the storage medium. A management unit manages mapping between a continuous series of logical addresses and discrete physical addresses skipping a predetermined number of replacement areas. A controller identifies to which physical address the received logical address is mapped, and controls access to the storage medium using the identified physical address. When a defect occurs in a storage area indicated by a physical address, the information processing apparatus remaps its corresponding logical address to a replacement area adjacent to the defective physical address.

Abstract: A method for managing an encoding process, the method includes receiving or determining, by a processor, (i) code rates for multiple pages, and (ii) sizes of a plurality of data segments to be stored in the multiple pages after being encoded to provide multiple codewords; determining, by the processor, sizes of the multiple codewords while maintaining the code rates for the multiple pages and minimizing a number of split data segments out of the plurality of data segments, wherein each split data segment is split between at least two codewords of the multiple codewords, wherein a retrieval of the split data segment involves a retrieval of the at least two codewords; and sending to an encoder information about the sizes of the multiple codewords.

Abstract: Technologies for a single-pass/single copy network abstraction layer unit (“NALU”) parser. Such a NALU parser typically reuses source and/or destination buffers, optionally changes endianess of NALU data, optionally processes emulation prevention codes, and optionally processes parameters in slice NALUs, all as part of a single pass/single copy process. The disclosed NALU parser technologies are further suitable for hardware implementation, software implementation, or any combination of the two.

Abstract: Devices implement encapsulation to support link layer preemption. The device may include a encapsulation logic that encapsulates data, such as an Ethernet frame, to produce an encapsulated frame. The encapsulated frame may include an encapsulation element that indicates whether the encapsulated data includes non-preemptible data, such as Distinguished Minimum Latency Traffic (DMLT), or preemptible data. The encapsulated frame may also indicate whether the encapsulated data comprises the last fragment of a preemptible frame.

Abstract: A system, method and computer program product for accessing host data records stored in a virtual tape storage (VTS) system. The computer program product includes a computer readable storage medium having computer readable program code embodied therewith. The computer readable program code includes computer readable program code configured to receive a mount request to access at least one host data record in a VTS system; computer readable program code configured to determine a starting logical block ID (SLBID) corresponding to the at least one requested host data record; computer readable program code configured to determine a physical block ID (PBID) that corresponds to the SLBID; computer readable program code configured to access a physical block on a magnetic tape medium corresponding to the PBID; and computer readable program code configured to output at least the physical block without outputting an entire logical volume that the physical block is stored to.

Abstract: A computer-implemented method for accessing data stored in a virtual tape storage (VTS) system, according to one embodiment, include receiving a mount request to access at least one host data record in a VTS system, issuing a locate command to position the sequential access storage medium having the logical volume stored therein to about a position where the physical block having at least a portion of the requested at least one host data record therein is located; creating a partial virtual volume in a tape volume cache; and copying the physical block having the at least a portion of the requested at least one host data record therein from the sequential access storage medium to the partial virtual volume in the tape volume cache. An amount of data copied from the logical volume to the partial virtual volume is less than the amount of data in the logical volume.

Abstract: In an embodiment, a method can include sending an I/O request from a mainframe to a virtual tape server. The method can further include reading a non-virtual tape file from the virtual tape server to the mainframe over a virtual tape protocol if the I/O request is a read request. The method can further include writing a non-virtual tape file from the mainframe to the virtual tape server over the virtual tape protocol if the I/O request is a write request.

Abstract: A pattern of features of a storage medium includes first features having a first logical state and second features having a second logical state, wherein a cross track dimension of the first features is different from a cross track dimension of the second features. A transducer of a memory device senses the pattern of features and generates a transducer signal. Read circuitry samples the transducer signal at a frequency of a sampling clock signal and generates a read signal from the sampled transducer signal. Servo electronics includes a demodulator that demodulates at least first and second orthogonal frequency components of the read signal. Timing circuitry synchronizes a phase of the sampling clock signal with a phase of the pattern of features using the first orthogonal frequency component. Position error circuitry generates a signal indicating a cross track positional offset of the transducer relative to the features using the first and second orthogonal frequency components.

Abstract: Physical storage is replaced online in a data integrity storage system comprising RAID groups of physical disks in separate enclosures (shelves). All disks of a RAID group are located on a corresponding shelf, and each shelf is mapped by an internal file system to a separate independent logical address space partitioned into a plurality of blocks forming a blockset containing data and metadata. Source shelf disk data is moved online to disks of a target shelf using invulnerable data movement that ensures the integrity of the data, and source shelf blockset metadata is migrated to a corresponding target shelf blockset. After verifying the correctness of the target data and metadata, the source shelf and blockset are removed.

Abstract: One embodiment relates to a method of generating worst case inter-symbol interference (ISI) inducing short patterns for simulating and/or testing a communication link. The method includes the generation of a binary clock sequence comprising bits of alternating values at the beginning of the pattern. In addition, an ISI inducing binary sequences and its complement are generated after the clock sequence. Another embodiment relates to a pattern generator for generating an worst case inter-symbol interference inducing short pattern for testing a communication link. Other embodiments, aspects, and features are also disclosed.

Abstract: An exemplary hard disk (HD) track has a full overhead section followed by user sections interleaved with intervening partial overhead sections that are too short for an HD drive (HDD) to attain sufficient timing lock using only one partial overhead section, but long enough for the drive to attain sufficient timing lock using multiple partial overhead sections to read user data from the user section immediately following the partial overhead section where sufficient timing lock is attained. The drive begins, but does not finish, attaining timing lock based on the first partial overhead section, but the drive does finish attaining timing lock based on the last partial overhead section. The drive can also read user data in subsequent user sections by maintaining or re-attaining sufficient timing lock using each successive partial overhead section. Increased user data storage is achieved without significantly impacting average latency of HDD read sessions compared to conventional HD drives.

Abstract: An information handling system includes a host processor and a tape drive, which in turn includes a controller and a compression buffer. The controller is in communication with the host processor, and is configured to receive a diagnostic command from the host processor, to switch the tape drive from a normal mode to a diagnostic mode in response to the diagnostic command, and to send a compression ratio for data associated with a write command to the host processor. The compression buffer is in communication with the controller, the compression buffer configured to receive the write command, to compress data associated with the write command while in the diagnostic mode, to calculate the compression ratio for the data associated with the write command, and to delete the compressed data while the tape drive is in the diagnostic mode.

Abstract: A disk drive is disclosed comprising a disk having a plurality of data tracks defined by servo sectors, where each data track comprises a plurality of data sectors, and each servo sector comprises a servo preamble and servo data. The disk drive further comprises a head comprising a read element and a write element, and a servo read channel comprising an analog front end and a timing recovery circuit. During an access operation, data preceding the servo preamble of a first servo sector in the first data track is read in order to initialize the analog front end of the servo read channel. At least part of the servo preamble is read to initialize the timing recovery circuit of the servo read channel, and at least part of the servo data of the servo sector is read using the timing recovery circuit.

Abstract: According to one embodiment, there is provided a magnetic disk device including a magnetic disk, a storage unit, and a control unit. The magnetic disk includes a recording region. The storage unit is configured to store a value according to number of accesses to each of a plurality of regions obtained by dividing of the recording region of the magnetic disk in association with each of the plurality of regions. The control unit is configured to count a value according to the number of accesses to each of a plurality of regions in a count step unit that is a value determined according to an elapsed time from occurrence of a specific situation and is a value counted per unit access, and to update the value stored in the storage unit.

Abstract: Data is recorded such that the positions of data will be aligned in a traveling direction and a width direction of the storage medium. The medium travels in the traveling direction from a first to a second position as a certain wrap of a group of plural files in a first physical range between the first and the second positions. A head shifts from the certain wrap to another wrap in the width direction of the medium. The medium travels in the traveling direction from a third to a fourth position as the other wrap of a group of plural files in a second physical range between the third and the fourth positions. The plural files in groups on the certain wrap and the other wrap may be written in reverse order to each other after being once stored in a buffer.

Abstract: Data is recorded such that the positions of data will be aligned in a traveling direction and a width direction of the storage medium. The medium travels in the traveling direction from a first to a second position as a certain wrap of a group of plural files in a first physical range between the first and the second positions. A head shifts from the certain wrap to another wrap in the width direction of the medium. The medium travels in the traveling direction from a third to a fourth position as the other wrap of a group of plural files in a second physical range between the third and the fourth positions. The plural files in groups on the certain wrap and the other wrap may be written in reverse order to each other after being once stored in a buffer.

Abstract: Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword.

Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of servo sectors defining a plurality of servo tracks. The servo tracks form a plurality of servo zones, and at least one servo sector of a servo track comprises a partial track address. A read signal generated by the head is processed to detect a current servo zone for the head, and the read signal is processed to detect the partial track address in one of the servo sectors of the current servo zone. A full track address is generated based on the detected servo zone and the detected partial track address.

Abstract: According to one embodiment, a disk storage apparatus includes a disk having a storage area, a storage device storing management information, and a controller. The storage area includes a plurality of areas. The management information includes information indicative of a use priority or rank of each of the areas. The information indicative of the use priority or rank is set based on a quality index relating to a read operation or a write operation. The controller selects an area which is high in the use priority or rank and is usable, by referring to the management information, and executes the write operation on the selected area.

Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a plurality of tracks defined by a plurality of servo sectors. An estimated track ID is generated and a plurality of proximate track IDs is generated having values proximate the estimated track ID. A set of Gray codes is generated each corresponding to the estimated track ID and the proximate track IDs, wherein each Gray code in the set of Gray codes comprises N bits, and M bits out of a high order of the N bits comprise the same value. A recorded Gray code is detected in a first servo sector to generate a detected Gray code, and an error in the detected Gray code is corrected by inverting at least one bit in the detected Gray code comprising a value that is different from the value of the corresponding bit in the M bits.

Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.

Abstract: A magnetic tape media for storing data includes at least one servo band extending along the magnetic tape media and having servo information encoded by an M-ary alphabet A comprising M>2 different symbols and is arranged in a set of words. Each word of the set of words contains synchronization information, wherein each symbol used for representing the synchronization information is from a set B of m symbols, which set B is a proper subset of the symbols in the alphabet A such that 1?m<M; longitudinal position information, wherein each symbol used for representing the longitudinal position information is from a set C of M-m symbols, which set C is a complementary set to set B; and other information, wherein each symbol used for representing the other information is from the set C of M-m symbols.

Abstract: According to one embodiment, a magnetic disk, a semiconductor memory, and a controller are installed. In the magnetic disk, writing is performed in units of band which is a collection of a plurality of adjacent tracks. The semiconductor memory caches data written in the magnetic disk. The controller manages the data cached in the semiconductor memory in units of capacity which is smaller than capacity of the band.

Abstract: Disk drives with servo systems are described that include a servo ID pattern (SID) with a SAM field, as well as, one or more Integrated Servo sequences designed to provide a redundant sync mark function. The write-to-read gaps are omitted before selected servo sector SIDs. For example, write-to-read gaps can be omitted before alternating servo sector SIDs. When in write-mode that allows writing an extended user data sector without a write-to-read gap, the servo system delays the servo gate assertion with respect to the following SID to accommodate the absence of the write-to-read gap, which means that the SAM field cannot be read, but the Integrated Servo sequence(s) can be read and detected by the digital filters. Embodiments of the invention include sync mark timing for each SID (not just every other SID) even when writing extended user data sectors by using the Integrated Servo sequences to provide a sync timing function.

Abstract: According to embodiments of the present invention, a storage medium is provided. The storage medium includes a dedicated servo layer including a plurality of servo tracks, wherein at least one of the plurality of servo tracks includes a modulated address information including an address information being modulated by at least one frequency associated with the at least one of the plurality of servo tracks. According to further embodiments of the present invention, a modulator for a storage medium, a demodulator for a storage medium, a data storage device and a method of processing address information for a data storage device are also provided.

Abstract: Methods and apparatus are provided for improved detection of servo sector data in a magnetic recording system using single bit error correction. Servo sector data is processed by detecting the servo sector data; determining whether a single bit error occurred in the detected servo sector data; and flipping a bit value of an individual bit in the detected servo sector data having a lowest amplitude sample among the samples of the detected servo sector data when a single bit error is detected in the detected servo sector data. The servo sector data comprises, for example, a servo address mark, Gray data, an RRO address mark and/or RRO data. For example, the bit value can be flipped by changing a binary value of one to a binary value of zero and changing a binary value of zero to a binary value of one.

Abstract: A method and computer program product identify the location of a bad block on a disk platter of a hard disk drive, determine an avoidance area extending from the bad block, and prevent data from being written to the avoidance area.

Abstract: A method for optimizing control circuit for FC HDDs in a system includes determining the number of subsystems supported in a FC loop and the number of HDDs to be supported in each of the subsystems, analyzing binary values of address of all HDDs for each of the subsystems, enumerating logical variations of the address selection signals according to the analyzed binary values to obtain logic combinations for the address selection signals, analyzing logic relations between these logic combinations and a system address signal, selecting logic components required according to the found logic relations, and calculating the total number of required logic components and the number of address selections signals that can share an output pin of each of the required logic components based on properties of output pins of the logic components and maximum input current of the address selection signals.