Transient Responsive Patents (Class 361/111)
  • Patent number: 11664657
    Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fang Lai, Yi-Hsun Wu, Ching-Yun Chang
  • Patent number: 11658472
    Abstract: An apparatus includes a plurality of surge protection devices (e.g., multiple metal oxide varistors connected in parallel) configured to be coupled to a power system, a plurality of mechanical actuators associated with respective ones of the surge protection devices and configured to indicate status of the associated surge protection devices, and a detector circuit configured to sense actuation of the actuators and responsively determine a protection status of the plurality of surge protection devices. The detector circuit may include a plurality of switches configured to be actuated by respective ones of the actuators. The detector circuit may further include a processor coupled to the plurality of switches and configured to determine states of switches and to determine the protection status based on the determined status of the switches. The processor may be configured to interpret the status of the switches based on a stored identifier.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: May 23, 2023
    Assignee: Eaton Intelligent Power Limited
    Inventors: Douglas Garrelts, James Nicholas Skoczlas
  • Patent number: 11624766
    Abstract: A method for measuring a partial discharge in an electric drive system with an electric rotating machine and a converter during the operation of the electric drive system includes continuously analyzing a signal shape of a converter signal generated by the converter. A measurement signal is measured while the converter signal has a sinusoidal signal shape, and the measurement signal is compared with a reference signal. A partial discharge is detected when a deviation of the measurement signal from the reference signal exceeds a threshold value.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: April 11, 2023
    Assignee: Siemens Aktiengesellschaft
    Inventors: Artur Jungiewicz, Alija Obralic
  • Patent number: 11626770
    Abstract: A power apparatus, power assembly, energy assembly or energy apparatus that stores and disperses energy, the power assembly including: (1) a first and second energy object that experiences movement so as to store kinetic energy in the energy object, the energy object including a magnet assembly through which electrons are driven resulting in electric output from the magnet assembly, and the electric output dependent on experienced EMF (electro-motive force) that is experienced by the magnet assembly. The power assembly can include a switch assembly adapted to perform switching to switch between a first arrangement in which the first positive output is connected to the second positive output, and a second arrangement in which the first positive output is connected to the first negative output, and such second arrangement provides increased energy output relative to the first arrangement. A flip assembly can be provided that performs flipping of output energy.
    Type: Grant
    Filed: November 30, 2019
    Date of Patent: April 11, 2023
    Inventor: Joshua Robert Miner
  • Patent number: 11621261
    Abstract: The embodiments provide a detection circuit and a detection method. The detection circuit includes an ESD protection device, a first fuse and a transistor. A first terminal of the ESD protection device is connected to a first terminal of the first fuse, and a connection terminal of the ESD protection device and the first fuse serves as a first test terminal; a second terminal of the first fuse is connected to a gate electrode of the transistor, and a connection terminal of the first fuse and the transistor serves as a second test terminal; and a second terminal of the ESD protection device is connected to at least one of a source electrode, drain electrode or substrate of the transistor, and a connection terminal of the ESD protection device and the transistor serves as a third test terminal.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 4, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qian Xu
  • Patent number: 11616390
    Abstract: Provided in embodiments of the present invention are a micro-grid reconstruction method and device, a micro-grid protection and control center and a storage medium. The method includes: monitoring and acquiring current operating data of a micro-grid in real-time; storing the acquired current operating data and corresponding time stamp information in a database; analyzing an operating state of the micro-grid based on the operating data and the corresponding time stamp information that are stored in the database; and determining a current control scheme for the micro-grid according to a current analysis result, and reconstructing the micro-grid according to the current control scheme. The technical solution mentioned above realizes flexible protection and control of the micro-grid and improves the operating automation and intelligence of a system.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 28, 2023
    Assignee: Tsinghua University
    Inventors: Hengwei Lin, Kai Sun, Xi Xiao
  • Patent number: 11616360
    Abstract: An integrated circuit is provided. An ESD inhibition circuit of the integrated circuit is connected with a first pad, a first node and a second node. The ESD inhibition circuit includes a capacitor bank, a resistor, a voltage selector and a switching transistor. The capacitor bank is connected between the first pad and a third node. The resistor is connected between the third node and the first node. The two input terminals of the voltage selector are connected with the third node and a fourth node, respectively. An output terminal of the voltage selector is connected with a fifth node. A first terminal of the switching transistor is connected with the first pad. A second terminal of the switching transistor is connected with the second node. A gate terminal of the switching transistor is connected with the fifth node.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: March 28, 2023
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Wei Lai, Yun-Jen Ting, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Patent number: 11616359
    Abstract: Disclosed is an ESD protection circuit which performs a protection operation by detecting an introduction of an ESD signal when the ESD signal is introduced through a power line. The ESD protection circuit includes a noise detection circuit configured to provide a first detection signal which detects power noise or an ESD signal introduced through a power line; an ESD detection circuit configured to provide a second detection signal which detects an ESD signal introduced through the power line; and a pull-down control circuit configured to perform pull-down on the ESD signal of the power line when the first detection signal which detects the power noise or the ESD signal and the second detection signal which detects the ESD signal are received.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: March 28, 2023
    Assignee: SILICON WORKS CO., LTD
    Inventor: Jang Hyun Yoon
  • Patent number: 11611211
    Abstract: A system having a device for conducting an electrostatic discharge (ESD) current from a designated pin node. The system includes first and second pin nodes, and a switching device having a first switching threshold. The switching device includes a first, terminal coupled to a reference node, and a second terminal, coupled to the first pin node to actuate the switching device to conduct ESD current from the first pin node responsive to a voltage between the first pin node and the reference node exceeding the first switching threshold. The switching device further includes a third terminal, coupled to the second pin node, to actuate the switching device to conduct ESD current from the first pin node responsive to a voltage between the first pin node and the second pin node exceeding a second switching threshold.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: March 21, 2023
    Assignee: Analog Devices, Inc.
    Inventor: Michael Amato
  • Patent number: 11606888
    Abstract: A circuit module 2 comprises: a wiring structure 4; at least one electronic component 6a, 6b arranged on the upper surface of the wiring structure 4; an insulating resin layer 8 which is provided on the upper surface of the wiring structure 4 and in which at least one electronic component 6a, 6b is embedded; and a metal layer 10 provided on the upper surface of the insulating resin layer 8. The surface roughness of the portion S1 directly above each electronic component on the upper surface of the insulating resin layer 8 is expressed as R1. The surface roughness of the portion S2 other than the portion directly above all the electronic components on the upper surface of the insulating resin layer 8 is expressed as R2. At least one R1 satisfies the condition: R1>R2.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 14, 2023
    Assignee: TDK CORPORATION
    Inventors: Shuichi Takizawa, Hironori Sato, Atsushi Yoshino, Hideki Kachi
  • Patent number: 11600612
    Abstract: A switch chip includes a first switch device, a first ESD protection device and a second ESD protection device. The first switch device is electrically coupled between a first pad and a second pad. The first ESD protection device is electrically coupled to a third pad which is electrically coupled to the first pad by a first bond wire. The second ESD protection device is electrically coupled to a fourth pad which is electrically coupled to the second pad by a second bond wire.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: March 7, 2023
    Assignee: VIA LABS, INC.
    Inventors: Didmin Shih, Tengyi Huang, Ting-Yen Wang, Yen Wei Wu
  • Patent number: 11588318
    Abstract: A device, a method and a system for monitoring an electrical connection status of a disconnector device are disclosed. The disconnector device is connectable to pole-mounted equipment in a power distribution or transmission grid, thereby disconnecting the pole-mounted equipment. The connection status monitoring device includes a determining section configured to determine whether the disconnector device has been activated and to generate connection status indicator data, indicative of whether the disconnector device has been activated. The determining section further includes a wireless communication section which is adapted to connect to a wireless communication infrastructure using a wireless communication protocol, and to transmit the connection status indicator data over the wireless communication infrastructure.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 21, 2023
    Assignee: Hitachi Energy Switzerland AG
    Inventors: Philipp Sommer, Xavier Kornmann, Daniel Neeser, Stefano Bertoli, Ektor Sotiropoulos, Martin Schick-Pauli, Gian-Luigi Madonna, Alexander Fach, Yannick Maret
  • Patent number: 11581305
    Abstract: Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: February 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nitin Gupta, Ramakrishnan Subramanian, Sitaram Banda
  • Patent number: 11581303
    Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: February 14, 2023
    Assignee: STMicroelectronics SA
    Inventors: Louise De Conti, Philippe Galy
  • Patent number: 11581304
    Abstract: The present disclosure provides an electronic device that includes a substrate. The substrate includes a well and a peripheral insulating wall laterally surrounding the well. At least one lateral bipolar transistor is formed in the well, and the at least one transistor has a base region extending under parallel collector and emitter regions. The peripheral insulating wall is widened in a first direction, parallel to the collector and emitter regions, so that the base region penetrates into the peripheral insulating wall.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 14, 2023
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Olivier Ory
  • Patent number: 11575232
    Abstract: The present disclosure provides an electrical plug including a first temperature detection element and a second temperature detection element. When the processor determines that the temperature of the contact pins is greater than or equal to a temperature threshold according to a first detection signal outputted by the first temperature detection element and a second detection signal outputted by the second temperature detection element, the processor disables the electrical plug to transmit the input power to a load. When one of the temperature detection elements fails, the electrical plug determines whether the temperature of the electrical plug is greater than or equal to the temperature threshold according to the other one of the temperature detection elements. The electrical plug meets the redundant design required for functional safety to avoid unexpected hazards caused by the failure of a single temperature detection element. Therefore, the stability of the electrical plug is enhanced.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: February 7, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Wei Lin, Shao-Hua Li
  • Patent number: 11575259
    Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 7, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Wen-Yi Chen, Reza Jalilizeinali, Sreeker Dundigal, Krishna Chaitanya Chillara, Gregory Lynch
  • Patent number: 11569658
    Abstract: High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: January 31, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, James Zhao
  • Patent number: 11569222
    Abstract: An electrostatic discharge protection circuit for an integrated circuit and a method for electrostatic discharge protection thereof are disclosed. The integrated circuit includes a power source, a ground, a signal input, and a signal output. The integrated circuit further comprises one or more essentially identically configured electrostatic discharge protection circuits, configured to provide electrostatic discharge protection between any two of the power source, the ground, the signal input, and the signal output. A method of providing electrostatic discharge protection includes providing one or more essentially identically configured electrostatic discharge protection circuits coupled between and providing electrostatic discharge protection for any two of the power source, the ground, the signal input, and the signal output. The disclosed integrated circuit and method provide advantages of simplifying the integrated circuit design and reducing design time.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 31, 2023
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Kei Kang Hung, Qi-An Xu
  • Patent number: 11569220
    Abstract: An electrostatic discharge (ESD) protection device includes a first clamping circuit, a second clamping circuit, and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is configured to steer an ESD current from an input/output pad to at least one of the first clamping circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: January 31, 2023
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Wen-Tai Wang
  • Patent number: 11557895
    Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Ken-Hao Fan, Yu-Ti Su, Tzu-Cheng Kao, Ming-Fu Tsai, Chia-Lin Hsu
  • Patent number: 11557896
    Abstract: Provided is an electrostatic discharge protection circuit, including a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor has a first end coupled to a first power rail. The first transistor has a first end coupled to the first power rail, and a control end of the first transistor is coupled to a second end of the first resistor. The second resistor is coupled between a second end of the first transistor and a second power rail. The second transistor has a first end coupled to the first power rail, a control end of the second transistor is coupled to the second end of the first transistor, and a second end of the second transistor is coupled to the second power rail.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: January 17, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Nai Sheng Wu, Chao-Lung Wang, Chia-Lung Lin
  • Patent number: 11552467
    Abstract: An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Michel Bouche
  • Patent number: 11552548
    Abstract: A power supply control device controls power supply through two branch paths branched from a common power supply path. Two N-channel FETs are respectively disposed in the two branch paths. A booster circuit outputs a voltage from a common output end, and applies a voltage to gates of the two FETs through a circuit resistor. Two charge resistors are respectively disposed in two applying paths through which a voltage is applied from the output end of the booster circuit to the gates of the two FETs. Each of two diodes are respectively connected between both ends of each of the two charge resistors. Cathodes of the two diodes are disposed on the side of the booster circuit.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 10, 2023
    Assignees: SUMITOMO WIRING SYSTEMS, LTD., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinji Aoyama, Hiroshi Kimoto, Nobutoshi Hagiwara, Takumi Matsumoto
  • Patent number: 11552469
    Abstract: To provide a semiconductor device with a tolerant buffer capable of protecting the internal circuit even when the power supply potential is turned 0 [V]. In the semiconductor device, the protection voltage generating circuit 100 generates the larger of the divided voltage and the power supply voltage Vdd obtained by dividing the voltage padv applied to the pad 4 as the protection voltage protectv. The first protection circuit 200 for protecting the internal logic circuit 2A,2B and the output buffer 10 and the second protection circuit 300 for protecting the input buffer 20 operate protectv this protection voltage.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 10, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Dai Kamimaru
  • Patent number: 11532609
    Abstract: An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: December 20, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATE
    Inventors: Aravind C. Appaswamy, James P. Di Sarro
  • Patent number: 11527530
    Abstract: An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.
    Type: Grant
    Filed: May 16, 2021
    Date of Patent: December 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, James Paul DiSarro, Ann Margaret Concannon, Rajkumar Sankaralingam
  • Patent number: 11527879
    Abstract: A crowbar module includes first and second electrical terminals, a module housing, and first and second crowbar units. The first crowbar unit is disposed in the module housing and includes a first thyristor electrically connected between the first and second electrical terminals. The second crowbar unit is disposed in the module housing and includes a second thyristor electrically connected between the first and second electrical terminals in electrical parallel with the first crowbar unit.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 13, 2022
    Assignee: RIPD IP DEVELOPMENT LTD
    Inventors: Zafiris G. Politis, Grigoris Kostakis, Thomas Tsovilis, Kostas Bakatsias
  • Patent number: 11515302
    Abstract: A circuit includes a switch coupled between a configuration terminal and an internal node. In a method of operation, the configuration terminal of the circuit is coupled to an internal node during a configuration phase and decoupled from the internal node during normal operation.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 29, 2022
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Andreas Baenisch
  • Patent number: 11508667
    Abstract: Some examples described herein provide for a shield in an integrated circuit (IC) structure for memory protection. In an example, an IC structure includes a semiconductor material, an interconnect structure, and a shield. The semiconductor material has a protected region. Devices are disposed in a first side of the semiconductor material in the protected region. The interconnect structure is disposed on the first side of the semiconductor material. The interconnect structure interconnects the devices in the protected region. The shield is disposed on a second side of the semiconductor material opposite from the first side of the semiconductor material. The shield is positioned aligned with the protected region.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 22, 2022
    Assignee: XILINX, INC.
    Inventors: James Karp, Yan Wang
  • Patent number: 11502876
    Abstract: A transceiver device for a bus system. The transceiver device includes a first bus terminal for connection to a first signal line of the bus system, a second bus terminal for connection to a second signal line of the bus system, and a receiving unit for receiving a bus receive signal from the first and second bus terminals. The transceiver device is designed to interconnect the first and second bus terminals via a predefinable electrical resistance for a predefinable first period of time. The predefinable first period of time is selectable as a function of at least one parameter of the receiving unit.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 15, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Steffen Walker, Arthur Mutter
  • Patent number: 11495963
    Abstract: The present invention discloses an electrostatic discharge protection circuit having time-extended discharging mechanism. A RC circuit is coupled between an ESD input terminal that receives an ESD input and a ground terminal and includes an input control terminal. An inverter includes a P-type transistor coupled between the ESD input terminal and an output control terminal and an N-type transistor circuit including N-type transistors coupled in series and between the output control terminal and a ground terminal, wherein two of the N-type transistors has an internal connection terminal. Gates of the P-type transistor and N-type transistors are controlled by the input control terminal. A switch transistor is coupled between the ESD input terminal and the internal connection terminal. A discharging transistor is coupled between the ESD input terminal and the ground terminal. The gates of the switch transistor and the discharging transistor are controlled by the output control terminal.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: November 8, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsin Liao, Jyun-Ren Chen, Tay-Her Tsaur, Po-Ching Lin
  • Patent number: 11468812
    Abstract: A display apparatus comprises a display panel on which a plurality of pixels are displayed, a plurality of signal lines to which a signal required to drive the display panel is supplied, and an electrostatic discharge circuit connected between each of the plurality of signal lines and the electrostatic discharge line. The electrostatic discharge circuit includes first and second current paths between the signal line and the electrostatic discharge line, a first electrostatic discharge circuit connected to the first current path, including a plurality of first thin film transistors having a first gate electrode connected to the second current path and a second gate electrode connected to the first current path, and a second electrostatic discharge circuit connected to the second current path, including at least one second thin film transistor having a first gate electrode connected to the first current path and a second gate electrode connected to the first current path.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: October 11, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Yeonkyung Kim, TaeWoong Moon, JunHyeon Bae, Yewon Hong, Yeonwoo Shin
  • Patent number: 11462903
    Abstract: An ESD circuit includes a voltage division circuit, a RC control circuit and a voltage selection circuit. The voltage division circuit is connected between a first power pad and a first node, and generates a first voltage. The RC control circuit is connected between the first power pad and a second power pad, and generates a second voltage and a third voltage. The voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage. The first transistor and the second transistor are serially connected between the first power pad and the second power pad. A gate terminal of the first transistor receives the first voltage. A gate terminal of the second transistor receives the third voltage. The third transistor is connected with the first power pad and an internal circuit. A gate terminal of the third transistor receives the fourth voltage.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: October 4, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Wei Lai, Yun-Jen Ting, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Patent number: 11463437
    Abstract: A method can include detecting an activation of a networked device. The method can further include obtaining a hazard score corresponding to a degree of hazard associated with the networked device. The method can further include determining an activation confidence score corresponding to the activation of the networked device. The method can further include determining, based at least in part on the hazard score and the activation confidence score, an adjusted activation confidence score. The method can further include determining that the adjusted activation confidence score exceeds a threshold. The method can further include initiating a deactivation of the networked device in response to the determining that the adjusted confidence score exceeds the threshold.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jacob Thomas Covell, Robert Huntington Grant, Jacky Lu, Thomas Jefferson Sandridge
  • Patent number: 11456595
    Abstract: An electrostatic protection circuit includes first and second diodes, a resistor and a capacitor, an inverter configured to invert a signal to output an inverted signal to a gate-coupled transistor, a first switch configured to block a first leakage current from flowing through a pull-up driver in response to the inverted signal, and a second switch configured to block a second leakage current from flowing through a pull-down driver in response to the signal.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: September 27, 2022
    Inventor: Janghoo Kim
  • Patent number: 11456596
    Abstract: A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: September 27, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 11451051
    Abstract: A system and method for suppressing EMP-induced voltage surges due to detonation of a nuclear weapon at high altitude generating an EMP (HEMP) comprising E1, E2, and E3 component pulses. A plurality of shunting assemblies, each including transient voltage suppressors (TVSs), metal oxide varistors (MOVs), gas discharge tubes (GDTs), other mechanical, electrical and ionization discharge devices (IDDs) and combinations thereof of surge limiting technologies, are positioned intermediate a signal stream and a plurality of electronic device ports associated with a plurality of communication channels for sensing upstream of the communication channels an overvoltage associated with each of the E1, E2, and E3 components of the EMP and shunting the over-voltages to predetermined allowable levels within the predetermined time.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: September 20, 2022
    Inventors: Plamen Doynov, Timothy A Carty
  • Patent number: 11444451
    Abstract: A current transient suppression circuit includes an inductor electrically connected to a test signal by an input of the inductor, at least one switching device electrically connected to an output of the inductor, and an output of the at least one switching device connected to a shunt path. A method of suppressing current transients in a circuit includes receiving a test signal at an inductor, and when the test signal comprises a current transient, the current transient is received at the inductor, activating at least one switching device electrically connected to the inductor to shunt the current transient away from a device under test.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: September 13, 2022
    Assignee: Keithley Instruments, LLC
    Inventor: Arthur Sypen
  • Patent number: 11444077
    Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 13, 2022
    Assignee: STMicroelectronics SA
    Inventors: Jean Jimenez, Boris Heitz, Johan Bourgeat, Agustin Monroy Aguirre
  • Patent number: 11431333
    Abstract: A switching circuit comprising a transistor (23) and a drive component both for controlling the transistor and also for limiting the power supply current (Ia) suppled to a load (22), the drive component being arranged both to receive a control voltage (VH) and also: when the control voltage (VH) is disconnection signal, to generate a drive voltage (Vp) that causes the transistor to occupy a non-conductive state; when the control voltage (VH) is a connection signal and the power supply current (Ia) cannot reach a predefined current threshold, to generate drive voltage (Vp) that causes the transistor to occupy saturated conditions; and when the control voltage (VH) is a connection signal and the power supply current (Ia) can reach a predefined current threshold, to generate a drive voltage (Vp) that causes the transistor to occupy linear conditions, such that the power supply current is regulated so that it does not exceed the predefined current threshold.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 30, 2022
    Assignee: SAFRAN ELECTRONICS & DEFENSE
    Inventors: Olivier Meline, Fran├žois Guillot
  • Patent number: 11424614
    Abstract: Described is a system that includes a solid-state switch in series with a battery and a controller. The system also includes a capacitor coupled between a source and a gate of the solid-state switch and a resistor coupled between the gate of the solid-state switch and ground. The solid-state switch gradually transitions from an open state to a closed state over a time constant of the capacitor and the resistor upon application of power from the battery to the solid-state switch. The system further includes a first switching device that controls the application of power from the battery to the solid-state switch. Additionally, the system includes a second switching device that provides a discharge path of the capacitor upon completion of a task by the controller.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 23, 2022
    Assignee: LANDIS+GYR INNOVATIONS, INC.
    Inventor: Daniel E. Fabrega
  • Patent number: 11418025
    Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage and a second voltage. When a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch. When the voltage difference between the first voltage and the second voltage is lower than a second voltage threshold, the ESD driver outputs a second trigger signal to turn on the ESD protection switch.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: August 16, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Hang Fan, Ming-Fang Lai, Shui-Ming Cheng
  • Patent number: 11417645
    Abstract: An electrostatic discharge protection structure includes a laterally diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes an embedded bipolar junction transistor. A gate, a source, a buried layer lead-out area, and a substrate lead-out area of the LDMOS device are grounded. A drain and a body region lead-out area of the LDMOS device are electrically connected to a pad input/output terminal. In an embodiment, the embedded bipolar junction transistor includes a PNP transistor operative to transmit a reverse electrostatic discharge current. An N+ drain, a gate, an N+ source, and a P+ substrate lead-out area form a grounded-gate NMOS (GGNMOS) operative to transmit a forward electrostatic discharge current.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 16, 2022
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Zhenghao Gan
  • Patent number: 11418027
    Abstract: An electrostatic discharge protection circuit including a silicon controlled rectifier and a transistor is provided. The silicon controlled rectifier includes a first end, a second end, and a third end. The first end of the silicon controlled rectifier is coupled to a first pad. The second end of the silicon controlled rectifier is coupled to a second pad. The transistor includes a first end, a second end, and a control end. The first end of the transistor is coupled to the first pad. The second end of the transistor is coupled to the second pad. The control end of the transistor is coupled to the third end of the silicon controlled rectifier.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: August 16, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Nai Sheng Wu, Chao-Lung Wang
  • Patent number: 11410827
    Abstract: A fuse with a frequency separation function includes an input port portion, an output port portion, a first transmitting portion between the input port portion and the output port portion, the first transmitting portion configured to transmit a lightning surge current entering the input port portion and guide the lightning surge current to the output port portion, a second transmitting portion between the input port portion and the output port portion, the second transmitting portion configured to be capable of transmitting a normal current and an abnormal current entering the input port portion, and a melting mechanism portion which is provided between the second transmitting portion and the input port portion or between the second transmitting portion and the output port portion, the melting mechanism configured not to melt and break when the normal current passes, and configured to melt and break when the abnormal current passes.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 9, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Naomichi Nakamura, Hidetoshi Takada, Jun Kato
  • Patent number: 11404861
    Abstract: Systems and methods for mitigating ground induced currents are provided. In one or more examples, the systems and methods can utilize one or more device(s) that can be configured to detect DC currents being induced in and propagated along a power line that is transmitting an AC power signal. In one or more examples the device can be separate the desirable AC power waveform from the undesirable induced DC voltage and determine if the level of induced DC propagating on the power line requires mitigation. In one or more examples, if it is determined that mitigation is required, then the device can be configured to trigger a switch that can be shunt the DC power at the AC waveform zero crossing to a circuit element that is configured to dissipate the undesirable DC current. Filtering can be employed to remove any inadvertent low voltage harmonic distortion. The switch can be triggered during a zero-crossing of the signal to minimize disruption to an end user of the power signal.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 2, 2022
    Assignee: The MITRE Corporation
    Inventor: Nick Donnangelo
  • Patent number: 11398470
    Abstract: The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: July 26, 2022
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Yaobin Guan, Jianjian Sheng
  • Patent number: 11381076
    Abstract: A drive circuit includes a voltage input circuit, a first surge protection device, and a second surge protection device. The voltage input circuit includes a first line terminal and a second line terminal, and supplies an input voltage to the first and second line terminals. The first surge protection device is connected between the first line terminal and ground to connect the first line terminal to ground when the input voltage is supplied, and to disconnect the first line terminal from ground when the input voltage is not supplied. The second surge protection device is connected between the second line terminal and ground to connect the second line terminal to ground when the input voltage is supplied, and to disconnect the second line terminal from ground when the input voltage is not supplied.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 5, 2022
    Assignee: The Vollrath Company, L.L.C.
    Inventor: Donald Zahrte, Sr.
  • Patent number: 11374396
    Abstract: A circuit protection device is provided. The circuit protection device includes an active energy absorber that is coupled between two power lines in an electrical power distribution system and is configured to selectively conduct fault current responsive to overvoltage conditions. The active energy absorber includes an overvoltage protection module that includes two thyristors that are connected in anti-parallel with one another and a varistor that is connected with the overvoltage protection module as a series circuit. The series circuit including the varistor and the overvoltage protection module is connected between the power lines.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: June 28, 2022
    Assignee: RIPD RESEARCH AND IP DEVELOPMENT LTD.
    Inventors: Grigoris Kostakis, Zafiris G. Politis, Fotis Xepapas, Alexis Chorozoglou, Christos Prevezianos