Transient Responsive Patents (Class 361/111)
  • Patent number: 11362083
    Abstract: A TVS circuit having a first diode with a cathode coupled to a first terminal and an anode coupled to a first node. A second diode has an anode coupled to a second node and a cathode coupled to a third node. A third diode is coupled between the first node and second node. A fourth diode is coupled between the first node and third node. A fifth diode is coupled between the second node and a second terminal. A sixth diode is coupled between the second terminal and the third node. A seventh diode can be coupled between the second terminal and an intermediate node between the fifth diode and sixth diode. The first diode is disposed on a first semiconductor die, while the second diode is disposed on a second semiconductor die. Alternatively, the first diode and second diode are disposed on a single semiconductor die.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Semtech Corporation
    Inventors: Liping Ren, William Allen Russell
  • Patent number: 11362515
    Abstract: The present invention discloses an electrostatic discharge protection circuit having false-trigger prevention mechanism. A RC circuit, including an input control terminal, is coupled between an electrostatic discharge input terminal for receiving an input power and a ground terminal. An inverter includes a P-type transistor circuit, including P-type transistors coupled between the electrostatic discharge input terminal and an output control terminal in series and having an internal connection terminal between two of the P-type transistors, and an N-type transistor, coupled between the output control terminal and the ground terminal. Gates of the P-type and N-type transistors are controlled by the input control terminal A switch transistor, having the gate controlled by the input control terminal, is coupled between the internal connection terminal and the ground terminal.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: June 14, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsin Liao, Jyun-Ren Chen, Tay-Her Tsaur, Po-Ching Lin
  • Patent number: 11330725
    Abstract: A housing includes: a box-shaped main body portion accommodating an electronic circuit substrate and including an opening portion; a lid portion covering the opening portion so as to be able to open or close the opening portion; a jumper detachably attached to the electronic circuit substrate; a window portion different from the opening portion, the window portion being opposed to the jumper and being open at the main body portion; and a cover portion covering the window portion so as to be able to open or close the window portion.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: May 10, 2022
    Assignee: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Haruhiko Tan, Shota Tominaga
  • Patent number: 11316341
    Abstract: Disclosed are a surge protection power supply clamping circuit, a chip and a communication terminal. The power supply clamping circuit comprises at least one driving unit and discharging unit; the discharging units are connected to the corresponding driving units respectively, and the driving units are connected to the same time delay unit respectively; the time delay units and the discharging units are connected to a power supply voltage and a ground line respectively. The driving units or the discharging units are sequentially controlled in the power supply voltage wiring direction, so that the sum values of an equivalent conduction resistance and an equivalent metal wiring resistance of respective discharging units are the same, and therefore, the uneven conduction of an NMOS transistor caused by different metal wiring resistances due to different metal wiring lengths of the NMOS transistor of each discharging unit can be counteracted.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 26, 2022
    Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventor: Sheng Lin
  • Patent number: 11316340
    Abstract: A circuit for preventing failure of a device includes a first rail, electrostatic discharge (ESD) protection circuitry, a second rail, an ESD switching circuitry, biasing circuitry, and a signal limiter. The first rail is for one or more first electrical components formed in a first portion of a substrate. The second rail is for one or more second electrical components formed in a second portion of the substrate. The first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor. The biasing circuitry is configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switching circuitry is switched on. The signal limiter electrically couples to the first rail and the emitter of the parasitic transistor.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies AG
    Inventor: Ulrich Glaser
  • Patent number: 11309308
    Abstract: An electrostatic discharge protection circuit includes an internal circuit, a pad, a first high voltage transistor, an electrostatic protection element and a control circuit. A first terminal of the first high voltage transistor is coupled to the pad, a second terminal of the first high voltage transistor is coupled to the internal circuit and includes a control terminal. The electrostatic protection element has one end coupled to the first end of the first high voltage transistor and the other end grounded. The control circuit is coupled between the control terminal of the first high voltage transistor and the ground terminal. The control circuit is configured to control the first high voltage transistor to turn off when the pad receives an electrostatic voltage.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: April 19, 2022
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Kun-Min Chen, Chien-Lun Chu
  • Patent number: 11295919
    Abstract: A circuit-breaker includes: an input terminal for connecting the circuit-breaker to a voltage source; an output terminal for connecting t the circuit-breaker to a load; a switching circuit having an input side connected to the input terminal and having an output side; and a separation switching unit connected to the output terminal and to the output side of the switching circuit. The switching circuit includes a first current path and a second current path, the first and the second current path being connected in parallel between the input side and the output side. The switching circuit includes a varistor device and a controllable switching component, the varistor device and the controllable switching component being connected in series between the first and the second current path.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 5, 2022
    Assignee: Eaton Intelligent Power Limited
    Inventor: Kenan Askan
  • Patent number: 11285815
    Abstract: An electrical vehicle charging device includes a power converter for receiving an AC voltage from an AC grid or a DC voltage from a DC grid, a transformer having a primary side connected to an output side, a full wave rectifier having a first input and a secondary input and a positive output and a negative output, at least two output capacitors connected between respective end taps of end taps connected in series via a center tap and between the positive output and the negative output, whereby the end taps are for providing the DC voltage to the electrical vehicle, and a switch connected in series between the first input or the secondary input and the center tap, and whereby the electrical vehicle charging device is adapted for closing and/or opening the switch depending on a DC voltage level required for charging the electrical vehicle.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: March 29, 2022
    Assignee: ABB Schweiz AG
    Inventor: Stefan Joannes Raaijmakers
  • Patent number: 11277002
    Abstract: A circuit arrangement for a surge protection device for protecting multiple DC or AC power lines. The circuit arrangement includes a plurality of DC or AC power line inputs, a negative potential or neutral input, a ground potential input, a surge protection component having one or more surge elements, a rectification circuit including a plurality of diodes, and an alarm circuit for receiving a status output from the surge protection component.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 15, 2022
    Assignee: MERSEN USA EP Corp.
    Inventor: Roy Ball
  • Patent number: 11271385
    Abstract: An abnormal-voltage protection apparatus includes a switch unit, a voltage detection unit, and a delay time control unit. The switch unit is coupled to a power supplying path formed between an AC power source and a load. The voltage detection unit detects the AC power source and provides a detection signal. The delay time control unit is coupled to the voltage detection unit and the switch unit, and receives the detection signal and provides a control signal to the switch unit according to the detection signal. When the voltage detection unit detects that the AC power source changes from an abnormal voltage to a normal voltage, the delay time control unit turns on the switch unit by the control signal after a delay time so that the AC power source supplies power to the load through the power supplying path.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 8, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Chieh Tseng, Chia-Hao Yeh, Likai Lin
  • Patent number: 11264797
    Abstract: Disclosed in the present invention is a novel overvoltage protective device for lightning protection, comprising a first varistor, a second varistor, a PTC Thermistor, and lead-out terminals. The first varistor and the PTC Thermistor are connected in parallel, and then further connected in series with the second varistor to form a single port combined circuit. The surge-withstand capability of the first varistor is higher than the surge-withstand capability of the second varistor. At least one of the two lead-out terminals of the single port combined circuit is a thermally-conductive end with low thermal resistance. The second varistor is thermally coupled to the PTC Thermistor. The thermally-conductive end with low thermal resistance is thermally coupled to one or both of the second varistor and the PTC Thermistor.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 1, 2022
    Assignee: CHENGDU TIEDA ELECTRONICS CORP.
    Inventors: Zhicheng Zhang, Lei Ye, Jungu Zhan, Jun Zhang, Xiaolong Shi
  • Patent number: 11239229
    Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
  • Patent number: 11228244
    Abstract: It is an object of one or more embodiments of the present disclosure to provide a Multiple-Inductor Multiple-Output (MIMO) switching converter to supply several different output voltages. The combination of this MIMO converter with a booster circuit supplies one or more individual cores with current that bypasses the parasitic network. The booster circuit has a wider bandwidth or a faster response when compared to the main MIMO switching converter. The MIMO booster circuit can supply a number of cores with only a single set of shared inductors. The main advantages include a lower component count and a reduced printed circuit board footprint to support multiple cores in a Multiple-Inductor Multiple-Output. The present disclosure makes use of the low duty-cycle of the power peaks and the low statistical likelihood of these peaks occurring for all cores simultaneously.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 18, 2022
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Mark Childs
  • Patent number: 11211791
    Abstract: An electrostatic discharge (ESD) protection device including a stack of ESD clamps, a trigger circuit, and a transistor. The trigger circuit may respond to an ESD event by conducting current, which may cause the transistor to turn on. A combination of the trigger circuit conducting current and the transistor turning on may trigger the ESD clamps into a conducting state to shunt current from a first node to a second node.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: December 28, 2021
    Assignee: SOFICS BVBA
    Inventors: Sven Van Wijmeersch, Stefaan Verleye, Benjamin Ernest Henri Virginie Van Camp
  • Patent number: 11209475
    Abstract: A transient voltage suppressor (TVS) can include an input line, a return line, and a plurality of TVS diodes disposed in series between the input line and the return line. The TVS can include a switch assembly operatively connected to the plurality of TVS diodes and configured to bypass at least one of the plurality of TVS diodes to allow a remainder of the plurality of TVS diodes to be tested at a voltage that is lower than if the switch assembly were not employed.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 28, 2021
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Robert Annan Barnet
  • Patent number: 11201467
    Abstract: Reduced flyback electrostatic discharge (ESD) surge protection is disclosed. An ESD protection circuit differentiates ESD events from normal power on based on supply rise time. During an ESD protection cycle, the ESD protection circuit briefly clamps a supply on an identified ESD edge to limit and protect an electronic device from high voltage and/or current. In some cases, a surge condition may occur as the ESD protection circuit becomes disabled, such as in the presence of a fast rise time power supply. When the power supply is also inductive, a flyback voltage overshoot at the sudden release of the ESD clamp can result in permanent over voltage-related device damage. An exemplary ESD protection circuit includes a controlled disable state which reduces or eliminates flyback during such a surge by gradually ramping down current from the ESD protection cycle.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: December 14, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Stephen James Franck
  • Patent number: 11201614
    Abstract: Disconnection of a circulation path through which a circulation current flows is detected while suppressing an increase in circuit scale. A battery monitoring device includes switching circuits that control currents flowing through coils of main contactors by being controlled to be turned on and off, freewheeling diodes that are connected to the coils of the main contactors to form circulation paths for circulating the currents, and a control unit. The control unit measures output voltages of the freewheeling diodes at an input terminal, and detects the disconnection of the circulation paths based on the output voltages of the freewheeling diodes.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 14, 2021
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Hikaru Miura, Akihiro Machida, Mutsumi Kikuchi, Tatsumi Yamauchi
  • Patent number: 11201465
    Abstract: A semiconductor device including a digital circuit, a first ground potential line provided corresponding to the digital circuit, an analog circuit, a second ground potential line respectively provided corresponding to the analog circuit, and a bidirectional diode group provided between the first ground potential line and the second ground potential line.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 14, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuyuki Morishita
  • Patent number: 11201464
    Abstract: The invention relates to an arrangement for overload protection of overvoltage protection devices, consisting of at least one type II surge arrester with or without a thermal disconnecting device that responds in the event of an of overload. According to the invention, a switching unit free of movable contacts is connected in series with the at least one surge arrester and structurally combined therewith, which switching unit has at least two fixed narrow spaced switching contacts, wherein the spacing of the switching contacts is specified in such a way that in the event of every surge current or discharge process, the switching device changes into a quasi-closed state because of the arc formed; whereas in the idle state, the voltage of the connected mains drops at the switching device, with the surge arrester arranged in series remaining free of leakage current.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 14, 2021
    Assignee: DEHN SE + CO KG
    Inventor: Ralph Brocke
  • Patent number: 11190012
    Abstract: An electrostatic protection circuit that is electrically connected to a first terminal to which a first voltage signal is input, a second terminal to which a second voltage signal whose potential is lower than that of the first voltage signal is input, and a connection terminal that is connected to an external circuit, and mitigates the influence of a surge voltage on an internal circuit, the electrostatic protection circuit including: a discharge node that is electrically connected to the first terminal via a first diode element; a first protection circuit that is electrically connected to the first terminal and the second terminal; a second protection circuit that is electrically connected to the discharge node and the connection terminal; and a third protection circuit that is electrically connected to the discharge node and the second terminal, and an anode of the first diode element is electrically connected to the first terminal, and a cathode of the first diode element is electrically connected to the
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 30, 2021
    Inventor: Masuhide Ikeda
  • Patent number: 11183838
    Abstract: Power sourcing equipment for power over Ethernet (PoE) includes a power supply control circuit, an Ethernet port, and a surge protection circuit. The surge protection circuit includes a first circuit, a second circuit, and a common discharge circuit. The first circuit is connected to a power supply pin group of the Ethernet port, the power supply control circuit, and the common discharge circuit. The second circuit is connected to a non-power supply pin group of the Ethernet port and the common discharge circuit. The first circuit transmits, to the common discharge circuit, a first surge that is input from the power supply pin group. The second circuit transmits, to the common discharge circuit, a second surge that is input from the non-power supply pin group. The common discharge circuit discharges the first surge and the second surge to ground.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 23, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Shiyong Fu, Yan Zhuang, Qi Dong, Xiangen Xu, Xueqi Chen, Yu Ding
  • Patent number: 11164860
    Abstract: An electrostatic discharge protection circuit and a semiconductor device are provided. The circuit includes: a power source terminal, a ground terminal, and a discharge path. The discharge path includes a clamp transistor and a MOS transistor connected in series and integrated into a same semiconductor substrate with different types. For the MOS transistor, a gate electrode is electrically connected to a substrate terminal; a first electrode is one of a source electrode and a drain electrode; a second electrode is another one of the source electrode and the drain electrode; the first electrode is electrically connected to a gate electrode of the clamp transistor; and the second electrode is electrically connected to the ground terminal. When an electrostatic discharge occurs, the MOS transistor is turned on to form parasitic current between a substrate terminal of the clamp transistor and the second electrode of the MOS transistor.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Guang Chen, Jie Chen
  • Patent number: 11165250
    Abstract: A system for conditioning electric power supplied from a three-phase alternating current electric power supply, including three phase lines, to a load, including the phase lines and an electric ground line, includes a plurality of first surge arresters, a plurality of second surge arresters, a plurality of third surge arresters, a three-phase surge suppressor, and a plurality of capacitors. The surge arresters minimize the amount by which the voltage between two phases and the ground line exceeds a rated value. The three-phase surge suppressor minimizes the amount by which the voltage between any of the three phases and the ground line exceeds a rated value. The capacitors minimize the amount by which the voltage between two phases falls below a rated value.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 2, 2021
    Assignee: Innovative Energy Solutions & Services, Inc.
    Inventors: Jerry B. Johnson, Andrew B. Johnson
  • Patent number: 11165254
    Abstract: A property power system can include multiple photovoltaic (PV) panels to generate DC electrical energy from solar energy and a first power conversion module to convert between DC and AC electrical energy and to control aspects of each PV panel. The property power system can have a group of battery blades to store electrical energy and another power conversion module to convert between DC and AC electrical energy and to control aspects of each battery blade. The property power system can have a multiple synchronization interfaces configured to aggregate the AC electrical energy of each of the PV panels/battery blades, respectively, and to control delivery of the aggregated AC electrical energy. The property power system can include a grid circuit disconnector to prevent back-feed of power during grid outage condition while the PV panels or the group of battery blades is powering an electrical load center of the property.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 2, 2021
    Assignee: Sinewatts, Inc.
    Inventor: Shibashis Bhowmik
  • Patent number: 11158628
    Abstract: Disclosed are an electro-static discharge circuit, an array substrate, a display panel and a display apparatus. The electro-static discharge circuit includes a first transistor, a second transistor, a first switching device and a second switching device. A first end of the first transistor is electrically connected to a first level line, a second end of the first transistor is electrically connected to a signal line, a control end of the first transistor is electrically connected to a first end of the first switching device, a second end of the first switching device is electrically connected to the first level line, and a control end of the first switching device is electrically connected to the signal line.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 26, 2021
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Shui He, Zhaokeng Cao, Yinghua Mo, Xiao Li
  • Patent number: 11158570
    Abstract: Semiconductor devices having busing layouts configured to reduce on-die capacitance are disclosed herein. In one embodiment, a semiconductor device includes an electrostatic discharge device electrically connected in parallel with an integrated circuit and configured to divert high voltages generated during an electrostatic discharge event away from the integrated circuit. The semiconductor device further includes a signal bus and a power bus electrically connected to the electrostatic discharge device. The signal bus includes a plurality of first fingers grouped into first groups and the power bus includes a plurality of second fingers grouped into second groups. The first groups are positioned generally parallel to and interleaved between the second groups.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael V. Ho, Eric J. Smith
  • Patent number: 11146061
    Abstract: An overvoltage protection device includes: input terminals; output terminals; at least two overvoltage protection elements for forming staggered protection levels; and at least one longitudinal element electrically connecting an input terminal and an output terminal to conduct an operating current. In order to form a first protection level, a first overvoltage protection device is connected to two input terminals on an input side upstream of the at least one longitudinal element, and, in order to form a second protection level, a second overvoltage protection element is connected to two output terminals on an output side and downstream of the at least one longitudinal element, the at least one longitudinal element influencing a response of the at least two overvoltage protection elements in case of an overvoltage. The at least one longitudinal element is provided with a thermal overload protection device for reducing a possible current flow.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 12, 2021
    Assignee: PHOENIX CONTACT GMBH & CO. KG
    Inventors: Christian Birkholz, Steffen Pfoertner, Jens Willmann
  • Patent number: 11133798
    Abstract: A device includes a first connection pin, a second connection pin, a third connection pin, and a fourth connection pin. The second connection pin is configured to be connected to a supply voltage. The fourth connection pin is configured to be coupled to a reference voltage. The device further includes a first transistor including: a first gate and a first source/drain coupled to the first connection pin; a second transistor including a second gate and a second source/drain connected to the first transistor; and a third transistor including a third gate, a third source/drain connected to the second transistor, and a fourth source/drain connected to the fourth connection pin. The third transistor is configured to be controlled by a digital signal using the third connection pin. Both the first gate and the second gate are directly connected to the second connection pin.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 28, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Nicolas Froidevaux, Laurent Lopez
  • Patent number: 11133299
    Abstract: An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: September 28, 2021
    Assignee: NXP B.V.
    Inventors: Da-Wei Lai, Stephen John Sque, Wilhelmus Cornelis Maria Peters
  • Patent number: 11121546
    Abstract: The invention relates to a protection ensemble, comprising a circuit breaker, and a surge protector device, wherein the circuit breaker and the surge protector device have an interface, wherein the surge protector device comprises a monitoring device and, upon recognizing a fault condition by the monitoring device, the circuit breaker can be tripped by means of the interface.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 14, 2021
    Assignee: PHOENIX CONTACT GMBH & CO KG
    Inventors: Gernot Finis, Mario Stolzenberg
  • Patent number: 11114849
    Abstract: The present invention provides both a margin of a discharge start voltage with respect to a power supply voltage and a margin of a clamp voltage with respect to a breakdown withstand voltage of an internal circuit. The semiconductor device according to the embodiment includes a first amplifier circuit for amplifying a detection signal and outputting a drive signa, a second amplifier circuit for feedback-amplifying the detection signal to be input to the first amplifier circuit, and a discharge element whose discharge capability changed according to the magnitude of the drive signal.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 7, 2021
    Assignee: RENESA.S ELECTRONICS CORPORATION
    Inventor: Koki Narita
  • Patent number: 11114845
    Abstract: An adapter system for protection of electronics from voltage spikes induced on connected wires. Said adapter system comprises an enclosure, one or more power line connectors and a suppression elements. Two or more plug sockets comprise at least a first line socket and a neutral socket. Said first line socket connects to a first line. Said neutral socket connects to a neutral. Said adapter system is configured to connect to at least said first line with said one or more power line connectors and suppressing a portion of a power on said first line with said suppression elements.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 7, 2021
    Inventors: William Goldbach, James Moellmann, Mark Wingate
  • Patent number: 11114848
    Abstract: Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 7, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: James P. Di Sarro, Farzan Farbiz
  • Patent number: 11114850
    Abstract: An electrostatic discharge protection circuit includes a first internal circuit formed between a first power line and a first ground line, and configured to operate in a range between a first power and a first ground; a second internal circuit formed between a second power line and a second ground line, and configured to operate in a range between a second power having a level higher than the first power and a second ground; a signal line connecting an output terminal of the first internal circuit and an input terminal of the second internal circuit; and a protection circuit configured to form a bypass path for bypassing a stress due to electrostatic discharge when the electrostatic discharge occurs, between the signal line and the second ground line, to protect a semiconductor device of the second internal circuit from the electrostatic discharge.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 7, 2021
    Assignee: Silicon Works Co., Ltd.
    Inventors: Jae Min Kim, Jae Hyun Lee, Yong Nam Choi
  • Patent number: 11101799
    Abstract: An input/output driving circuit may include a pad, an open-drain driving circuit, a high-voltage protection unit and a control unit. The open-drain driving circuit may be configured to output a transmission signal to the pad. The high-voltage protection unit may be configured to input a received signal from the pad. The control unit may include a gate control logic, a transmission control logic and an inverter for controlling the open-drain driving circuit. The control unit may also include a reception control logic and a well voltage generation unit for controlling the high-voltage protection unit.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventor: Seung Ho Lee
  • Patent number: 11095286
    Abstract: A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 17, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: Adrian John Bergsma
  • Patent number: 11063427
    Abstract: Disclosed is a surge control circuit, including: an absorption circuit including an absorption element and a bypass switch which are connected in series, a switch group connected in parallel to both ends of the absorption circuit and a first control circuit electrically connected to the switch group and bypass switch respectively. Normally, the first control circuit controls the switch group and the bypass switch to turn on simultaneously, makes the current flow through the switch group; when detecting the current is greater than or equal to the first preset current value, or the current increase rate is greater than or equal to the preset current rate of change, the first control circuit controls the switch group to turn off, makes the current flow through the absorption circuit; when detecting the current is less than the second preset current value, the first control circuit controls the bypass switch to turn off.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 13, 2021
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: JianPing Ying, Wuying Li, Lifeng Qiao, Teng Liu
  • Patent number: 11056879
    Abstract: An apparatus for electrostatic discharge protection. In one embodiment, an integrated circuit (IC) includes a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event. A plurality of metal oxide semiconductor (MOS) transistors are coupled to the trigger circuit. The plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a ground conductor in response to the trigger circuit generating the trigger voltage VT. A voltage limiter circuit is also included and is configured to limit the trigger voltage VT.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 6, 2021
    Assignee: NXP USA, Inc.
    Inventors: Michael A. Stockinger, Marcin Grad, Paul Hendrik Cappon, Sjoerd Bruinsma
  • Patent number: 11043487
    Abstract: An electrostatic discharge (ESD) protection circuit (for a protected device in a semiconductor system, the protected device being coupled between a first node and a first reference voltage) includes: an ESD device coupled between the first node and the first reference voltage; a logic block including a first input and an output, the first input being coupled to a second reference voltage, and the output being coupled to an input of the ESD device and a feedback control circuit coupled between the first node and a second input of the logic block.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wan-Yen Lin, Bo-Ting Chen
  • Patent number: 11038479
    Abstract: Disclosed is an amplifier circuit for providing an output of at least 100 W, preferably of at least 200 W and most preferably of at least 250 W comprising a field effect transistor. A drain of the field effect transistor is connected with a protective feedback circuit. The protective feedback circuit is arranged to reduce an over-voltage energy at the drain of the field effect transistor if the voltage between the gate and a drain of the field effect transistor exceeds a feedback threshold voltage. Further disclosed is a radio frequency amplifier comprising an amplifier circuit, an electrical radio frequency generator comprising the radio frequency amplifier and a plasma processing system comprising an electrical radio frequency generator. Still further disclosed is a method of protecting a field effect transistor in an amplifier circuit.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 15, 2021
    Assignee: Comet AG
    Inventors: Anton Labanc, Daniel Gruner
  • Patent number: 11031777
    Abstract: An electronic apparatus is provided. The electronic apparatus according to an embodiment includes a main circuit unit, a power source supplier configured to generate power, and supply the generated power to the main circuit unit, and a surge protector disposed between the main circuit unit and the power source supplier, the surge protector being configured to, based on a surge occurring from the power source supplier, perform a clamping operation on power output from the power source supplier at a first voltage level, wherein the power source supplier is further configured to, based on the clamping operation of the surge protector at the first voltage level being stopped, perform a clamping operation on the generated power at a second voltage level greater than the first voltage level.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungyong Joo, Sunjin Park
  • Patent number: 11025053
    Abstract: A surge protection circuit protection circuit includes a first series-connected line formed by at least two TVSs connected in series. One end of the line is connected to a positive terminal, and another is connected to a negative terminal. A second series-connected line is formed by at least one TSS. One end is connected between the at least two TVSs in the first series-connected line, and another end is grounded. The first line is connected in parallel to a protected circuit. When a differential-mode surge voltage appears at the ends of the first line, a voltage of a backend connection circuit is clamped to a first value. When a common-mode surge voltage appears at the two ends of the first line to the ground end, respectively, voltages to ground of the positive terminal and the negative terminal are reduced to a second value.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 1, 2021
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Eric Chemisky, Fei Huang Hu, Ling Bao Min, Yue Zhuo
  • Patent number: 11009574
    Abstract: A coil array component including an element assembly that includes a filler and a resin material, a first coil portion and a second coil portion that are embedded in the element assembly and that are composed of a first coil conductor and a second coil conductor, respectively, and four outer electrodes electrically connected to the first coil portion and the second coil portion. Also, four extension electrodes that extend from end surfaces of the element assembly to the bottom surface and are electrically connected to the outer electrodes on the bottom surface are further included. In addition, the extension electrodes are covered with insulating layers on end surfaces of the element assembly.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 18, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keiichi Yoshinaka, Katsuhisa Imada, Mitsuhiro Sato, Ryohei Kawabata
  • Patent number: 10998721
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics International N.V.
    Inventor: Radhakrishnan Sithanandam
  • Patent number: 10985747
    Abstract: The Robust Safe Switch and Control Device is an “Internet of Things” end effecter that provides a minimally dissipating, robust switch tightly integrated with circuit, life and property automated safety features. The device enables extended sensing and monitoring capabilities that enable the effective management of the “Internet of Things.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 20, 2021
    Inventor: James William Masten, Jr.
  • Patent number: 10983150
    Abstract: Various embodiments described in this disclosure pertain to methods and systems for detecting and evaluating oscillations in an electrical power grid. The oscillations can include one or more oscillatory conditions, which can occur in one or more of five predefined frequency bands. Each of the five predefined frequency bands is categorized at least in part, by oscillations that are originated by uniquely different sources. In one embodiment, an oscillation detector can be used to detect the oscillatory condition and determine a magnitude characteristic, a phase characteristic, and/or a damping characteristic of at least one oscillation frequency that contributes to the oscillatory condition.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 20, 2021
    Assignee: General Electric Technology GmbH
    Inventors: Zhiying Zhang, Ilia Voloh, Mark Gerard Adamiak
  • Patent number: 10971489
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Patent number: 10970610
    Abstract: In an impedance matching circuit, first to fourth inductors are formed by a conductor pattern of a coil shape, and a fifth inductor is formed by a conductor pattern of an unwound shape. The first inductor and the third inductor are respectively formed in different layers of a substrate and are arranged in such a relationship as to have coil openings overlapping each other. Moreover, the second inductor and the fourth inductor are respectively formed in different layers of the substrate and are arranged in such a relationship as to have coil openings overlapping each other. Two coils interposing the mounting position of the RFIC are in a 180° rotational symmetry relationship.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 6, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noriyuki Ueki, Hirokazu Yazaki, Yoshihiro Aoyama
  • Patent number: 10958125
    Abstract: A circuit board to be mounted in a non-drive end shield of an electric motor has a converter formed on the circuit board. The circuit board is divided into a central region and a number of toothed regions surrounding the central region, wherein planes of the toothed regions are bent with respect to a plane of the central region in a mounting position.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: March 23, 2021
    Assignee: Lenze Drives GmbH
    Inventors: Jan Wettlaufer, Karsten Huebner, Martin Ehlich
  • Patent number: 10950597
    Abstract: The present disclosure relates to the field of integrated circuits protection, and specifically discloses an electrostatic protection circuit and a semiconductor structure. The electrostatic protection circuit is disposed between a first port and a second port that require electrostatic protection, comprising at least one interdigital loop and a control circuit electrically connected to the interdigital loop. The interdigital loop comprises an electrostatic protection transistor having a drain electrically connected to the first port and a source electrically connected to the second port. The control circuit comprises a first transistor and a second transistor. The drain of the first transistor and the gate of the second transistor are electrically connected to the first port. The drain of the second transistor and the gate of the first transistor are electrically connected to the second port.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 16, 2021
    Inventors: Mingliang Li, Xiaoming Hu