Abstract: An apparatus may include a regulated power converter, a control engine configured to control the regulated power converter based upon a regulation control parameter, a period detection system and a parameter control system. The period detection system may be configured to monitor a signal to detect transient events at an output of the regulated power converter, wherein the transient events include a first transient event and a second transient event after the first transient event. The period detection system may be configured to determine, in response to the second transient event, a transient event period between the first transient event and the second transient event. The period detection system may be configured to determine transient event period information based upon the transient event period. The parameter control system may be configured to set the regulation control parameter to a value determined based upon the transient event period information.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection network for a chip. The chip includes a first power supply pad, a second power supply pad, and a ground pad. The ESD protection network includes: a first ESD protection circuit, located between the first power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the first power supply pad; a second ESD protection circuit, located between the second power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the second power supply pad; and a third ESD protection circuit, configured to provide a discharge path for an electrostatic charge between the first power supply pad and the second power supply pad.

Abstract: In some embodiments, an electrical device can include a body having a shape that extends along a longitudinal direction, and a set of electrodes implemented on the body at different locations along the longitudinal direction and configured to allow the electrical device to be positioned and mounted to a surface. The set of electrodes can include first and second electrodes configured to provide first and second engagements with the surface, respectively, and to allow a settling motion when the electrical device is positioned on the surface. The set of electrodes can further include a selected electrode having a side configured to allow the settling motion and an engagement portion configured to stop the settling motion and thereby provide a third engagement with the surface.

Abstract: In an embodiment, a HEMT is formed to have a main transistor having a main active area and a sense transistor having a sense active area. An embodiment may include that the main active area is isolated from the sense active area.

Abstract: A low-side contactor coil drive circuit can include an input line and a first solid state switch having a first switch base, a first switch collector, and a first switch emitter. The first switch collector can be connected to the input line and the first switch emitter is connected to ground. The circuit can include a second solid state switch having a second switch base, a second switch collector, and a second switch emitter. The second switch emitter can be connected to the input line in parallel with the first switch collector. The second switch collector can be connected to the first switch base. The circuit can include a third solid state switch having a third switch gate, a third switch source, and a third switch drain. The third switch drain can be connected to the second switch base.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

Abstract: An electrical plug provides protection against electrical surges with a replaceable surge protector cartridge that is readily removable and replaceable along an exterior of the plug. Surge protector circuitry in the cartridge can absorb an electrical surge received at the plug from an electrical mains source, and the electrical plug can maintain electrical continuity from plug prongs to an electrical cord both before and after the surge protector has absorbed an electrical surge.

Abstract: An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.

Abstract: An input/output driving circuit may include a pad, an open-drain driving circuit, a high-voltage protection unit and a control unit. The pad is for transmitting and receiving signals. The open-drain driving circuit may output a transmission signal to the pad. The high-voltage protection unit may input a received signal from the pad. The control unit may control the open-drain driving circuit and the high-voltage protection unit. The control unit may include a gate control logic, a transmission control logic and an inverter. The gate control logic may receive a voltage of the pad and output a feedback voltage to the open-drain driving circuit. The transmission control logic may receive a clock signal and an enable signal, and transfer a first control signal to the open-drain driving circuit. The inverter may invert the enable signal and transfer an inverted enable signal to the gate control logic.

Abstract: An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.

Abstract: Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.

Abstract: A protection device configured for being electrically connected to a test tap of a HV bushing for protecting the bushing from transient overvoltages. The protection device includes at least two parallel connected protection branches connected between the test tap and a ground connector configured for connecting to ground. Each of the protection branches includes a plurality of parallel connected gas discharge tubes, a Transient-Voltage-Suppression (TVS) diode connected in series with the gas discharge tubes, and a resistor connected in series with the gas discharge tubes and across the TVS diode.

Abstract: An ESD clamp circuit has an ESD detection circuit connected between a first terminal and a second terminal, with a first output node and a second output node. The ESD detection circuit is configured to output respective first and second control signals at the first and second output nodes in response to an ESD event. A discharge circuit includes a p-type transistor having a source, a drain and a gate, with the gate connected to the first output node. An n-type transistor has a source, a drain and a gate, with the gate connected to the second output node. The drain is connected to the drain of the p-type transistor. The discharge circuit is configured to establish a first ESD discharge path from the first terminal, through the p-type transistor and the n-type transistor, to the second terminal, and to further establish a second ESD discharge path in parallel with the first ESD discharge path. The second ESD discharge path includes a parasitic silicon controlled rectifier (SCR).

Abstract: A first overvoltage protection and reporting system comprises input and output transceivers and input and output surge protection devices coupled respectively to the input and output transceivers. The input surge protection device includes first and second gas discharge tubes coupled to the input transceiver only at, respectively, a first input and a second input. The output surge protection device includes third and fourth gas discharge tubes coupled to the output transceiver only at, respectively, a first and a second output. A second overvoltage protection and reporting system comprises input and output transceivers, a processor coupled between the input and output transceivers, and an output surge protection system that includes a surge protection device coupled to the output transceiver and a sensor receiver coupled between the output transceiver and the processor. The processor detects a failure of the surge protection device based on a signal received from the sensor receiver.

Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.

Abstract: Disclosed are an electrostatic protection circuit, a display substrate and a display apparatus. The electrostatic protection circuit includes: a plurality of first transistors (11) on a base substrate, each of which includes a gate, an active layer (112), a first electrode (113), a second electrode (114) and a connection part (115). Gates of the first transistors (11) are connected to each other to form a control line (12). The first electrode (113) of each first transistor (11) is electrically connected to a panel crack detect line (PL), the connection part (115) is connected between the first electrode (113) and the second electrode (114), and the active layer (112) and the gate of each first transistor (11) are arranged in an overlapping manner and insulated and separated from each other to form a first capacitor. The control line (12) is electrically connected to a first power supply line (VSS).

Abstract: A voltage converter delivers an output voltage between a first and a second node. The voltage converter includes a capacitor series-coupled with a resistor between the first and second nodes. The resistor is coupled in parallel with a bidirectional switch receiving at its control terminal a positive bias voltage referenced to the second node.

Abstract: According to one embodiment, an integrated circuit includes a first power supply line, a protection circuit, an internal circuit, a second transistor, and a shutoff control circuit. A first power supply voltage is supplied to the first power supply line. The protection circuit is connected to the first power supply line. The internal circuit includes a first transistor whose breakdown voltage is lower than the first power supply voltage. A drain or a source of the first transistor is connected to the first power supply line. The second transistor is on the first power supply line between the protection circuit and the internal circuit and is configured to switch between conduction and non-conduction states to connect and disconnect the protection circuit and the internal circuit from one another along the first power supply line. The shutoff control circuit is configured to turn off the second transistor during an ESD operation.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: This invention relates to the technical field of harmonic elimination for ferromagnetic resonance for a voltage transformer (abbreviated as PT), in particular, to a harmonic elimination method for ferromagnetic resonance for an active resistance-matching voltage transformer based on PID-adjustment, including compiling a resistance matching algorithm; designing and building a harmonic elimination control system based on the PID control strategy; presetting an active resistance-matching strategy; designing an engineering scheme for placing resistors.

Abstract: In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

Abstract: The invention relates to a protection for a semi-conductor switch against over voltages. A capacitive element is provided on an inlet connection of the semi-conductor switch. The load amount, which flows into said capacitive element, is integrated in order to trigger a protection function when a threshold value is exceeded.

Abstract: An output circuit included in an integrated circuit may employ multiple protection circuits to protect driver devices from damage during an electrostatic discharge event. One protection circuit clamps a signal port to a ground supply node upon detection of the electrostatic discharge event. Another protection circuit increases the voltage level of a control terminal to one of the driver devices during the electrostatic discharge event to reduce the voltage across the driver device and prevent damage to the device.

Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P? closer to insulator layer).

Abstract: A multi-stage surge protection device protects against complex, time-variant voltage transients, including those resulting from a high-altitude nuclear electromagnetic pulse or a solar coronal mass ejection. The transient voltage suppressor limits the let-through voltage to a clamping level and provides indication to the crowbar circuit when it is no longer able to do so. Once the clamping level is no longer able to be maintained, the crowbar circuit draws enough current to trip an upstream protective device, such as a breaker or fuse. A low-pass filter can be added to significantly lower the let-through voltage of the device for short-duration pulses, and help to spread the energy to more effectively utilize the transient voltage suppressor.

Abstract: The present invention is a spark gap protection capable of integrating into multiple layer semiconductor substrate packaging. The initial gap in the spark gap is solid and it can be converted into air, meaning gaseous, and the air gap is achieved by having the gap initially be filled with a solid and then running a voltage through the spark gap so that the gap explodes and the solid is replaced by an air cavity.

Abstract: A control system includes a secondary battery protection apparatus and a device. The secondary battery protection apparatus includes one or more monitoring terminals each provided in a path different from power paths, each monitoring terminal being operable for monitoring a potential at a negative electrode of a given secondary battery cell among a plurality of the secondary battery cells. The secondary battery protection apparatus includes one or more internal switches each of which is provided in an internal line between the negative electrode of a given secondary battery cell and a given monitoring terminal. The device includes a balance control circuit that adjusts, based on potentials monitored by the monitoring terminals, a current flowing into a line path that includes a corresponding internal line. The balance control circuit controls balance among the cell voltages for the secondary battery cells, based on the adjusted current.

Abstract: A surge protection apparatus is disclosed. The surge protection apparatus includes a housing; electronics contained in the housing; and a plurality of metal tabs electrically connected to the electronics, the metal tabs being configured to connect to a terminal block of a relay panel in a substation, the metal tabs electrically connecting the terminal block to the electronics to provide EMP surge protection to the relay panel.

Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

Abstract: A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically connected to the antenna pad and extending in a first direction, the first direction is parallel to a major axis of the TSV. The semiconductor device includes a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell.

Abstract: A motor-drive system may include a rectifier, a metal-oxide varistor (MOV) assembly, and an inverter. The rectifier may generate a direct current (DC) voltage based on a first voltage received from at least one supply voltage line coupled to a voltage source. The MOV assembly may include at least two metal-oxide varistors (MOVs) respectively coupled to the at least one supply voltage lines. The MOV assembly may couple between the voltage source and the rectifier. The motor-drive system may also include a permanently-installed jumper to couple at least one MOV of the at least two MOVs of the MOV assembly to a system ground. The inverter of the motor-drive system may convert the DC voltage to an alternating current (AC) voltage, which may be provided to a load of the motor-drive system.

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Abstract: An electronic device and an antenna feeding device are provided. The electronic device includes a metal housing, a radiation element, a substrate, a grounding element and an electrostatic protection element. The antenna feeding device includes a substrate, a grounding element, and an electrostatic protection element. The radiation element is arranged along the edge of the electronic device, and the radiation element and the metal housing are separated from each other. The substrate is arranged on the metal housing. The substrate includes a feeding portion and a grounding portion, and the feeding portion is coupled to the radiating element. The grounding portion is coupled to the metal housing. The grounding element is electrically connected to the metal housing, and the grounding element is coupled to the grounding portion. The electrostatic protection element is electrically connected between the feeding portion and the grounding portion.

Abstract: An electrostatic discharge clamp is shown, which includes a clamping circuit, a driving circuit, a capacitor and resistor network, and a bias circuit. The clamping circuit has a plurality of transistors connected in a cascode configuration. The driving circuit is coupled to the gates of the transistors of the clamping circuit. The capacitor and resistor network introduces an RC delay in response to an electrostatic discharge event to control the driving circuit to turn on the transistors of the clamping circuit for electrostatic discharging. The bias circuit biases the driving circuit to turn off the transistors of the clamping circuit when the capacitor and resistor network does not detect the electrostatic discharge event.

Abstract: An electrical over stress protection device is provided. A detection circuit detects an input voltage from a pad, provides a first discharge path when the input voltage is higher than a preset voltage, and provides a turn-on voltage to a discharge protection circuit to control the discharge protection circuit to provide at least one second discharge path.

Abstract: An integrated circuit with a hot-plug protection circuit includes input pins and an output pin. The input pins are electrically coupled to a common node in the hot-plug protection circuit via respective electrical connections. The integrated circuit includes clamping circuitry coupled between the common node and the output pin, the clamping circuitry activatable as a result of a voltage spike applied across the clamping circuitry. The plurality of electrical connections and the clamping circuitry provide respective current discharge paths between the input pins in the input pins and the output pin, the respective current discharge paths configured to become conductive as a result of a voltage spike applied to any of the input pins in the plurality of input pins being transferred to the common node via the respective electrical connection in the plurality of electrical connections electrically coupling said any of said input pins to the common node.

Abstract: The present disclosure provides an electrostatic discharge protection circuit, a chip including a first pad and a second pad. The electrostatic discharge protection circuit includes a trigger unit and a discharge transistor. The trigger unit is connected between the first pad and the second pad, provided with a trigger terminal, and configured to generate a trigger signal when there is an electrostatic pulse on the first pad. The first pad is connected to a first voltage, the second pad is connected to a second voltage, and the first voltage is greater than the second voltage. The discharge transistor has a first terminal connected to the first pad, and a second terminal connected to the second pad, and discharges an electrostatic charge to the second pad when triggered by the trigger signal.

Abstract: A wind turbine (10) is disclosed having a hub (14) with electrical power therein and at least one blade (20) attached to the hub. The blade (20) has a blade root (21), a blade tip (26) and a down-wire (30) for the conduction of lightning current to the ground. The wind turbine (10) further has a blade electrical system (99) that takes electrical power from the hub (14) and transmits electrical power into the blade (20) to at least one area located between the blade root (21) and the blade tip (26). The blade electrical system (99) if formed by a power-transfer unit (100) having a power-driver unit (110), a power-conditioner unit (130) and a dielectric (120) separating the power-driver unit (110) and the power-conditioner unit (130). The power-driver unit (110) receives electrical power from the hub (14) and transmit the electrical power through the dielectric (120) to the power-conditioner unit (130).

Abstract: A new and improved intrinsically safe barrier (“ISB”) provides advantages in connection with installation of field equipment in hazardous areas including Division 2/Zone 2 areas. In one embodiment the new ISB provides a pluggable/unpluggable ISB for use with a receiving terminal base adapted for individual field mounting and alternatively for use with a circuit mount terminal base to permit direct mounting of ISB on circuit boards. A highly effective heat sink design and potting material allows for heat dissipation to allow the ISB to serve a wider range of applications.

Abstract: An Electrostatic Discharge (ESD) protection circuit includes a first discharge path and a second discharge path. The first discharge path is located between a first potential terminal and a second potential terminal. The second discharge path is located between the first potential terminal and the second potential terminal, and is connected to the first discharge path in parallel. The first discharge path and the second discharge path are used for discharging electrostatic charges. At least one of the first discharge path and the second discharge path includes a Silicon Controlled Rectifier (SCR).

Abstract: An apparatus includes a controller configured to generate a PWM signal for controlling a power switch of a forward converter, a bias switch and a bias capacitor connected in series and coupled to a bias winding of the forward converter, and a comparator having a first input connected to the bias capacitor, a second input connected to a predetermined reference and an output configured to generate a signal for controlling the bias switch to allow a magnetizing current from the bias winding to charge the bias capacitor when a voltage across the bias capacitor is less than the predetermined reference.

Abstract: An electro-static discharge (ESD) protection circuit is electrically connected to a first pad and a second pad. The ESD protection circuit includes an ESD transistor having a control terminal, a first terminal electrically connected to the first pad, a second terminal electrically connected to the second pad, and a substrate end; and an electro-static pulse detection circuit having an upper terminal electrically connected to the first pad, a lower terminal electrically connected to the second pad, and an output terminal electrically connected to the control terminal and the substrate end of the ESD transistor.

Abstract: Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.

Abstract: A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.

Abstract: A property power system can include multiple photovoltaic (PV) panels to generate DC electrical energy from solar energy and a first power conversion module to convert between DC and AC electrical energy and to control aspects of each PV panel. The property power system can have a group of battery blades to store electrical energy and another power conversion module to convert between DC and AC electrical energy and to control aspects of each battery blade. The property power system can have a multiple synchronization interfaces configured to aggregate the AC electrical energy of each of the PV panels/battery blades, respectively, and to control delivery of the aggregated AC electrical energy. The property power system can include a grid circuit disconnector to prevent back-feed of power during grid outage condition while the PV panels or the group of battery blades is powering an electrical load center of the property.

Abstract: The present invention relates to an electrostatic protection circuit for protecting an internal circuit. The electrostatic protection circuit includes: a first circuit connected between a power pad and an input pad and configured to discharge a first electrostatic current; a second circuit connected between the input pad and a ground pad and configured to discharge a second electrostatic current; a third circuit connected between the power pad and the input pad and configured to discharge a third electrostatic current; a fourth circuit connected between the power pad and the ground pad and configured to discharge a fourth electrostatic current; a fifth circuit connected between the input pad and the ground pad and configured to discharge a fifth electrostatic current; and a sixth circuit connected between the ground pad and the power pad and configured to discharge a sixth electrostatic current.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

Abstract: A method of administering insulin includes receiving blood glucose measurements of a patient at a data processing device from a glucometer. Each blood glucose measurement is separated by a time interval and includes a blood glucose time associated with a time of measuring the blood glucose measurement. The method also includes receiving patient information at the data processing device and selecting a subcutaneous insulin treatment for tube-fed patients from a collection of subcutaneous insulin treatments. The selection is based on the blood glucose measurements and the patient information. The subcutaneous insulin treatment program for tube-fed patients determines recommended insulin doses based on the blood glucose times. The method also includes executing, using the data processing device, the selected subcutaneous insulin treatment.

Abstract: The present application provides a surge protection circuit, a lightning protector and an electronic device. The surge protection circuit includes a first protection module, the first protection module comprises a first protection sub-module and a second protection sub-module electrically connected to the first protection sub-module. The first protection sub-module is used for surge protection during a first surge input, the second protection sub-module is used for surge protection during a second surge input protection, and the second surge strength is higher than the strength of the first surge. The surge protection circuit, lightning protection and electronic equipment could provide different levels of surge protection for different levels of surge and could greatly enhance the sensitivity of lightning protection.

Abstract: A system may include a power source, a power converter having an input coupled to the power source and an output for supplying electrical energy to a load, and a control circuit for controlling operation of the power converter. The control circuit may include a first feedback control subsystem configured to monitor an output voltage present at the output of the power converter and regulate the output voltage at or about a predetermined regulated voltage level in a normal mode of operation of the power converter and a second feedback control subsystem configured to monitor an input voltage present between the power source and the input of the power converter and responsive to the input voltage decreasing below a predetermined minimum voltage level, causing the power converter to operate in a protection mode of operation in order to maintain the input voltage at or about the predetermined minimum voltage level.