Transient Responsive Patents (Class 361/111)
  • Patent number: 11031777
    Abstract: An electronic apparatus is provided. The electronic apparatus according to an embodiment includes a main circuit unit, a power source supplier configured to generate power, and supply the generated power to the main circuit unit, and a surge protector disposed between the main circuit unit and the power source supplier, the surge protector being configured to, based on a surge occurring from the power source supplier, perform a clamping operation on power output from the power source supplier at a first voltage level, wherein the power source supplier is further configured to, based on the clamping operation of the surge protector at the first voltage level being stopped, perform a clamping operation on the generated power at a second voltage level greater than the first voltage level.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungyong Joo, Sunjin Park
  • Patent number: 11025053
    Abstract: A surge protection circuit protection circuit includes a first series-connected line formed by at least two TVSs connected in series. One end of the line is connected to a positive terminal, and another is connected to a negative terminal. A second series-connected line is formed by at least one TSS. One end is connected between the at least two TVSs in the first series-connected line, and another end is grounded. The first line is connected in parallel to a protected circuit. When a differential-mode surge voltage appears at the ends of the first line, a voltage of a backend connection circuit is clamped to a first value. When a common-mode surge voltage appears at the two ends of the first line to the ground end, respectively, voltages to ground of the positive terminal and the negative terminal are reduced to a second value.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 1, 2021
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Eric Chemisky, Fei Huang Hu, Ling Bao Min, Yue Zhuo
  • Patent number: 11009574
    Abstract: A coil array component including an element assembly that includes a filler and a resin material, a first coil portion and a second coil portion that are embedded in the element assembly and that are composed of a first coil conductor and a second coil conductor, respectively, and four outer electrodes electrically connected to the first coil portion and the second coil portion. Also, four extension electrodes that extend from end surfaces of the element assembly to the bottom surface and are electrically connected to the outer electrodes on the bottom surface are further included. In addition, the extension electrodes are covered with insulating layers on end surfaces of the element assembly.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 18, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keiichi Yoshinaka, Katsuhisa Imada, Mitsuhiro Sato, Ryohei Kawabata
  • Patent number: 10998721
    Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics International N.V.
    Inventor: Radhakrishnan Sithanandam
  • Patent number: 10983150
    Abstract: Various embodiments described in this disclosure pertain to methods and systems for detecting and evaluating oscillations in an electrical power grid. The oscillations can include one or more oscillatory conditions, which can occur in one or more of five predefined frequency bands. Each of the five predefined frequency bands is categorized at least in part, by oscillations that are originated by uniquely different sources. In one embodiment, an oscillation detector can be used to detect the oscillatory condition and determine a magnitude characteristic, a phase characteristic, and/or a damping characteristic of at least one oscillation frequency that contributes to the oscillatory condition.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 20, 2021
    Assignee: General Electric Technology GmbH
    Inventors: Zhiying Zhang, Ilia Voloh, Mark Gerard Adamiak
  • Patent number: 10985747
    Abstract: The Robust Safe Switch and Control Device is an “Internet of Things” end effecter that provides a minimally dissipating, robust switch tightly integrated with circuit, life and property automated safety features. The device enables extended sensing and monitoring capabilities that enable the effective management of the “Internet of Things.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 20, 2021
    Inventor: James William Masten, Jr.
  • Patent number: 10971489
    Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics SA
    Inventor: Johan Bourgeat
  • Patent number: 10970610
    Abstract: In an impedance matching circuit, first to fourth inductors are formed by a conductor pattern of a coil shape, and a fifth inductor is formed by a conductor pattern of an unwound shape. The first inductor and the third inductor are respectively formed in different layers of a substrate and are arranged in such a relationship as to have coil openings overlapping each other. Moreover, the second inductor and the fourth inductor are respectively formed in different layers of the substrate and are arranged in such a relationship as to have coil openings overlapping each other. Two coils interposing the mounting position of the RFIC are in a 180° rotational symmetry relationship.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 6, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noriyuki Ueki, Hirokazu Yazaki, Yoshihiro Aoyama
  • Patent number: 10958125
    Abstract: A circuit board to be mounted in a non-drive end shield of an electric motor has a converter formed on the circuit board. The circuit board is divided into a central region and a number of toothed regions surrounding the central region, wherein planes of the toothed regions are bent with respect to a plane of the central region in a mounting position.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: March 23, 2021
    Assignee: Lenze Drives GmbH
    Inventors: Jan Wettlaufer, Karsten Huebner, Martin Ehlich
  • Patent number: 10950597
    Abstract: The present disclosure relates to the field of integrated circuits protection, and specifically discloses an electrostatic protection circuit and a semiconductor structure. The electrostatic protection circuit is disposed between a first port and a second port that require electrostatic protection, comprising at least one interdigital loop and a control circuit electrically connected to the interdigital loop. The interdigital loop comprises an electrostatic protection transistor having a drain electrically connected to the first port and a source electrically connected to the second port. The control circuit comprises a first transistor and a second transistor. The drain of the first transistor and the gate of the second transistor are electrically connected to the first port. The drain of the second transistor and the gate of the first transistor are electrically connected to the second port.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 16, 2021
    Inventors: Mingliang Li, Xiaoming Hu
  • Patent number: 10944257
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 9, 2021
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan Sithanandam, Divya Agarwal, Jean Jimenez, Malathi Kar
  • Patent number: 10944258
    Abstract: An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 9, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Wei Lai, Yun-Jen Ting, Yi-Han Wu, Kun-Hsin Lin, Hsin-Kun Hsu
  • Patent number: 10916939
    Abstract: Transient overvoltage suppression is provided by discharging through a Metal Oxide Varistor (MOV) and Silicon Controlled Rectifier (SCR) which are connected in series between power supply lines. The SCR has a gate that receives a trigger signal generated by a triggering circuit coupled to the power supply lines. A trigger voltage of the triggering circuit is set by a Transil™ avalanche diode.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: February 9, 2021
    Assignees: STMicroelectronics (Tours) SAS, STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Romain Pichon, Yannick Hague, Sean Choi
  • Patent number: 10897131
    Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: January 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Cheng Liao, Ting-Yao Lin, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 10892756
    Abstract: A DPI circuit reduces noise effects in an ESD circuit when coupled between an ESD circuit and a protected pin. The DPI circuit includes an NMOS transistor coupled between an output node and a lower rail and a charge pump coupled between the input node and the gate of the first NMOS transistor. A resistor is coupled between the gate of the first NMOS transistor and the lower rail.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 12, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Benjamin Lee Arney, Sigfredo Emanuel González Díaz
  • Patent number: 10877530
    Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Tessil Thomas, Robin A. Steinbrecher, Sandeep Ahuja, Michael Berktold, Timothy Y. Kam, Howard Chin, Phani Kumar Kandula, Krishnakanth V. Sistla
  • Patent number: 10868424
    Abstract: The present invention provides a chip comprising a circuit module, a power switch and a detection and control circuit. The power switch is coupled between a supply voltage and the circuit module, and is used to selectively connect the supply voltage to the circuit module, and control a current amount flowing into the circuit module according to at least a control signal. The detection and control circuit is coupled to the power switch, and is used to detect a first signal generated by a first circuit positioned surrounding the circuit module, and compare the first signal with a second signal in a real-time manner to generate the control signal to adjust the current amount flowing into the circuit module.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 15, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Cheng-Kai Huang
  • Patent number: 10862296
    Abstract: The present invention relates to an apparatus and a method for protecting a MOSFET relay by using a voltage detector and a signal fuse, which calculate a detection voltage value through a voltage detector from an electrically conducted current value of a MOSFET relay provided in a battery main circuit for a vehicle and pre-block current applied to the MOSFET relay by operating a signal fuse when the calculated voltage value is more than a predetermined threshold to protect the MOSFET relay from being burned.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 8, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hyeon Jin Song, Chang Bog Lee, Yanglim Choi
  • Patent number: 10861845
    Abstract: In certain configurations, an input/output (IO) interface of a semiconductor chip includes a pin, an interface switch connected to the pin, and an overstress detection and active control circuit that controls a resistance of the interface switch with active feedback. The overstress detection and active control circuit increases a resistance of the interface switch in response to detection of a transient overstress event between a first node and a second node. Accordingly, the overstress detection and active control circuit provides separate detection and logic control to selectively modify the resistance of the interface switch such that the interface switch operates with low resistance during normal operating conditions and with high resistance during overstress conditions.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 8, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 10862300
    Abstract: A DC power distribution system includes a plurality of power sources and a DC power distribution bus having a plurality of DC bus sections. At least one power source is coupled to each of the DC bus sections. One or more power switching assemblies couple one of the DC bus sections to another. The power switching assembly has first and second terminals, the first terminal being electrically coupled to a first bus section and the second terminal being electrically coupled to a second bus section. First and second semiconductor devices are electrically coupled between the first and second terminal to control current flow between the first terminal and the second terminal. At least one power switching assembly further includes a pair of current limiters coupled between the first and second semiconductor devices and an energy store is coupled to that power switching assembly between the pair of current limiters.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: December 8, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventor: Espen Haugan
  • Patent number: 10855091
    Abstract: In one aspect, an electronic apparatus may include a base and an electrode. In one embodiment, the electrode can be cylindrical with a threaded portion on top of the electrode, and the threaded portion can be used to secure another electronic device with corresponding threads. For example, the electrode can be used to connect with a camera having an electrode and a corresponding threaded portion. More specifically, the camera can be secured on the electrode through the threaded portions and when the camera is fully secured on the electrode, the electrode can be in contact with the electrode to electrically connect with the camera.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 1, 2020
    Inventor: Shou Qiang Zhu
  • Patent number: 10826290
    Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, the ESD protection circuit is connected between a VDD rail and a VSS rail and includes an internal floating ESD rail located between the VDD rail and the VSS rail, I/O pins connected between the internal floating ESD rail and the VSS rail, ESD diodes corresponding to at least one I/O pin, an internal bias cell corresponding to an I/O pin and configured to short the corresponding I/O pin to the internal floating ESD rail when the I/O pin is pulled high, and an internal bias cell corresponding to a VDD pin of the VDD rail and configured to short the VDD rail to the internal floating ESD rail when the VDD pin is pulled high.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Gijs Jan de Raad, Madan Mohan Reddy Vemula
  • Patent number: 10825767
    Abstract: A semiconductor packaging structure for packaging a semiconductor chip is disclosed, the semiconductor chip comprises at least two electrodes, each of the at least two electrodes comprises at least one electrode opening, and the packaging structure comprises: a packaging chassis, provided with at least two pin electrodes respectively corresponding to the at least two electrodes; and at least two extended electrodes, each of the at least two extended electrodes being electrically connected to one of the at least two pin electrodes, and comprising at least one conductive pillar for inserting into the at least one electrode opening formed on one of the at least two electrodes.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: November 3, 2020
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventor: Shufeng Zhao
  • Patent number: 10818653
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 27, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Shang-Chuan Pai, Wei-Chung Wu, Szu-Chi Chen, Sheng-Chih Chuang, Yin-Ting Lin, Pei-Chun Yu, Han-Pei Liu, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
  • Patent number: 10811954
    Abstract: A surge protective apparatus of a power conversion circuit includes an AC-to-DC conversion circuit and two voltage clamping units. The AC-to-DC conversion circuit receives an AC power source and converts the AC power source into a DC power source. The DC power source is provided between a positive output terminal and a negative output terminal of the AC-to-DC conversion circuit. Two first ends of the two voltage clamping units are respectively coupled to a first AC terminal and a second AC terminal of the AC power source, and two second ends of the two voltage clamping units are commonly coupled to the positive output terminal or the negative output terminal. Accordingly, it is to effectively suppress surge energy generated from the AC power source.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 20, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Chia-Hsien Chu
  • Patent number: 10784672
    Abstract: A circuit interrupter including a line conductor, a neutral conductor, separable contacts, an operating mechanism structured to trip open the separable contacts, a magnetic trip actuator structured to cause the operating mechanism to trip open the separable contacts in response to a short-circuit between the line and neutral conductors, a protection circuit including a self-test circuit structured to perform a self-test and to output a signal in response to failing the self-test, and an electrical component electrically connected between the line and neutral conductors and having an open state and a closed state. The electrical component is structured to switch from the open state to the closed state and cause a short-circuit between the line and neutral conductors in response to receiving the signal from the self-test circuit.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 22, 2020
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Jason Kohei Arthur Okerman, Andrew William Courson
  • Patent number: 10784807
    Abstract: A method and a parameter estimation system are provided for controlling an electrical machine, (e.g., an induction motor), powered by a drive unit. The method and the parameter estimation system disclosed herein detect a travelling wave generated on a linking element disposed between a first connection point, which is at least one terminal of the electrical machine, and a second connection point, which is at least one terminal of the drive unit. Further, the method and the parameter estimation system disclosed herein obtain at least one of a plurality of wave characteristics associated with the travelling wave, (e.g., an amplitude, a width, a frequency, a travel time of the travelling wave). Further, the method and the parameter estimation system disclosed herein determine one or more control parameters, (e.g., an operational torque and speed), of the electrical machine based on at least one of the wave characteristics.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: September 22, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventors: Suryanarayana Bhamidipati, Siraj Issani, Anand Venkatramani
  • Patent number: 10784679
    Abstract: This application discloses an electrostatic discharge protection apparatus and an integrated circuit with multiple power domains. The electrostatic discharge protection apparatus includes a diode and an NMOS transistor. A positive electrode of the diode is coupled to a first interface, a negative electrode of the diode is coupled to a first electrode of the NMOS transistor, both a second electrode of the NMOS transistor and a gate electrode of the NMOS transistor are coupled to a second interface, and a substrate of the NMOS transistor is used for grounding. At least one electrostatic discharge protection apparatus may be disposed in the integrated circuit with multiple power domains.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 22, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mei Li, Bingwu Ji, Yu Xia
  • Patent number: 10777547
    Abstract: Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shu-Yu Su, Jam-Wem Lee, Wun-Jie Lin
  • Patent number: 10763663
    Abstract: The present application is directed to a three phase power transmission system including a first conductor line, a second conductor line and a third conductor line. One or more sensors are configured to detect traveling waves in each of the first second and third conductors. A controller is configured to receive data transmitted by the one or more sensors and determine which of the traveling modal waves is a first metallic mode wave (MM1), a second metallic mode (MM2) wave and/or a ground mode (GM0) wave. The controller is operable to determine which of the conductor lines are faulted based on detection of one or more of MM1 waves, MM2 waves and/or GM0 waves.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 1, 2020
    Assignee: ABB Power Grids Switzerland AG
    Inventor: Reynaldo Nuqui
  • Patent number: 10763855
    Abstract: A circuit includes a high voltage (HV) transistor having a first current electrode, a second current electrode, and a control electrode coupled to receive a control signal. The HV transistor is configured and arranged to be non-conductive when the control signal is at a first state and conductive when the control signal is at a second state. A low voltage (LV) transistor is coupled to the first current electrode of the HV transistor. An HV pad is coupled to the second current electrode of the HV transistor. An operating voltage rating of the HV pad exceeds an operating voltage rating of the LV transistor. A secondary electrostatic discharge protection device is coupled between the second current electrode of the HV transistor and a voltage supply terminal.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP USA, INC.
    Inventors: Ashutosh Jain, Michael A Stockinger, Stefano Pietri, Jaideep Banerjee, Ateet Omer
  • Patent number: 10763852
    Abstract: A switch having a drain, a source, and a control. The switch comprising a depletion-mode transistor including a first, a second, and a control terminal and an enhancement-mode transistor including a first, a second, and a control terminal. The first terminal of the depletion-mode transistor is the drain of the switch and the control of the depletion-mode transistor is coupled to the source of the switch. The control of the enhancement-mode transistor is coupled to the control of the switch, the second terminal of the enhancement-mode transistor is the source of the switch. The switch comprises a clamp circuit to clamp a voltage of the first terminal of the enhancement-mode transistor to a threshold, the clamp circuit comprises a resistor and a pn-junction device coupled between the first and second terminals of the enhancement-mode transistor and between the second terminal and the control of the depletion-mode transistor.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 1, 2020
    Assignee: Power Integrations, Inc.
    Inventors: Hartley Horwitz, Sorin Georgescu, Kuo-Chang Robert Yang
  • Patent number: 10750933
    Abstract: The disclosure extends to systems and methods for reducing the area of an image sensor by employing bi-directional pads used for both image data issuance and configuration command reception and internal supply voltage generation, for reducing the number of conductors in an endoscope system.
    Type: Grant
    Filed: March 15, 2014
    Date of Patent: August 25, 2020
    Assignee: DePuy Synthes Products, Inc.
    Inventor: Laurent Blanquart
  • Patent number: 10742025
    Abstract: A system and method for detecting and isolating an electromagnetic pulse (“EMP”) along first phase, second phase, and third phase electrical lines electrically connected to a monitored infrastructure so as to protect the monitored infrastructure, the method for detecting and isolating includes a phase unit receiving electric signal data from a sensor electrically connected individually to each of the first phase, second phase, and third phase electrical lines, respectively, upstream of and associated with the monitored infrastructure. The method includes determining if the received electric signal data associated with the respective electrical line is indicative of an E1 component of an EMP and, if so, actuating an isolation subsystem in less than 300 nanoseconds to electrically isolate the respective electrical line against electrical communication with the monitored infrastructure.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 11, 2020
    Inventors: Timothy A Carty, Gregory Wayne Clarkson
  • Patent number: 10742026
    Abstract: Aspects of the invention provide for an electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a stacked coil assembly with four ports. The electrostatic protection device further includes a human body model ESD protection circuit, a charge device model ESD protection circuit, and an impedance matching circuit. The human body model ESD protection circuit, the charge device model ESD protection circuit, and the impedance matching circuit are connected to separate ports selected from the four ports.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pier Andrea Francese, Thomas Morf
  • Patent number: 10734806
    Abstract: High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 4, 2020
    Assignee: Analog Devices, Inc.
    Inventors: James Zhao, Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 10714294
    Abstract: An emitter with a diameter of 100 nm or less is used with a protective cap layer and a diffusion barrier between the emitter and the protective cap layer. The protective cap layer is disposed on the exterior surface of the emitter. The protective cap layer includes molybdenum or iridium. The emitter can generate an electron beam. The emitter can be pulsed.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: July 14, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Frances Hill, Gildardo R. Delgado, Rudy F. Garcia, Gary V. Lopez Lopez, Michael E. Romero, Katerina Ioakeimidi, Zefram Marks
  • Patent number: 10700516
    Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit including: a first terminal configured to provide a first voltage having a first value in a normal mode; a second terminal configured to provide a second voltage having a second value in the normal mode; a detection circuit configured to provide a detection voltage according to the first and second voltages; and a protection circuit configured to operate in one of the normal mode and an ESD mode according to the detection voltage. When the difference between a value of the detection voltage and an average of the first and second values reaches a predetermined threshold, the protection circuit enters the ESD mode from the normal mode, and thereby has a first path between the first terminal and a grounding terminal and/or a second path between the second terminal and the grounding terminal be conductive for discharging abnormal energy.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 30, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chien-Ming Wu
  • Patent number: 10685928
    Abstract: A circuit device includes a first pad and a second pad that are disposed in a first pad disposition region along a first side; a third pad and a fourth pad that are disposed in a second pad disposition region along a second side which faces the first side; and a first to fourth electrostatic protection circuits that are disposed in a circuit disposition region between the first pad disposition region and the second pad disposition region and are connected to the first to fourth pads.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: June 16, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Takehiro Yamamoto, Masayuki Ishikawa
  • Patent number: 10680590
    Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 9, 2020
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
  • Patent number: 10673227
    Abstract: A system level electrostatic discharge (ESD) detection device includes a phase detection unit including at least one phase detector suitable for detecting a phase difference between a plurality of supply voltages or between a plurality of input signals; a storage unit suitable for shifting between a first and a second state, the second state indicating a phase difference detected by the phase detection unit; and an output unit suitable for outputting a system level electrostatic discharge (ESD) detection signal according to the first or second state of the storage unit.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung-Ryong Lee, Kang-Bong Seo, Ik-Seok Yang
  • Patent number: 10673187
    Abstract: An integrated component for protecting against overvoltages, including a varistor and a gas discharge tube that are connected in series between a first and a second electrical connection terminal and a peripheral coating including a seal-tight and electrically insulating resin, the peripheral coating being arranged around the varistor and the gas discharge tube so as to form a seal-tight and electrically insulating barrier that leaves the first and second electrical connection terminals accessible only at two opposite ends of the peripheral coating.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 2, 2020
    Assignee: CITEL
    Inventor: Vincent Crevenat
  • Patent number: 10659047
    Abstract: The output driving circuit include a pull-down driver, an input/output (IO) control logic, a gate control logic, and an inverter. The pull-down driver includes first, second, and third transistors that are sequentially coupled between a pad and a ground node. The IO control logic is configured to receive a clock signal and an enable signal, and transfer a first control signal to the third transistor. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the first transistor. The inverter is configured to invert the enable signal and transfer an inverted enable signal to the gate control logic. Therefore, the reliability of the output driving circuit can be improved.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Seung Ho Lee
  • Patent number: 10651641
    Abstract: A circuit includes an input terminal and a regulated supply line for supplying an electronic device with an electrostatic discharge protection and driver circuit for the electronic device. The supply line is coupled to the input terminal via the circuitry, so that current injected into the input terminal may produce a voltage increase on the regulated supply line. A comparator sensitive to the voltage at the input terminal and the voltage on the supply line is provided. A current sink coupled with the supply line and being activatable to sink current from the supply line is also provided. The comparator is configured for activating the current sink as a result of the voltage at the input terminal exceeding the voltage on the supply line of a certain intervention threshold.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 12, 2020
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Mauro Giacomini, Rajesh Narwal, Pravesh Kumar Saini
  • Patent number: 10637457
    Abstract: A method for controlling an electronic semiconductor switch connected in a load current circuit, the semiconductor switch being connected between an input terminal routed to a source and an output terminal of the load current circuit routed to a load. A control circuit is connected to a supply voltage and has a bridge circuit connected on the primary side to a transformer and to the supply voltage. A load circuit is connected to the transformer on the secondary side, the load circuit having a driver circuit for the semiconductor switch. A threshold value signal is routed to the bridge circuit on the control side. The bridge circuit generates a primary signal which is transmitted as a secondary signal to the load circuit that is galvanically isolated from the control circuit, and wherein the secondary signal is fed to the driver circuit, which generates a drive signal for the semiconductor switch.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: April 28, 2020
    Assignee: Ellenberger & Poensgen GmbH
    Inventors: Dirk Boesche, Ernst-Dieter Wilkening
  • Patent number: 10622074
    Abstract: According to an embodiment, a semiconductor storage device includes a first chip including a power supply protection circuit. The power supply protection circuit including: a resistor including a first end connected to the second pad; a first capacitor including a first end connected to a second end of the resistor; a first transistor including a first end connected to the second pad, a second end connected to a node with a signal of a value based on a voltage of the first end of the first capacitor, and a gate connected to the first pad; a first inverter including an input terminal connected to the second end of the first transistor; and a second transistor including a gate connected to an output terminal of the first inverter.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Maya Inagaki, Masaru Koyanagi
  • Patent number: 10610326
    Abstract: Markers, microwave probes, and related systems and methods are provided for localizing lesions within a patient's body, e.g., within a breast. The marker includes an energy converter e.g., one or more photodiodes, for transforming energy pulses striking the marker into electrical energy, a switch, e.g., FET, coupled to the photodiodes such that light from a probe cause the switch to open and close. A pair of antenna wires are coupled to the switch to provide an antenna, the switch configured to open and close when light strikes the photodiodes to modulate signals from the probe reflected by the antenna back to the probe to identify the location of the marker. The marker also includes an electro static discharge (ESD) protection device coupled to the switch to provide protection against an electrostatic discharge event.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: April 7, 2020
    Assignee: Cianna Medical, Inc.
    Inventors: Nikolai Rulkov, Michael John Lopez, John E. Greene
  • Patent number: 10599597
    Abstract: Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently control the first discharge circuit and the second discharge circuit to discharge the voltage on the VBUS line.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Derwin Mattos, Godwin Gerald Arulappan, Syed Raza, Anup Nayak, Sumeet Gupta, Venkat Mandagulathur
  • Patent number: 10591532
    Abstract: A semiconductor integrated circuit of the present disclosure includes: first power and second power supply lines that are coupled to a protected circuit; a third power supply line that is supplied with a voltage different from voltages supplied to the first and second power supply lines; a detection circuit that is coupled between the first and second power supply lines and detects a surge occurring in the first power supply line; an inverter circuit that includes one or more inverters coupled in series, and is coupled between the first and second power supply lines; a protection transistor that is coupled between the first and second power supply lines, and is controlled by an output of the detection circuit to cause the surge to flow through the second power supply line; and a time constant circuit that is coupled to at least the third power supply line and the protection transistor.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: March 17, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Takaaki Tatsumi
  • Patent number: 10594222
    Abstract: Described is an explosion endangered region usable, switching power supply for supplying an output voltage controlled to a desired value, comprising a supply path, which includes a switching controller controlled via a driver, a galvanically isolated transformer connected after the switching controller, and, connected after the transformer, a rectifier-containing, output circuit, and a feedback path, via which the driver is fed a signal transmitted via a light source and a light receiver and reflecting the output voltage, based on which the driver controls the output voltage to the desired value via a corresponding operation of the switching controller. The feedback path includes a voltage regulator, which regulates a supply voltage falling across the light source to a fixed value, and an electrical current regulator, which regulates an electrical current flowing through the light source to an electrical current value corresponding to the output voltage.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 17, 2020
    Assignee: Endress+Hauser SE+Co. KG
    Inventors: Simon Weidenbruch, Narcisse Michel Nzitchieu Gadeu, Max Jehle