Threshold Device (neon Tube) Patents (Class 361/200)
  • Patent number: 11096281
    Abstract: A power delivery system includes a first planar power module that is coupled to a power system and that transmits power received from the power system. A first planar power module connector is connected to the first planar power module and transmits the power received from the first planar power module. A second planar power module is connected to the first planar power module connector and transmits the power received from the first planar power module connector. A first power transmission coupling engages at least one of the first planar power module and the second planar power module, and receives the power from the at least one of the first planar power module and the second planar power module to which it is engaged, and transmits the power to a first component via a first power transmission pad coupled to the first component and engaging the first power transmission coupling.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 17, 2021
    Assignee: Dell Products L.P.
    Inventors: Xin Zhi Ma, Nan Wang
  • Patent number: 8103021
    Abstract: An audio reproducing apparatus includes a power supply, an amplifier, a speaker, and a controller. The power supply is for supplying a voltage. The amplifier is for receiving the voltage and audio signals, amplifying the audio signals, and outputting amplified audio signals. The speaker is for reproducing sound after receiving the amplified audio signals. The controller is for receiving the voltage and generating a control signal to enable the amplifier. The controller includes a generator and a delay unit. The generator is for receiving the voltage and generating the control signal. The delay unit is for delaying the time of transferring the voltage from the power supply to the generator.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: January 24, 2012
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Lung Dai, Wang-Chang Duan
  • Patent number: 7551451
    Abstract: A plasma display module including a plasma display panel (PDP) including a first substrate and a second substrate and having an alignment mark formed thereon, and a chassis supporting the PDP and having an alignment mark corresponding to the alignment mark of the PDP.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: June 23, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sok-San Kim, Tae-Kyoung Kang, Ki-Jung Kim, Myoung-Kon Kim, Won-Sung Kim
  • Patent number: 6859995
    Abstract: A new fixture which is capable of holding an HSA throughout all processes is invented so that Quasi-Static Test can be done before swaging. Handling operations are reduced and rework is made much easier. The invention further provides a process for testing the HSA by means of the fixture.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: March 1, 2005
    Assignee: Sae Magnetics (H.K.) Ltd.
    Inventors: Takehiro Kamigama, Huegung Wang, Yiusing Ho, Chunkau Leung, Waikong Cheung, Shinji Misawa, Jinsuo Sun, Wenxin Chang
  • Patent number: 6801418
    Abstract: Grounding elements are used to properly ground floor coverings and other elements whereby a floor covering, such as a carpet, need not be removed and reinstalled to correct a grounding problem. Properly grounded floor coverings and other devices reduces the effects of electrostatic discharge (ESD) and eliminates disruptive leak paths. One form of the invention has an element that is touched by a user layered on top of an ESD grounded work surface.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: October 5, 2004
    Inventor: Barry M. Epstein
  • Publication number: 20030151876
    Abstract: A new fixture which is capable of holding an HSA throughout all processes is invented so that Quasi-Static Test can be done before swaging. Handling operations are reduced and rework is made much easier. The invention further provides a process for testing the HSA by means of the fixture.
    Type: Application
    Filed: November 13, 2002
    Publication date: August 14, 2003
    Inventors: Takehiro Kamigama, Huegung Wang, Yiusing Ho, Chunkau Leung, Waikong Cheung, Shinji Misawa, Jinsuo Sun, Wenxin Chang
  • Publication number: 20020186521
    Abstract: Aluminum surface mount capacitors containing one or more anode foil coupons are initially anodized in an aqueous phosphate solution in order to produce an anodic oxide film having extreme resistance to hydration and attack by corrosive anions for the purpose of producing surface mount capacitors at high yield and of high stability.
    Type: Application
    Filed: July 12, 2002
    Publication date: December 12, 2002
    Applicant: KEMET ELECTRONICS CORPORATION
    Inventors: Philip Michael Lessner, Brian John Melody, John Tony Kinard, Erik Karlsen Reed, Albert Kennedy Harrington, Daniel F. Persico, David Alexander Wheeler
  • Publication number: 20020021543
    Abstract: A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2<V1 are present at a respective end of the selected word line/bit lines, the cell field is configured to have all of the bit/word lines set to voltages (V1+V2)/2 and to have a maximum cell voltage of ±(V1-V2)/2.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 21, 2002
    Inventors: Dietmar Gogl, Helmut Kandolf, Stefan Lammers
  • Publication number: 20020021544
    Abstract: A dielectric region, such as a ferroelectric dielectric region of an integrated circuit capacitor, is protected by a multi-layer insulation structure including a first relatively thin insulation layer, e.g., an aluminum oxide or other metal oxide layer, and a second, thicker insulating layer, e.g., a second aluminum oxide or other metal oxide layer. Before formation of the second insulation layer, the first insulation layer and the dielectric preferably annealed, which can increase a remnant polarization of the dielectric region. The first insulation layer can serve as a hydrogen diffusion barrier during formation of the second insulation layer and other overlying structures. In this manner, degradation of the dielectric can be reduced. Devices and fabrication methods are discussed.
    Type: Application
    Filed: August 7, 2001
    Publication date: February 21, 2002
    Inventors: Hag-ju Cho, Hyeong-geun An
  • Publication number: 20010055714
    Abstract: An electronic power device comprising support plates each having one face receiving one or more power components and an opposite face in contact with a cooling fluid for cooling said power components by conduction, wherein at least one support plate is associated with another support plate disposed facing it and provided with similar power components, and wherein the power components of the two facing support plates are disposed facing one another and in the immediate vicinity of one another.
    Type: Application
    Filed: May 11, 2001
    Publication date: December 27, 2001
    Applicant: ALSTOM
    Inventors: Jacques Cettour-Rose, Daniel Fellmann, Alain Petitbon
  • Publication number: 20010038519
    Abstract: An electrode material for an electrochemical capacitor having a large capacity, having a titanium oxide compound such as titanium oxide, hydrated titanium oxide or their hydrogenated products, and at least one oxidizable and reducible metal element contained in the titanium oxide compound.
    Type: Application
    Filed: May 16, 2001
    Publication date: November 8, 2001
    Applicant: Hitachi Maxell, Ltd.
    Inventors: Yoshio Takasu, Yasushi Murakami, Mitsuo Ueno, Shigeo Aoyama, Mayumi Iwagawa, Kiyoshi Sato, Seiichi Asada
  • Publication number: 20010026434
    Abstract: A configuration for connecting power semiconductor chips in modules is configured such that the power semiconductor chips are positioned in a chessboard pattern and in each case a respective function type of the power semiconductor chips is assigned to a respective “color” of the fields of the chessboard pattern.
    Type: Application
    Filed: March 12, 2001
    Publication date: October 4, 2001
    Inventor: Manfred Loddenkoetter
  • Patent number: 6116039
    Abstract: An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber; an evaporator in fluid communication with both the sorber and the condenser and connected in heat-exchange relation to the electrical component; wherein a sorbate which has been condensed in the condenser is evaporated in the evaporator, thereby absorbing heat from the electrical component, and then adsorbed onto the sorbent; an electromagnetic wave generator, a waveguide coupler for directing the electromagnetic waves to the sorbent; wherein the sorbate is desorbed from the sorbent by the electromagnetic waves and condensed in the condenser; and wherein the desorption of the sorbate from the sorbent is substantially isothermal.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: September 12, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Dennis M. Pfister, Charles M. Byrd
  • Patent number: 5854764
    Abstract: A sectorized electrically erasable and programmable non-volatile memory device comprises: a plurality of individually-addressable memory sectors, each memory sector comprising an array of memory cells arranged in rows and columns; redundancy columns of redundancy memory cells for replacing defective columns of memory cells; and a redundancy control circuit for storing addresses of the defective columns and activating respective redundancy columns when said defective columns are addressed. Each memory sector comprises at least one respective redundancy column.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: December 29, 1998
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Corrado Villa, Marco Dallabora, Fabio Tassan Caser
  • Patent number: 5696661
    Abstract: The present invention is directed to a device intended to turn on loads and keep them on for a pre-established period of time and includes a remanence relay which includes a coil L, a movable contact 1, a fixed, normally opened contact 2b and a fixed, normally closed contact 2a. When a remote push switch S is pushed to its ON position, a first current flows through the coil L in a first direction to cause the movable contact 1 to move from engagement with the contact 2b to engagement with the contact 2a. As a result, power is applied to a load 5. When the switch S is opened, a timing circuit, which includes a capacitor C1, a resistor R3, an electric disruptive device D5 and a diode D4, is initiated which charges the capacitor C1. When the voltage of the capacitor C1 reaches the threshold voltage of the disruptive device D5, a second current opposite in direction to the first current flows through the coil L to cause the movable contact to move to the contact 2b and disconnect the load 5.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: December 9, 1997
    Inventors: Marisa Barbosa Vieira, Maria Carolina Tirico Felizatti
  • Patent number: 4553850
    Abstract: A logic regulation circuit for regulating the frequency dividing ratio of a variable frequency divider of an electronic timepiece comprises a first switch group having a plurality of ON and OFF switching states representative of different frequency rates and a second switch group having a plurality of ON and OFF switching states representative of frequency rate adjustment values. A first set of memory circuits is connected to the first switch group for memorizing the ON-OFF information thereof, and a second set of memory circuits is connected to the second switch group for memorizing the ON-OFF information thereof.
    Type: Grant
    Filed: March 15, 1983
    Date of Patent: November 19, 1985
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Yosuke Kanno