Abstract: A backplane bus system and related method for increasing the throughput of cPCI-specified backplane architectures. The system includes an interposer card for transforming reflective-wave switching into incident-wave switching. Establishing incident-wave switching on the bus along with careful slot pitch and impedance layout increases the rate at which the voltage amplitude observed by all receivers connected to the bus is sufficient to produce a change of state on the first signal propagation down the bus. Most existing peripherals are configured with transceivers that produce reflective-wave switching. The present system includes an interposer card to transform that switching into incident-wave switching. A preferred transceiver for doing so and that is implemented on the interposer card is a GTLP transceiver. A state machine is employed to regulate operation of the incident-wave switching transceiver. The system may be used to permit implementation of as many as 21 slots on a conventional cPCI backplane.

Abstract: The present invention is an electronic lock having a shorting or shunt circuit designed to allow an authorized operator to open the electronic lock and which will prevent an unauthorized operator from opening the lock when authorized combination has not been entered.

Abstract: A single resonant DC charging circuit provides both the power and timing for the pedestal insertion is, likewise, controlled by a single trigger circuit input and by a saturable reactor which controls the firing of a thyratron switch.

Abstract: An improved high security locking apparatus is provided by combining an electromagnetic locking apparatus of the type which includes a lock portion and a removable key portion, the key portion providing a determined unlocking combination signal, the lock portion providing an immediate unlocking function in response to the presentation of the determined unlocking combination signal from the key portion while placed within a determined surface location of the lock portion, with an interlocked time delay circuit which provides silent, time delayed activation of the unlocking function in response to the simultaneous presence of the determined unlocking combination signal with the placement of the key portion within the determined surface location, and which inhibits the unlocking function for all other conditions.