Lead Frame Patents (Class 361/813)
  • Patent number: 10438871
    Abstract: A conductor track which is designed in particular for use with ultrasonic welding. The invention also relates to an associated method and to an associated use.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 8, 2019
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Svenja Raukopf, Lothar Biebricher, Dietmar Huber, Jakob Schillinger
  • Patent number: 10395843
    Abstract: An electrical connection contact (5) for a ceramic component (2) is specified. The connection contact (5) comprises a first material (M1) and a second material (M2) arranged thereon, wherein the first material (M1) has a high electrical conductivity and the second material (M2) has a low coefficient of thermal expansion.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: August 27, 2019
    Assignee: Epcos AG
    Inventors: Markus Koini, Christoph Auer, Jürgen Konrad, Franz Rinner, Markus Puff, Monika Stadlober, Thomas Wippel
  • Patent number: 9958292
    Abstract: A sensor package includes a lead frame, a sensor component, and first and second capacitors. The lead frame has a sensor mounting area and first and second leads. The sensor mounting area, the first lead, and the second lead are characterized by a first side and a second side. The sensor component is attached to the first side of the sensor mounting area of the lead frame. The first capacitor is interconnected between the first and second leads, with the first capacitor being attached to the first side of each of the leads. The second capacitor is interconnected between the first and second leads, with the second capacitor being attached to the second side of each of the leads. The first and second capacitors are arranged in stacked relation with one another on opposing sides of the leads, and the sensor component and capacitors are located in a single housing.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: May 1, 2018
    Assignee: NXP B.V.
    Inventor: Bernd Offermann
  • Patent number: 9553073
    Abstract: A chip stack structure using conductive film bridge adhesive technology comprises a substrate, a first chip, at least one bridge element, a conductive film, and a second chip. The first chip is electrically connected to a first electrode of the substrate. The at least one bridge element has a first bridge surface and a second bridge surface at two ends, and the first bridge surface and the second bridge surface are electrically connected to the first chip and a second electrode of the substrate, respectively. The conductive film is electrically connected to the first bridge surface of the at least one bridge element. The second chip is stacked and electrically connected to the conductive film. Thus, the structure of the present invention not only facilitates the ease of stacking the chips but also increases the effectiveness of the chips heat dissipation and ability of withstanding electrical current.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: January 24, 2017
    Inventors: Chien-Ko Liao, Tzu-Chih Lin
  • Patent number: 9312229
    Abstract: A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes a diffusion barrier layer that includes sidewall portions, and a metallic material encircled by the sidewall portions of the diffusion barrier layer. The metallic material has a second planar surface level with the first planar surface. An air gap extends from the second planar surface of the metallic material into the metallic material. An edge of the air gap is aligned to an edge of the metallic material.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Dun-Nian Yaung
  • Patent number: 9219028
    Abstract: An embodiment of a packaged device includes first and second package leads, a first integrated circuit (IC) die, and a sub-assembly that includes a second IC die coupled to a substrate. The first IC die has a first coil, and the second IC die has a second coil. The first and second IC die are arranged within the device so that the first and second coils are aligned with each other across a gap between the first and second IC die, and the first and second IC die are galvanically isolated from each other. The first IC die is electrically coupled to the first package lead (e.g., with a wirebond), and a substrate bond pad is electrically coupled to the second package lead (e.g., with a wirebond). The sub-assembly also may include encapsulation at least over a wirebond that electrically couples the second IC die to the substrate.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 22, 2015
    Inventors: Leo M. Higgins, III, Fred T. Brauchler
  • Patent number: 9129979
    Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 8, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuya Koike, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
  • Patent number: 9105611
    Abstract: Disclosed herein is a power module package including: a substrate having a ceramic layer formed in one surface thereof; a circuit pattern formed on the ceramic layer; a first lead frame having one side contacting the circuit pattern and the other side protruding toward the outside; and a first semiconductor chip mounted on one side of the first lead frame.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: August 11, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Soo Kim, Yong Hoon Kwak, Sun Woo Yun, Young Ki Lee, Kyu Hwan Oh, Jin Suk Son
  • Patent number: 9097753
    Abstract: A Hall sensor is provided having a first Hall element with a first terminal contact and with a second terminal contact and with a third terminal contact, a second Hall element with a fourth terminal contact and with a fifth terminal contact and with a sixth terminal contact, a third Hall element with a seventh terminal contact and with an eighth terminal contact and with a ninth terminal contact, and a fourth Hall element with a tenth terminal contact and with an eleventh terminal contact and with a twelfth terminal contact. The first Hall element and the second Hall element and the third Hall element and the fourth Hall element are connectable in series.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: August 4, 2015
    Assignees: Micronas GmbH, Albert-Ludwigs-Universitaet Freiburg
    Inventors: Roiy Raz, Patrick Ruther, Timo Kaufmann, Oliver Paul
  • Patent number: 9099625
    Abstract: A light emitting diode package includes a metallic frame, and an LED chip disposed on the metallic frame. The metallic frame includes first and second metal plates arranged side by side with a space therebetween, and two support arms extending integrally and respectively from two opposite ends of the second metal plate to a level higher than the second top surface and that further extend toward the first metal plate at a level higher than the first top surface crossing the space. The support arms are not in contact with the first metal plate. An encapsulant encapsulates the metallic frame and the LED chip. At least a region of the encapsulant that covers the LED chip is transparent.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: August 4, 2015
    Assignees: Lite-On Electronics (Guangzhou) Limited, Lite- On Technology Corp.
    Inventors: Yi-Chien Chang, Chen-Hsiu Lin, Meng-Sung Chou
  • Publication number: 20150101570
    Abstract: Electrical component assemblies and other electrical connectors are provided having protective coatings that allow for use in high temperature and highly corrosive environments. Methods for applying protective coatings are also provided. In one embodiment, a connector is provided and includes a protective coating that encapsulates at least a portion thereof. The connector can be, for example, an electrical lead frame, or a connector having a distal side and a proximal side that is disposed in an automotive fuel system such that the distal side is sealed from the proximal side. Methods for coating connectors are also provided.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Inventor: John David Seaton
  • Patent number: 9001527
    Abstract: The present invention discloses an electronic package structure. The body has a top surface with a cavity thereon, the first conductive element is disposed in the cavity, and the second conductive element is disposed in the body. The first external electrode electrically connected to the first conductive element and the second external electrode electrically connected to the second conductive element are both disposed on the top surface of the body or a first surface formed by the top surface of the encapsulation compound and the exposed portions of the top surface of the body which are not covered by the encapsulation compound.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: April 7, 2015
    Assignee: Cyntec Co., Ltd.
    Inventors: Da-Jung Chen, Chun-Tiao Liu, Bau-Ru Lu
  • Patent number: 9001524
    Abstract: An integrated circuit device includes a support for supporting electrical circuitry, an integrated circuit having electrical circuitry disposed on the support, and a magnetic portion attached to the support around the integrated circuit. The integrated circuit and the magnetic portion are interconnected for converting a power input signal having a first characteristic to a power output signal having a second characteristic different from the first characteristic.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: April 7, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Sunil M. Akre
  • Patent number: 8994156
    Abstract: Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: March 31, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Shing Chiang, Ping-Cheng Hu, Yu-Fang Tsai
  • Patent number: 8987875
    Abstract: An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates. The substrates, lead frames, and electronic devices are sintered together using silver-based sintering paste between each layer. The material and thicknesses of the substrates and lead frames are selected so stress experienced by the electronic devices caused by changes in temperature of the assembly are balanced from the center of the assembly, thereby eliminating the need for balancing stresses at a substrate level by applying substantially matching metal layers to both sides of the substrates.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 24, 2015
    Assignee: Delphi Technologies, Inc.
    Inventors: Carl W. Berlin, Gary L. Eesley
  • Patent number: 8942009
    Abstract: A power switch assembly includes a flip-chip type integrated circuit chip and a lead-frame with a plurality of spaced apart parallel lead sections. The flip-chip type integrated circuit chip includes a distributed transistor, and first and second pluralities of flip-chip interconnects connected to source and drain regions, respectively. The first and second lead sections at least partially overlap along the first axis. Each of the plurality of lead sections includes a contact portion and an extended portion extending laterally from the contact portion. The extended portions of the first and second lead section extend from the contact portion in opposite directions. The first side of the first and second lead section contacts at least two of the first and plurality of flip-chip interconnects, respectively. The second side of the first and second lead are configured to contact a first and second contact area on a printed circuit board, respectively.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Efren M. Lacap, Ilija Jergovic
  • Patent number: 8928049
    Abstract: A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8883567
    Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Todd Wyant, Patricia Sabran Conde, Vikas Gupta, Rajiv Dunne, Emerson Mamaril Enipin
  • Publication number: 20140328042
    Abstract: A power supply module and a method for manufacturing the same are disclosed. The power supply module includes a coil including a coil body and a connecting terminal; electronic components at least including an integrated circuit chip; a connector configured to be electrically connected with the coil and the electronic component; and a magnetic conductor configured to enclose in and around the coil body and the electronic component, wherein the connector is integrally formed with the integrated circuit chip when manufacturing the latter. The present disclosure can make the structure of the power supply module be more compact to further meet the needs of miniaturization design, reduce material consumption, simplify procedure, and therefore reduce the production costs.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 6, 2014
    Inventors: Zhuo WU, Douglas James Malcolm, Yanfei Liu
  • Publication number: 20140268624
    Abstract: A carrier for mounting a piezoelectric device, e.g., a surface acoustic wave (SAW) device, on a circuit board and a method of mounting a piezoelectric device on a circuit board using such a carrier are disclosed. The carrier includes a carrier bottom, a plurality of metal contacts, and a carrier lid attached to the carrier bottom. The carrier bottom has an opening extending partially through the carrier bottom from a top surface thereof and the opening is configured such that when a piezoelectric device to be mounted in the carrier is inserted into the carrier bottom, the piezoelectric device is at least partially recessed within the carrier bottom. The metal contacts include a cantilevered end configured for electrical connection to a piezoelectric device. The carrier lid is configured to retain a piezoelectric device within the carrier bottom and to apply substantially even pressure across a top surface of a piezoelectric device.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Peter Owen, Conrad Zeglin, Barclay Roman, Mark Meister
  • Patent number: 8837168
    Abstract: An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 16, 2014
    Assignee: Cyntec Co., Ltd.
    Inventors: Da-Jung Chen, Chau-Chun Wen, Chun-Tiao Liu
  • Publication number: 20140247576
    Abstract: A device for carrying high-voltage equipment in an electrically-insulated manner includes a carrier platform which is mounted and electrically insulated by way of support insulators. The high-voltage equipment is supported on the carrier platform. The carrier platform has primary carriers with which the platform rests on the support insulators. In order to achieve a device that prevents deflections of the carrier platform in a cost-effective manner, the high-voltage equipment is at least partially arranged in a carrier structure that is equipped with support feet, with each foot arranged vertically above a primary carrier.
    Type: Application
    Filed: October 31, 2011
    Publication date: September 4, 2014
    Inventors: German Kuhn, Achim Von Seck
  • Patent number: 8824165
    Abstract: An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 2, 2014
    Assignee: Cyntec Co. Ltd
    Inventors: Da-Jung Chen, Chau-Chun Wen, Chun-Tiao Liu
  • Patent number: 8816411
    Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 26, 2014
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiak Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Patent number: 8815646
    Abstract: A semiconductor device is formed by molding using a resin with a semiconductor element and one or two heat dissipating plates contained therein, said one or two heat dissipating plates being disposed to face one surface or both the surfaces of the semiconductor element. An intermediate layer is formed by spraying a metal powder to the semiconductor element and to one of or both of the heat dissipating plates using a cold spray method, and the semiconductor element and the heat dissipating plate are bonded together using a solder with the intermediate layer therebetween.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hirotaka Ohno
  • Patent number: 8787003
    Abstract: According to one embodiment of a capacitor module, the capacitor module includes a substrate having a metallization on a first side of the substrate, a plurality of connectors electrically coupled to the metallization and a plurality of capacitors disposed on the metallization. The plurality of capacitors includes a first set of capacitors electrically connected in parallel between a first set of the connectors and a second set of the connectors. The capacitor module further includes a housing enclosing the plurality of capacitors within the capacitor module.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies AG
    Inventors: Daniel Domes, Reinhold Bayerer
  • Publication number: 20140192506
    Abstract: A lead frame includes adjacent die pads which lie adjacent to each other; grounding leads extended from the adjacent die pads; a connecting bar by which the grounding leads extended from the adjacent die pads are interconnected. The grounding leads and the connecting bar are formed to be thinner at one surface than a maximum thickness of leads of the lead frame, the grounding leads extended from the adjacent die pads are aligned on a common axis while providing the connecting bar between the grounding leads, and a support projection is provided at the one surface on the connecting bar in the common axis.
    Type: Application
    Filed: January 2, 2014
    Publication date: July 10, 2014
    Applicant: MITSUI HIGH-TEC , INC.
    Inventor: Takahiro ISHIBASHI
  • Publication number: 20140176176
    Abstract: A high bandwidth solder-less lead may be connected to an electrical device having land patterns so that signals on the device may be more easily measured through the lead. The lead includes an attachment mechanism to mount the lead on the device, a microspring housing and at least one microspring. The microspring connects one of the particular land patterns on the device to the lead where it may be easier to couple to a measurement device than to the electrical device itself The lead may be coupled to a flexible electrical conduit to make attaching to the testing device even easier. In other versions, a uniform connector may be temporarily attached to the solder-less lead to test the device. Then the connector may be disconnected from the first lead and connected to another lead to test another area of the device.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: TEKTRONIX, INC.
    Inventor: JAMES H. MCGRATH, JR.
  • Patent number: 8754511
    Abstract: In order to prevent an increase in temperature of a discharge resistance discharging an electric charge accumulated in a smoothing capacitor, the present description discloses a power module. The power module has a first lead frame, a second lead frame, first and second semiconductor switches connected in series between the first lead frame and the second lead frame, a resistor connected between the first lead frame and the second lead frame, and a resin package that encapsulates the first lead frame, the second lead frame, the first semiconductor switch, the second semiconductor switch, and the resistor. In this power module, a radiator portion for radiating heat from the first lead frame and/or the second lead frame is formed in at least a part of the package.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: June 17, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Takashi Atsumi
  • Patent number: 8737089
    Abstract: A Ferritic stainless steel, non Ferritic stainless steel or carbon steel based lead frame and method for producing same is provided. The lead frame is preferably used for TantalumNiobium capacitors but could possibly be applicable to other integrated circuits with the same operating parameters. Any reference to Tantalum capacitors in this application applies equally to Niobium capacitors unless otherwise noted. The lead frame is prepared by choosing one of Ferritic stainless steel, non Ferritic stainless steel or carbon steel as a base metal and rolling it to a final required thickness. The base metal is then preferably plated with a nickel strike or other conventional barrier layer and then with final outer plating layers(s). The exact thickness and choice of layering varies and can be tailored to meet the requirements of each lead attach process.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: May 27, 2014
    Assignee: Micro Stamping Corporation
    Inventors: Frank J. Semcer, Sr., Steven G. Santoro, James McClintock, Frank J. Jankoski, Jr.
  • Publication number: 20140134966
    Abstract: An integrated circuit package includes an encapsulation and lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame includes a first conductor formed in the lead frame having a first conductive loop and a third conductive loop disposed substantially within the encapsulation. A second conductor is formed in the lead frame galvanically isolated from the first conductor. The second conductor includes a second conductive loop disposed substantially within the encapsulation proximate to the first conductive loop to provide a communication link between the first and second conductors. The third conductive loop is wound in an opposite direction relative to the first conductive loop in the encapsulation.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 15, 2014
    Inventors: David Kung, David Michael Hugh Matthews, Balu Balakrishnan
  • Patent number: 8716069
    Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 6, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Yongping Ding
  • Patent number: 8717777
    Abstract: The present technology relates to fused capacitor structures provided with a leadframe design configured to accepting a plurality of selectively placed fuses. The leadframe and fuse configuration enables construction of fused capacitors exhibiting low Equivalent Series Resistance (ESR) and allows construction of a variety of fuse configuration using a single leadframe design.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: May 6, 2014
    Assignee: AVX Corporation
    Inventors: Douglas Mark Edson, James Allen Fife, Glenn Maurice Vaillancourt, David Allen Wadler
  • Publication number: 20140111960
    Abstract: A leadframe module for an electrical connector includes a leadframe having contacts initially held together as part of the leadframe. The contacts have mating ends configured to be mated to corresponding mating contacts. The contacts having mounting ends configured to be terminated to corresponding conductors. Dielectric shells coat corresponding contacts. Outer shields are applied to corresponding dielectric shells. Each of the contacts, dielectric shells and outer shields define corresponding shielded transmission lines of the leadframe module. Optionally, a ground plate may be coupled to each of the transmission lines and electrically connected to the outer shields of the transmission lines to electrically common each of the outer shields.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: Tyco Electronics Corporation
    Inventor: Michael Fredrick Laub
  • Patent number: 8692360
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: April 8, 2014
    Assignee: International Rectifier Corporation
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 8681479
    Abstract: A method, apparatus, and system are described for a pre-wired and pre-engineered integrated platform for power supply and distribution that is pre-assembled, scalable, and modular. The skeletal framework of the integrated platform acts as an equipment support structure as well as a cable routing support system. A set of cables having wiring is routed along the skeletal framework of the integrated platform and goes to two or more cabinet enclosures mounted onto the skeletal framework. The skeletal framework acts as a National Electric Code approved raceway system to support and route the set of cables to the electrical equipment in the mounted cabinet enclosures. The integrated platform supports the weight of the one or more cabinet enclosures mounted onto the skeletal framework.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: March 25, 2014
    Assignee: Rosendin Electric, Inc.
    Inventors: Matthew John Englert, Jeffrey David Rose, John Manual Loera
  • Publication number: 20140071650
    Abstract: A wireless multichip module has a leadframe structure 10 with potions for receiving flip-chip mounted dies, including an integrated circuit 20 and high and low side mosfets 30, 40 to form a half-bridge circuit encapsulated in molding compound 70. The module is assembled without any bond wires. The module may also carry passive components including an external input capacitor 150 or an internal input capacitor 350.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 13, 2014
    Inventors: Allan Tungul Flores, Romel N. Manatad
  • Patent number: 8669652
    Abstract: To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 11, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventors: Shohei Hata, Yuichi Oda, Kazuma Kuroki, Hiromitsu Kuroda
  • Publication number: 20140036471
    Abstract: Systems and methods are disclosed herein for a low cost, compact size, and thin half-etched leadframe quad-flat no-leads (QFN) package that integrates RF passive elements in the QFN leadframe for linearized PA design and RF FEMs. The integrated RF passive elements in the QFN leadframe may include RF inductors (e.g., meanders lines or spirals) for amplifier bias or RF matching, extension bar of the ground paddle for inter-stage matching or jumper pads for connection. The integrated RF passive elements may also include transmission lines for output power matching, coupled line structures such as RF couplers, RF divider or combiner realized using transmission lines with proper impedance and length, jumper pads for adjusting the bond wire length, etc. The RF parameters of the integrated passive elements are adjustable using different length and number of wire bond for fine tuning the performance of the PAM or the RF FEM.
    Type: Application
    Filed: August 6, 2013
    Publication date: February 6, 2014
    Inventors: Cindy Yuen, Duc Chu
  • Patent number: 8643054
    Abstract: A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and a second branch extending from the first branch; an electrical contact structure between the second branch and the semiconductor light-emitting stack and having a first width; and a current blocking structure located right beneath the electrical contact structure and having a second width larger than the first width.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 4, 2014
    Assignee: Epistar Corporation
    Inventors: Chien-Fu Huang, Min-Hsun Hsieh, Chih-Chiang Lu, Chia-Liang Hsu, Shih-I Chen
  • Publication number: 20140029201
    Abstract: There is provided a power package module, including: a lead frame; at least one first electronic component mounted on the lead frame; and an insulating member disposed on a first surface of the first electronic component and having a via electrode connected to the first electronic component.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 30, 2014
    Inventors: Si Joong YANG, Do Jae Yoo, Joon Seok Chae
  • Patent number: 8630097
    Abstract: Disclosed herein are a power module using sintering die attach and a manufacturing method of the same. The power module includes: a substrate having an insulating layer formed on a surface of a metal plate; a circuit layer formed on the substrate and including a wiring pattern and an electrode pattern; a device mounted on the wiring pattern; a sintering die attach layer applying a metal paste between the wiring pattern and the device and sintering the metal paste to bond the wiring pattern to the device; and a lead frame electrically connecting the device to the electrode pattern, whereby making it possible to simplify and facilitate the process, increase electrical efficiency and improve radiation characteristics, and manufacture firm and reliable power module.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 14, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Yong Hui Joo, Seog Moon Choi
  • Publication number: 20130343027
    Abstract: A method of forming a stacked electronic component, and an electronic component formed by the method wherein the method includes: providing a multiplicity of electronic components wherein each electronic component comprises a first external termination and a second external termination; providing a first lead frame plate and a second lead frame plate wherein the first lead frame plate and the second lead frame plate comprises barbs and leads; providing a molded case comprising a cavity and a bottom; and forming a sandwich of electronic components in an array between the first lead frame plate and the second lead frame plate with the barbs protruding towards the electronic components and the leads extending through the bottom.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Inventors: Maurice Perea, Allen Hill, Reggie Phillips
  • Publication number: 20130322046
    Abstract: A method of manufacturing an electronic device, the method includes: preparing a first lead frame having a first lead, the first lead having a first portion located in a first region; electrically connecting the first lead and a first electronic part; bending the first lead such that the first portion is located outside the first region; arranging a second lead frame to overlap the first lead frame such that a second portion of a second lead of the second lead frame is located in the first region; and electrically connecting the second lead and the second electronic part.
    Type: Application
    Filed: August 8, 2013
    Publication date: December 5, 2013
    Inventor: Tetsuya OTSUKI
  • Patent number: 8598693
    Abstract: A rear surface opposite to one plane of a die pad is formed to be exposed from one plane of a sealing resin. In addition, a concave portion disposed to be parallel with at least a first side of an outermost edge of a central structure and a second side adjacent to the first side, respectively, is formed in the one plane of the sealing resin. Here, a depth of the concave portion is equal to or greater than a height of the outermost edge of the central structure.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: December 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kenji Nishikawa
  • Publication number: 20130308289
    Abstract: Provided is a tape for electronic devices with lead crack and a method of manufacturing the tape. According to the present invention, by forming a bending portion on a narrow circuit pattern to be connected from an inner lead to an outer lead and further forming the bending portion within a resin application portion, crack occurred in a narrow wiring width can be avoided. The tape may include a first lead and a second lead formed on a dielectric substrate and a bending portion formed on one of the first lead and the second lead wherein the bending portion is formed within a resin application portion.
    Type: Application
    Filed: October 12, 2011
    Publication date: November 21, 2013
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Dae Sung Yoo, Han Mo Koo, Ki Tae Park, Jun Young Lim, Tae Ki Hong
  • Patent number: 8582317
    Abstract: A semiconductor component and a method of manufacturing the semiconductor component that reduces parasitic elements. A semiconductor chip is coupled to a semiconductor chip receiving area of a support structure. The semiconductor chip has at least two power semiconductor devices. A drain contact of a first power semiconductor device is coupled to a source contact of a second power semiconductor device and the drain and source contacts of the first and second power semiconductor devices are joined to the semiconductor chip receiving area. Another semiconductor chip may be bonded to a second semiconductor chip receiving area of the support structure. An energy storage element may be coupled between the source contact of the first power semiconductor device and the drain contact of the second semiconductor device. A protective structure may be formed over the semiconductor chips and the energy storage element.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: November 12, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yenting Wen, Kisun Lee, Michael Stapleton, Gary H. Loechelt
  • Publication number: 20130292811
    Abstract: A metal leadframe strip (500) for semiconductor devices is described. The leadframe strip has a plurality of sites (510) for assembling semiconductor chips. The sites alternate with zones (520) for connecting the leadframe to molding compound runners. The sites (510) have mechanically rough and optically matte surfaces (511, 512). The zones (520) have at least portions with mechanically flattened and optically shiny metal surfaces (521, 522). The flattened surface portions transition into the rough surface portions by a step.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 7, 2013
    Inventor: Donald C. Abbott
  • Patent number: 8547709
    Abstract: A composite substrate made of a circuit board mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the circuit board. Metal lines are used for electrical coupling between the circuitry of the IC chip and the circuit board. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the circuit board and good heat distribution from the lead frame.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: October 1, 2013
    Assignee: Cyntec Co. Ltd.
    Inventors: Han-Hsiang Lee, Kun-Hong Shih, Jeng-Jen Li
  • Publication number: 20130242524
    Abstract: An LED package with trenches traversing a die pad to provide a mechanical interlock mechanism to strengthen bonding between the die pad and an insulator such that de-lamination is less likely to occur between the die pad and the insulator. A chip carrying region is defined by a barrier portion formed by the insulator in the trenches and in gaps between electrodes and the die pad, such that a light converting layer is confined within the barrier portion.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 19, 2013
    Inventor: Hsun-Wei Chan