Abstract: The invention provides a low phase surge protection device including a voltage converter, a low phase delay detector and an output control switch. The voltage converter receives an alternate current (AC) input voltage, and converts the AC input voltage into a direct current (DC) input voltage. The low phase delay detector receives the DC input voltage to be a power source, enables a phase detection scheme by detecting whether the AC input voltage is in a stable state, and generates an enable signal by detecting a phase of the AC input voltage after the phase detection scheme is enabled. The output control switch receives the AC input voltage, and determines whether to transmit the AC input voltage to be an output voltage according to the enable signal.

Abstract: A direct current-to-direct current (DC-DC) power supply includes a voltage converter module that converts an input voltage having a first voltage level into an output voltage having a second voltage level that is less than the first voltage level. An over-voltage detection module receives the second voltage and generates an over-voltage signal indicating an over-voltage condition of the DC-DC power supply. A shutdown module receives the over-voltage signal and generates a shutdown signal in response to the over-voltage condition. An over-voltage protection module interposed between the shutdown module and the input of the voltage converter module. The over-voltage protection module is configured to selectively inhibit delivery of the input voltage to the voltage converter module in response to the shutdown signal.

Abstract: A peripheral device configured to be plugged into an audio jack of an electronic device includes an audio plug having an input terminal; a load electrically connected to the input terminal of the audio plug and configured to draw a first amount of current; a variable resistor electrically connected to the input terminal; a sensor configured to measure a voltage at the input terminal or an amount of current flowing into the load; and a controller that receives a signal from the sensor and is configured to control a resistance of the variable resistor such that a sum of the first amount of current and a second amount of current flowing through the variable resistor is substantially equal to a predetermined current value.

Abstract: An inverter drive device includes a drive circuit that outputs a gate voltage signal of a power semiconductor element; and a Zener clamping protection circuit that acquires an emitter electrode side voltage of the power semiconductor element, and, if that voltage is greater than a predetermined voltage value, performs clamping of the gate voltage of the drive circuit after a predetermined time interval has elapsed from the acquisition of the emitter electrode side voltage. The Zener clamping protection circuit includes a latch circuit that, after the emitter electrode side voltage has been acquired, continues the clamping of the gate voltage by the Zener clamping protection circuit during an interval.

Abstract: Provided is a transistor protection circuit capable of appropriately protecting a transistor even when a switching frequency is high. A transistor protection circuit according to an embodiment of the present invention is a transistor protection circuit for protecting a voltage-driven transistor that is switch-controlled by the application of a high-potential-side voltage or low-potential-side voltage of a power supply to a gate terminal of the transistor by a drive circuit. The transistor protection circuit has a power supply controller that gradually lowers the high-potential-side voltage of the power supply upon receiving a protection command for executing protection of the transistor.

Abstract: A battery pack including a battery and a battery protection circuit is disclosed. In one aspect, the battery protection circuit comprises a protective device configured to inhibit a flow of current between an electrode of the circuit and the battery when activated. The battery protection circuit further comprises a primary protection circuit and a secondary protection circuit. The primary protection circuit is configured to generate a control signal for control the protective device when detecting an abnormal voltage in a unit cell of the battery. The secondary protection circuit is configured to activate the protective device, either when receiving the control signal from the primary protection circuit or when detecting an abnormal voltage in a unit cell of the battery.

Abstract: A battery protection circuit includes a control module, a first switch, and a loading module. The control module includes a second switch. A base terminal of the second switch is connected to a positive terminal of a battery, and an emitter terminal of the second switch is grounded. The first switch includes a gate terminal, a source terminal, and a drain terminal. The gate terminal is connected to the control module and further connected to a collector terminal of the second switch, and the source terminal is grounded. The drain terminal is connected to a first capacitor, and the first capacitor is grounded. The loading module is connected to the battery. When the loading module is abnormal, the gate terminal receives a control signal to switch off the first switch.

Abstract: A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.

Abstract: Methods of the invention include an electrostatic discharge (ESD) protection method capable of detecting a slew rate of an input signal and capable of determining whether the slew rate of the input signal is greater than a threshold value. For an ESD event having a slew rate in excess of the threshold value said method generates a trigger signal which generates an activation signal that activates the ESD dissipation circuitry and that controls the length of time the dissipation circuit remains active. The method further comprises shunting the ESD energy away from a protected internal circuit. The method maintaining the shunting of the energy for a period of time sufficient to discharge of the ESD energy without damaging the protected circuitry.

Abstract: Provided is a transistor protection circuit capable of appropriately protecting a transistor even when a switching frequency is high. A transistor protection circuit according to an embodiment of the present invention is a transistor protection circuit for protecting a voltage-driven transistor that is switch-controlled by the application of a high-potential-side voltage or low-potential-side voltage of a power supply to a gate terminal of the transistor by a drive circuit. The transistor protection circuit has a power supply controller that gradually lowers the high-potential-side voltage of the power supply upon receiving a protection command for executing protection of the transistor.

Abstract: A driving circuit controls a driving signal according to a control signal at a first or second logic level for driving a load. A driving protection circuit includes a driving signal detection circuit for generating a load error signal in response to that a load is abnormal; a delay judgment circuit coupled to the driving signal detection circuit for generating a first signal in response to that the load has been abnormal for a predetermined time period; and a logic control circuit coupled to the delay judgment circuit and the driving circuit for determining whether to modulate the driving signal according to the first signal. When the control signal has been at the first logic level and the load has been abnormal for the predetermined time period, the logic control signal modulates the driving signal to be a level corresponding to the control signal at the second logic level.

Abstract: A system includes an electrical component, a MOV, a voltage sensor, and a circuit. The MOV is connected in parallel to the electrical component. The voltage sensor detects a voltage over the MOV and the electrical component. The circuit removes power in response to the voltage sensor detecting the voltage over the MOV and the electrical component being greater than a threshold voltage for a length of time greater than a threshold length of time. Removing power prevents the MOV from releasing one or more of smoke, smell, and sound. The MOV is thus not damaged as a result of a power surge. The system may be a power supply, or another type of electrical system. The electrical component may be a capacitor, or another type of electrical component.

Abstract: A clamp unit is adapted for controlling a clamp switch of a power supply such that the power supply outputs an output voltage in an ON mode when the clamp switch is in an ON-state and that the power supply does not output the output voltage in an OFF mode when the clamp switch is in an OFF-state. The clamp unit includes: a coupling circuit for outputting a coupling voltage in response to first and second reference voltages, and a control signal outputted by a control signal generating circuit in response to an input voltage; and a detecting circuit for outputting a clamp signal to the clamp switch in response to a first signal indicating whether the power is in the ON mode or the OFF mode, and a second signal indicating whether the power supply is to output the output voltage.

Abstract: An overcurrent protection circuit connected between a voltage input and a voltage output of an electronic device to protect against excessive current is disclosed. The overcurrent protection circuit includes first to fifth resistors, a relay comprising a coil and a normally closed switch, a pnp transistor, and a break-over element. When a current between the voltage input and the voltage output is greater or equal to a rated current of the electronic device, the npn transistor is turned on, while the coil is powered on to control the switch to be opened, therefore the voltage output cannot output voltage, which can protect against excessive current damaging the electronic device.

Abstract: A solid state power controller (SSPC) often contains electronic circuitry which could be damaged or upset by the excessive transient voltages induced by the lightning and SSPC could result in undesirable (or nuisance) trips due to lightning strikes. The present invention is intended to address the “nuisance trip” issue, by relying on the lightning indicative signals to distinguish between the transient current surge due to the lightning strike and that due to the circuit fault in the power distribution channel. The present invention utilizes either the break-down current in a transient voltage suppression (TVS) device, or a voltage signal at the output of the SSPC as the indication of lightning strike, to avoid nuisance trips.

Abstract: An embodiment of the invention relates to a switch-mode power converter including an inductor and an external rectifying diode. A series arrangement of a resistor and a switch are coupled in parallel with the external rectifying diode. The resistor and the switch enable continuous conduction mode, even at substantially no output current. A comparator senses a current level in the resistor. When the current level crosses a threshold level, the power converter is shut down. The current level is sensed with a second resistor coupled to a current source to produce a current sensing arrangement dependent on a ratio of resistances. Advantageously, the current level is sensed with clamp circuits coupled to the comparator, each clamp circuit including a series circuit arrangement of a field-effect transistor with a gate coupled to a voltage source.

Abstract: An over current protection circuit controls connection and disconnection of an electronic device. When the electronic device is turned off because of over current, the over current protection circuit automatically resets the electronic device after a delay time.

Abstract: A system includes an electrical component, a MOV, a voltage sensor, and a circuit. The MOV is connected in parallel to the electrical component. The voltage sensor detects a voltage over the MOV and the electrical component. The circuit removes power in response to the voltage sensor detecting the voltage over the MOV and the electrical component being greater than a threshold voltage for a length of time greater than a threshold length of time. Removing power prevents the MOV from releasing one or more of smoke, smell, and sound. The MOV is thus not damaged as a result of a power surge. The system may be a power supply, or another type of electrical system. The electrical component may be a capacitor, or another type of electrical component.

Abstract: A motor-drive circuit comprising: a current-passage-control circuit to perform ON/OFF control of a drive transistor connected to a motor coil to pass current through the motor coil; an overcurrent-state-detection circuit to detect whether current passing through the drive transistor is in an overcurrent state where the current exceeds a predetermined threshold value; a charging and discharging circuit to start charging a capacitor in response to detecting the overcurrent state by the overcurrent-state-detection circuit and subsequently discharge the capacitor in response to not detecting the overcurrent state; and an overcurrent-protection-control circuit to stop the ON/OFF control to turn off the drive transistor, for an elapsed charging period for a charging voltage of the capacitor at a predetermined voltage to exceed a threshold voltage, and determine whether to perform such an overcurrent-protection-control as to turn off the drive transistor by detection of the overcurrent state, after the charging peri

Abstract: An overvoltage protection circuit includes a PMOS transistor Q1 that is disposed between an input circuit 21, from which an input voltage VIN is supplied, and a system 22 and functions as a switch. A comparator 110 compares the input voltage VIN with a predetermined reference voltage to determine the occurrence of an overvoltage. Further, the comparator 110 outputs a High level as an operation signal when no overvoltage is detected. A soft switching control circuit 130 starts up by using the High level output from the comparator 110 as an enable signal, and gradually turns on the PMOS transistor Q1. A sudden change of the load exerted on the circuit on the input side is suppressed by the soft start function.

Abstract: An electrostatic discharge protection circuit has a substrate; a first P-well installed on the substrate and having a first P+-doped region and a first N+-doped region, both of which are connected to ground; a second P-well installed on the substrate and having a second P+-doped region and a second N+-doped region, both of which are connected to a power supply voltage; and a third P-well installed on the substrate and having a third N+-doped region, a third P+-doped region, and a fourth N+-doped region, all of which are for input/output signals.

Abstract: Method, and apparatus for operating a power feed in a computing system. One exemplary embodiment includes monitoring the power feed to ensure the power level of the entire system never remains above a first power level and only remains above a second power level for a period of time determined by a timer level.

Abstract: The integrated protection circuit according to the invention for ESD protecting an circuit device having at least one pad, e.g. a I/O pad, comprises a first transistor (MPI) whose control outputs are connected between the pad (2, 3) and the control input of a clamp transistor (MN4). The control outputs of the clamp transistor (MN4) are connected between the pad (2, 3) and a reference terminal (4). The protection circuit further comprises a second transistor (MN3) whose control outputs are connected between the control output of the first transistor (.MP 1) and the reference terminal (4). Finally the protection circuit also comprises time-delay elements (R, MN 1) connected between a supply voltage terminal (1) and the control inputs of the first transistor (MP I) and the second transistor (MN3).

Abstract: Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indicator continues to detect a signal level of the I/O pad and keeps the indication signal low. Once over-voltage is detected, the over-voltage indicator pauses detecting, asserts a high level in the indication signal, and periodically resumes detecting until end of over-voltage is detected. With informing provided by the indication signal, a core cell of the chip can perform proper operation to reduce potential damage caused by over-voltage.

Abstract: A power supply device having an overvoltage cutoff function, an image display device, and a method of cutting off overvoltage are provided. The power supply device includes a switch unit which cuts off a power supply to the power supply device; and an overvoltage sensing unit which compares a voltage of the power supply device with a specified reference voltage, and if the voltage of the power supply device is higher than the specified reference voltage, generates an overvoltage cutoff signal to control the switch unit. The overvoltage cutoff signal is used to report a power supply cutoff state. Accordingly, the damage of the power supply device due to an unstable AC input voltage can be prevented and the user can be alerted to the overvoltage through the display of the power supply cutoff state.

Abstract: Device for protecting an integrated circuit, comprising a device for detecting a latch-up condition, and a supply voltage control device for controlling a supply voltage of the integrated circuit, to modify a parameter of the supply voltage of the integrated circuit in order to prevent the latch-up from becoming permanently established.

Abstract: One embodiment of the invention includes a power regulation system. The system comprises a power regulator configured to periodically generate a switch signal that regulates a current flow through an inductor to set a magnitude of an output voltage. The system further comprises an overvoltage protection circuit configured to monitor a peak voltage magnitude of the switch signal and to generate an overvoltage indication signal in response to the peak voltage magnitude of the switch signal exceeding a predetermined limit.

Abstract: A method and associated system are disclosed for verifying charging failures for smart batteries by measuring input charging voltage and associated systems. In one embodiment, a determination is made whether or not a charging current is indicative of a battery failure by utilizing an analog-to-digital (A/D) port to measure the input charging voltage. As long as the measured input charging voltage is below the cell pack voltage or some set voltage value, whichever is higher, the BMU considers a charging current detection to be a false failure indication. If the measured charging voltage is above the cell pack voltage and the set voltage value, the BMU considers the charging current detection to be a positive failure indication. The BMU can then disable the battery or implement other verification steps before disabling the battery, as desired.

Abstract: An overcurrent detection circuit that detects an overcurrent state of a transistor that outputs a current to a load is provided with a start-up monitoring portion that distinguishes between a start-up state and a steady state, an overcurrent monitoring portion that monitors an overcurrent state of the transistor, and an output voltage monitoring portion that detects whether the output voltage to the load is normal or abnormal. The overcurrent monitoring portion changes an overcurrent detection level while referring to information from the start-up monitoring portion and the overcurrent monitoring portion.

Abstract: The embodiments of the present invention introduced and taught herein are directed to a whole-chip ESD protection arrangement that is independent of relative supply rail voltage and supply sequencing, thereby enabling ESD conduction path during ESD event and isolating the ESD conduction path during the power up and power down modes of the chip. An embodiment of the present invention uses the bi-directional R-C clamp with transistorized arrangements between powered rails and avoids the drawback of using uni-directional Clamps or diode array for clamping that consumes large silicon area, requires power sequencing and is prone to noise coupling between power rails.

Abstract: A three-terminal snapback device is utilized with a control circuit to provide a low snapback voltage that is protected from non-ESD voltage spikes and ripples. In response to a fast edge, the control circuit lowers the snapback voltage, unless a status signal indicates that normal operating voltages are present, and raises the snapback voltage a predefined time later. If the fast edge represents an ESD pulse, SCR operation is initiated at the lowered snapback voltage. If the fast edge represents a power on sequence, the maximum voltage is less than the momentarily lowered snapback voltage and therefore insufficient to initiate SCR operation. Further, once normal operating voltages are present, the control circuit continuously maintains the raised snapback voltage so that a non-ESD voltage spike or ripple can not improperly turn on the snapback device.

Abstract: A power supply device having an overvoltage cutoff function, an image display device, and a method of cutting off overvoltage are provided. The power supply device includes a switch unit which cuts off a power supply to the power supply device; and an overvoltage sensing unit which compares a voltage of the power supply device with a specified reference voltage, and if the voltage of the power supply device is higher than the specified reference voltage, generates an overvoltage cutoff signal to control the switch unit. The overvoltage cutoff signal is used to report a power supply cutoff state. Accordingly, the damage of the power supply device due to an unstable AC input voltage can be prevented and the user can be alerted to the overvoltage through the display of the power supply cutoff state.

Abstract: Example embodiments are directed to an over-voltage protection circuit and method thereof. The over-voltage protection circuit may include a voltage converter, a voltage comparator, a delay unit, and/or a switching unit. The voltage converter may be configured to generate first voltage and second voltages from a supply voltage. The voltage comparator may be configured to compare the first voltage with the second voltage and to generate a control signal according to the comparison result. The switching unit may be configured to determine whether to apply the supply voltage to a chip in response to the control signal. The delay unit may be configured to delay transmission of the control signal to the switching unit by a delay time.

Abstract: An apparatus for protecting an integrated circuit is applied to an electrical apparatus having a control unit. The control unit is used for controlling the integrated circuit and the protecting apparatus. The protecting apparatus includes a power input terminal, a power output terminal, and a control terminal. The power input terminal is used for receiving a power, and the power output terminal is used for outputting the power to the integrated circuit. The control terminal is used for receiving a control voltage of the control unit. When the control unit is at the power on mode, the control unit outputs the control voltage of a first level to prevent the power being input to the integrated circuit. Over a predetermined period of time, the control unit outputs the control voltage of a second level, so that the power can be input to the integrated through the protecting apparatus.

Abstract: A control circuit for a frequency converter is provided. The control circuit includes a switch circuit, a timer switch, a starter circuit, a starter relay, and a timer relay. The control circuit is capable of keeping the frequency converter on for a predetermined time period when the voltage level of the power supply is below a predetermined voltage level in order to keep the equipment operating. After the lapse of the predetermined period, if the voltage level is still below the predetermined voltage level, the circuit stops to the operation of the equipment to protect the equipment.

Abstract: An over voltage and surge voltage preventing circuit for a display module includes resistors that divide an input voltage. A first switching device is turned on when a voltage-divided value made by the resistors is larger than a reference voltage. A second switching device is connected to an output terminal of the first switching device to carry out a switching operation contrary to the first switching device. A third switching device has a control terminal connected to an output terminal of the second switching device to carry out the same switching operation as the second switching device, thereby shutting off said over voltage to output only a normal input voltage. A time constant circuit delays an input voltage supplied from a turn-on time of the power supply by a predetermined time constant to prevent a generation of surge voltage.

Abstract: A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.

Abstract: A synchronous DC-DC regulator, adapted to receive a high side pulsed signal and a low side pulsed signal that is substantially the inverse of the high side pulsed signal. The regulator includes an inductor, and a capacitor having one port connected to ground, and having a second port providing an output voltage of the DC-DC. A driver is provided for driving pulses of current to the inductor when the high side pulsed signal is asserted. A switch and a diode are provided, adapted to provide a path for the inductor to drive current to charge the capacitor when the high side pulsed signal is not asserted. An undercurrent sense circuit is adapted to sense a driving current flowing through the driver and to assert a disable signal when the driving current is less than a predetermined amount.

Abstract: A circuit for preventing high voltage damage to a MOSFET switch in series with an inductor when current flow is interrupted. Specifically, the present invention discloses a protection circuit comprising a PMOS coupled in series to a load, an inductor, and a re-chargeable battery cell. The PMOS is switched to a non-conductive state by a switch in order to prevent over-loading the protection circuit. A clamp circuit temporarily allows the PMOS to conduct when a positive rate change of voltage with respect to time occurs at the gate of the PMOS. The clamp circuit is coupled to the gate of the PMOS. In one embodiment, the clamp circuit has an RC time constant and is comprised of an NMOS, a capacitor, and a pull-down resistor.

Abstract: A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.

Abstract: An over voltage and surge voltage preventing circuit for a display module includes resistors that divide an input voltage. A first switching device is turned on when a voltage-divided value made by the resistors is larger than a reference voltage. A second switching device is connected to an output terminal of the first switching device to carry out a switching operation contrary to the first switching device. A third switching device has a control terminal connected to an output terminal of the second switching device to carry out the same switching operation as the second switching device, thereby shutting off said over voltage to output only a normal input voltage. A time constant circuit delays an input voltage supplied from a turn-on time of the power supply by a predetermined time constant to prevent a generation of surge voltage.

Abstract: An IGBT gate driver circuit includes means for detecting when the collector-to-emitter voltage (Vce) of a turned-on IGBT, intended to be operated in the saturation region, increases above a preset level, indicative of a fault condition, such as a short circuit. In response to such an increase in the Vce of a turned on IGBT, the IGBT is turned-off in two steps. First, the turn-on gate drive is decreased to a level that is still above the threshold (turn-on) voltage of the IGBT in order to decrease the current flowing through the IGBT and hence, the peak power dissipation. This decrease in the current through the IGBT and the peak power dissipation increases the length of time the IGBT can withstand a fault condition such as a short circuit. Then, after decreasing the gate drive to the IGBT, the gate drive is gradually decreased until the IGBT is completely turned off.