Including Semiconductor Means Patents (Class 363/60)
  • Patent number: 11909397
    Abstract: The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 20, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shintaro Harada, Takayuki Ikeda
  • Patent number: 11882530
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may operate in a dual-connectivity (DC) configuration, and may measure signals from more than one radio access technology (RAT). The UE may receive a first signal power for a first RAT and a second signal power for a second RAT. The UE may determine a common gain state for the first RAT and the second RAT based on the first signal power and the second signal power. The UE may then apply the common gain state to a first receiver chain within the UE for the first RAT and to a second receiver chain within the UE for the second RAT, where the first receiver chain and the second receiver chain share at least one shared low noise amplifier (LNA).
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Harish Venkatachari, Paolo Minero, Rui Li, Qian Ma, Antriksh Pany, Masoud Azmoodeh, Yu Fu, Ashwin Alur Sreesha, Rimal Patel, Arpit Chitransh
  • Patent number: 11863066
    Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 2, 2024
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Vikas Rana, Marco Pasotti, Fabio De Santis
  • Patent number: 11855455
    Abstract: Systems and methods for power start up in a multi-unit power distribution network contemplate selectively disconnecting and reconnecting a remote subunit from a power conductor in a power distribution network at a relatively low frequency while providing short current pulses (at a low duty cycle) with enough energy transfer to power conditioning elements within the remote subunit during a start-up sequence. Once the power conditioning elements are properly charged, the remote subunit may change frequencies of the disconnecting and reconnecting so as to synchronize such disconnections to an expected frequency at the power source. Circuitry at the power source may measure activity on the power conductors regardless of frequency to detect an unwanted load on the power conductors (e.g., a human contacting the power conductors).
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: December 26, 2023
    Assignee: Corning Research & Development Corporation
    Inventor: Ami Hazani
  • Patent number: 11837953
    Abstract: First and second circuit branches are coupled between an input node and ground. Each circuit branch includes a series coupling first-fourth transistors in a current flow path with an output node. A first capacitor is coupled between a first capacitor node and a second capacitor node intermediate the first transistor and the second transistor in the first circuit branch. A second capacitor is coupled between a third capacitor node and a fourth capacitor node intermediate the first transistor and the second transistor in the second circuit branch. An inter-branch circuit block between the first and second branches includes a first inter-branch transistor coupled between the first capacitor node in the first circuit branch and the fourth capacitor node in the second circuit branch and a second inter-branch transistor coupled between the third capacitor node in the second circuit branch and the second capacitor node in the first circuit branch.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 5, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Dago, Alessandro Gasparini, Osvaldo Enrico Zambetti, Salvatore Levantino, Massimo Antonio Ghioni
  • Patent number: 11824441
    Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dong Pan, Beau D. Barry, Liang Liu
  • Patent number: 11817149
    Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: November 14, 2023
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 11804775
    Abstract: In some examples, a device includes a selector circuit configured to deliver power to a first driver circuit, where the first driver circuit is configured to activate and deactivate a first switch of a postregulator. The device also includes a startup regulator and a controller configured to cause the selector circuit to deliver power from the startup regulator to the first driver circuit. The controller is also configured to determine that a boost regulator is operational after delivering power from the startup regulator to the first driver circuit. The controller is further configured to cause the selector circuit to deliver power from the boost regulator to the first driver circuit in response to determining that the boost regulator is operational.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: October 31, 2023
    Assignee: Infineon Technologies AG
    Inventors: Cristian Garbossa, Alberto Arpino, Michele Bergo, Dario Cappuzzo, Bogdan Dimitriu, Vlad Alexandru Mircea Ionescu, Paola Lops, Luca Scandola, Ozan Serpedin, Silvia Solda
  • Patent number: 11777398
    Abstract: Circuitry for bootstrapping and precharging a gate of a field-effect transistor (FET) is disclosed. In one embodiment, an apparatus includes a first transistor coupled to a switching node and further coupled to receive a supply voltage from a supply voltage node, and a second transistor coupled between the switching node and a ground node, wherein the first and second transistors are of a same type. A precharge circuit is configured to precharge a gate terminal of the first transistor to a voltage that is less than a supply voltage on the voltage supply node. The apparatus also includes a bootstrap circuit. Subsequent to precharging the gate terminal of the first transistor, the bootstrap circuit is configured to cause activation of the first transistor by charging the gate terminal to a voltage greater than the supply voltage.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: October 3, 2023
    Assignee: Apple Inc.
    Inventors: Giulio Maria Iadicicco, Michael Couleur, Siarhei Meliukh
  • Patent number: 11757355
    Abstract: The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: September 12, 2023
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Rajasekhar Nagulapalli, Simon Forey, Parmanand Mishra
  • Patent number: 11757357
    Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Takao Oshita, Fabrice Paillet, Rinkle Jain, Jad Rizk, Danny Bronstein, Ahmad Arnaot
  • Patent number: 11742033
    Abstract: According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and a first switch. The first boost circuit outputs a first voltage. The voltage division circuit divides the first voltage. The first detection circuit is configured to detect a first monitor voltage supplied to the first input terminal, based on a reference voltage which is supplied to a second input terminal of the first detection circuit, and to control an operation of the first boost circuit. The capacitor is connected between an output terminal of the first boost circuit and the first input terminal of the first detection circuit. The first switch cuts off a connection between the capacitor and the first detection circuit, based on an output signal of the first detection circuit, until the first voltage is output from the first boost circuit.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: August 29, 2023
    Assignee: Kioxia Corporation
    Inventors: Tatsuro Midorikawa, Masami Masuda
  • Patent number: 11716022
    Abstract: A power converter is disclosed. The power converter includes a switching circuit coupled to a capacitor and further coupled to a regulated power supply node via an inductor. The switching circuit is configured to magnetize the inductor, using the capacitor, in response to activation of a first control signal, and further configured to charge the capacitor, using an input power supply, in response to activation of a second control signal. A control circuit is configured to activate the first control signal based on a comparison of a first threshold value and a current flowing in the inductor. The control circuit is further configured to activate the second control signal based on a comparison of a second threshold value and the current flowing in the inductor.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: August 1, 2023
    Assignee: Apple Inc.
    Inventors: Giovanni Tarroboiro, Pietro Gabriele Gambetta
  • Patent number: 11689202
    Abstract: Disclosed herein are non-limiting examples of voltage generators that use multiple charge pumps coupled in series to generate a targeted voltage. The charge pumps implement multiple charge pump units that reduce the introduction of noise into a circuit in which they are implemented. The charge pumps units work in parallel on different clock phases to reduce spurious noise. This is in contrast to using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: June 27, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Florinel G. Balteanu, Paul T. DiCarlo
  • Patent number: 11646658
    Abstract: Charge pump stages are coupled between flying capacitor pairs and arranged in a cascaded between a bottom voltage line and an output voltage line. Gain stages apply pump phase signals having a certain amplitude to the charge pump stages via the flying capacitors. A feedback signal path from the output voltage line to the bottom voltage line applies a feedback control signal to the bottom voltage line. Power supply for the gain stages is provided by a voltage of the feedback control signal in order to control the amplitude of the pump phase signals. An asynchronous logic circuit generates the switching drive signals for the gain stages with a certain switching frequency which is a function of a logic supply voltage derived from the voltage of the feedback control signal.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: May 9, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Alessandro Gasparini, Alberto Cattani
  • Patent number: 11644798
    Abstract: A power supply circuit module for a TDC (Time to Digital Converter) includes a first input for receiving a control signal, a second input for receiving a power supply voltage, and an output configured to be connected to the power supply input of the TDC. An active main power supply device is configured to receive the control signal at the input and to contribute on the value of the power supply voltage resulting at an output by a voltage value lower than a first predefined percentage with respect to the nominal power supply voltage. A number N of active secondary power supply devices each are configured to contribute on the value of the power supply voltage resulting at the output by a percentage different from the remaining active secondary power supply devices.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: May 9, 2023
    Assignee: FONDAZIONE BRUNO KESSLER
    Inventor: Matteo Perenzoni
  • Patent number: 11641159
    Abstract: Circuits and methods that can rapidly detect voltage degradation in a positive charge pump output and discharge control node accumulated charge (CNAC), thereby forcing the positive charge pump into a high-power mode. Embodiments include circuitry configured to provide a load current to a positive charge pump, including a low-dropout regulator (LDO) having a pass device that includes a control input, and a rapid charge transfer circuit coupled to the control input of the pass device and configured to be coupled to a source of a trigger voltage, the rapid charge transfer circuit configured to transfer a charge to or from the control input of the pass device when the trigger voltage falls sufficiently below a specified level so as to rapidly place the pass device in a higher conduction state, and to automatically cease to provide the transfer the charge after a settable amount of time.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: May 2, 2023
    Assignee: pSemi Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 11601037
    Abstract: A rectangular-wave-signal generating circuit according to an embodiment comprises: a sawtooth-wave output circuit; a first detector; a second detector; and a first PWM-signal output circuit. The sawtooth-wave output circuit is configured to generate and output a sawtooth-wave signal synchronized with a clock signal. The first detector is configured to detect a first timing at which a potential of the sawtooth-wave signal exceeds a bottom potential. The second detector is configured to detect a second timing at which a potential of the sawtooth-wave signal exceeds a potential of a first pulse-width instruction voltage signal. The first PWM-signal output circuit is configured to generate a first PWM signal based on a time difference between the first timing and the second timing.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 7, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Toshimasa Namekawa
  • Patent number: 11594959
    Abstract: A switched capacitor voltage multiplication device has a rectifier with a DC input terminal and a DC output terminal and two pulse input terminals. A first flying capacitor is coupled to one of the pulse input terminals, while a second flying capacitor is coupled to the other pulse input terminal. A recycle resistor is coupled across the rectifier with a first resistor terminal coupled to one pulse input terminal and a second resistor terminal coupled to the other pulse input terminal.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 28, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy Bryan Merkin, John Russell Broze, Orlando Lazaro
  • Patent number: 11569738
    Abstract: Disclosed is a multi-stage charge pump. A first stage is controlled by a first clock signal. A second stage is controlled by a second clock signal, which has high and low states that are shifted relative to the high and low states of the first clock signal. The high and low states of the second clock signal can be higher than the high and low states, respectively, of the first clock signal for a positive charge pump and vice versa for a negative charge pump. Any additional stage is similarly controlled by an additional clock signal that is shifted with respect to the clock signal controlling the immediately preceding stage. By shifting the high and low states of clock signals controlling downstream stages, the need for series-connected or high voltage capacitors in the downstream stages is eliminated and circuit complexity and area consumption are reduced.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 31, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventor: Siva K. Chinthu
  • Patent number: 11552558
    Abstract: A charge pump having only NMOS devices charges a plurality of capacitors to a parallel charged voltage level by electrically connecting the capacitors in parallel between an input voltage node and a ground by activating a plurality of first NMOS transistor switches and a plurality of second NMOS transistor switches and deactivating a plurality of third NMOS transistor switches. The charge pump then generates a series capacitor output voltage level at a capacitor series output node by electrically connecting and discharging the capacitors in series between the input voltage node and the capacitor series output node by activating the third NMOS transistor switches and deactivating the first NMOS transistor switches and the second NMOS transistor switches.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: January 10, 2023
    Assignee: Silanna Asia Pte Ltd
    Inventors: Joseph H. Colles, Steven E. Rosenbaum, Stuart B. Molin
  • Patent number: 11539288
    Abstract: Devices and methods for operating a charge pump. In some implementations, a charge pump module includes a clock circuit configured generate to a first clock signal and a second clock signal, the first clock signal having a lower frequency than the second clock signal. The charge pump module also includes a driving circuit configured to generate a first set of clock signals based on the first clock signal and a second set of clock signals based on the second clock signal, the driving circuit coupled to the clock circuit. The charge pump module further includes a charge pump core including a set of capacitances, the charge pump core configured to charge the set of capacitances based the first set of clock signals and the second set of clock signals.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: December 27, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventors: Bo Zhou, Guillaume Alexandre Blin
  • Patent number: 11539289
    Abstract: A multi-level charge pump (MCP) circuit is provided. The MCP circuit includes a multi-level voltage circuit configured to receive a supply voltage and generate a low-frequency voltage. The multi-level voltage circuit includes a first switch path, a second switch path, and a third switch path each having a respective on-resistance and coupled in parallel between an input node and an output node. In a non-limiting example, the multi-level voltage circuit is configured to activate the first switch path and at least one of the second switch path and the third switch path when the multi-level voltage circuit generates the low-frequency voltage that equals the supply voltage. By activating at least two of the three switch paths to generate the low-frequency voltage, it may be possible to reduce an equivalent resistance of the multi-level voltage circuit, thus helping to improve efficiency and reduce power loss of the MCP circuit.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: December 27, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Jeffrey D. Potts, Michael R. Kay, Michael J. Murphy
  • Patent number: 11530947
    Abstract: Described herein is an electronic device, including a pixel and a turn-off circuit. The pixel includes a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage node and an anode selectively coupled to ground through an enable circuit, and a clamp diode having an anode coupled to the anode of the SPAD and a cathode coupled to a turn-off voltage node. The turn-off circuit includes a sense circuit coupled between the turn-off voltage node and ground and configured to generate a feedback voltage, and a regulation circuit configured to sink current from the turn-off voltage node to ground based upon the feedback voltage such that a voltage at the turn-off voltage node maintains generally constant.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: December 20, 2022
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: John Kevin Moore
  • Patent number: 11527952
    Abstract: During its first and second residence times, corresponding first and second currents flow between a charge pump and a circuit that connects to one of the charge pump's terminals. Based on a feedback measurement from the charge pump, a controller adjusts these first and second currents.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: December 13, 2022
    Assignee: PSEMI CORPORATION
    Inventors: Tim Wen Hui Yu, Gregory Szczeszynski
  • Patent number: 11487253
    Abstract: A sequential or cascading predictive control method is provided, including first solving a cost function and then a second cost function for two or more control objectives. The method includes separating the cost function into at least two or more cost functions, depending on the number of defined control objectives. The method additionally includes controlling a first variable with a unitary cost function, a single term or nature of the control objectives. The method also includes determining the possible states that minimize the cost of the first objective to be controlled. Considering only the options given through this determination, a second variable is controlled with a cost function that minimizes the cost function thereof.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: November 1, 2022
    Assignee: UNIVERSIDAD ANDRES BELLO
    Inventors: Margarita Norambuena Valdivia, Jose Rodriguez Perez
  • Patent number: 11424675
    Abstract: A circuit design for efficiently transferring significant levels of electrical power with non-inductive circuit elements. Power is transferred using synchronously-switched capacitive elements in such a way that both discharge from the power source and charge transferred to a load (and/or back to the power supply) are supplied as low duration, high-intensity current pulses. The synchronous power transfer alternates between connecting capacitive charge storage elements in parallel and in series so that both step-up and step-down topologies may be readily realized.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: August 23, 2022
    Assignee: APPARENT ENERGY, INC.
    Inventors: Hani Henri Hajje, Brett C. Belan, Adam Reed
  • Patent number: 11418131
    Abstract: A voltage balance control method for a flying-capacitor multilevel converter is provided. If the amplitude of the resultant current of the inductor currents from a plurality of output inductors is lower than or equal to a threshold current value, the flowing direction of the inductor current of at least one flying-capacitor multilevel branch circuit is controlled to be changed. Consequently, the problem of erroneously judging the current direction is avoided. Moreover, when the inductor current is low, the voltage of the flying capacitor is correspondingly controlled. Consequently, the voltage balance of the flying capacitor of the flying-capacitor multilevel converter can be achieved more easily.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 16, 2022
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Guoqiao Shen, Guojin Xu, Ning He, Jinfa Zhang
  • Patent number: 11411493
    Abstract: A two-stage power converter includes: a resonant switched-capacitor converter (RSCC) receiving an input voltage and generating a first stage voltage; a voltage regulator receiving the first stage voltage and generating an output voltage; and a communication interface and control circuit generating a charging operation signal, at least one discharging operation signal and a switching signal. The charging operation signal and the discharging operation signal are employed to control the RSCC to perform a charging process and at least one discharging process respectively, and the switching signal is employed to control the voltage regulator, so as to synchronize a resonant frequency of the RSCC and a switching frequency of the voltage regulator. The communication interface and control circuit adjusts a delay interval after the discharging process ends, and starts the charging process at an end time point of the delay interval.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: August 9, 2022
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kuo-Chi Liu, Ta-Yung Yang, Chung-Lung Pai
  • Patent number: 11411490
    Abstract: Charge pumps with accurate output current limiting are provided herein. In certain embodiments, a charge pump includes an output terminal for providing a regulated output voltage, a switched capacitor, and switches that control connectivity of the switched capacitor to selectively charge or discharge the switched capacitor. The switches are operable in two or more phases including a charging phase in which the switched capacitor is charged with a charging current and a discharging phase in which the switched capacitor is coupled to the output terminal. The charge pump further includes an output current limiting circuit that controls the charging current to limit an amount of output current delivered by the charge pump to the output terminal. The output current limiting circuit limits the output current based on comparing a reference signal to an integral of an observation current that changes in relation to the charging current.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: August 9, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventor: William L. Walter
  • Patent number: 11387654
    Abstract: A distributed control system uses a central controller in Internet communication with a local controller to manage grid tie attachment with a battery to form an integrated battery energy storage system (BESS). The BESS is capable of charging or discharging the battery, as well as correcting grid phase with volt amp reactive (VAR) leading or lagging operation modes. Examples shown include simple BESS charging and discharging, BESS integrated with renewable energy sources (here photovoltaic), and direct current fast charge (DCFC) connections with an electric vehicle.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: July 12, 2022
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Rajit Gadh, Hamidreza Nazaripouya, Chi-Cheng Chu
  • Patent number: 11381163
    Abstract: A resonant charge pump circuit includes a resonant circuit having a bucket capacitor and a bucket inductor connected in series, and a switching circuit connected to the resonant circuit. The switching circuit switches to a first state that enables current to flow from an input terminal into the resonant circuit to charge the bucket capacitor and the bucket inductor, and switches to a second state that enables current to flow from the resonant circuit to discharge the bucket capacitor and the bucket inductor to an output terminal. The resonant circuit controls current flow into and out from the resonant circuit when the switching circuit switches between the states. The resonant charge pump circuit also includes a timing circuit that controls when the switching circuit switches between the states.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 5, 2022
    Assignee: ACTIVE-SEMI, INC.
    Inventor: Masashi Nogawa
  • Patent number: 11368107
    Abstract: A multi-level switched capacitor boost inverter includes a series connection of a two-switched capacitor circuit, a source module and at least one one-switched capacitor circuit. Level-shifted pulse width modulation is used to apply gate pulses to the switches. The multi-level switched capacitor boost inverter uses only three capacitors and a single DC voltage source to generate thirteen voltage levels at load terminals with a voltage gain of three. The capacitors of the two-switched capacitor circuit are self-balancing. Additional one-switched capacitor circuits can be added in series with the inverter. Each additional one-switched capacitor circuit increases the number of levels and increases the gain by one.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: June 21, 2022
    Assignee: King Abdulaziz University
    Inventors: Hussain Bassi, Muhyaddin Rawa, Saad Mekhilef, Marif Daula Siddique, Noraisyah Binti Mohamed Shah
  • Patent number: 11336176
    Abstract: An internal voltage generation circuit may include an oscillation circuit, a signal generation circuit, and a pumping circuit. The oscillation circuit may generate an oscillation signal. The signal generation circuit may generate first and second pumping driving signals on the basis of the oscillation signal. The pumping circuit may generate a pumping voltage through a pumping operation on the basis of the first and second pumping driving signals.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: May 17, 2022
    Assignee: SK hynix Inc.
    Inventor: Seok In Hong
  • Patent number: 11336175
    Abstract: Operating a charge pump in which switches from a first set of switches couple capacitor terminals to permit charge transfer between them and in which switches from a second set of switches couple capacitor terminals of capacitors to either a high-voltage or a low-voltage terminal includes cycling the switches through a sequence of states, each state defining a corresponding configuration of the switches. At least three of the states define different configurations of the switches. During each of the configurations, charge transfer is permitted between a pair of elements, one of which is a first capacitor and another of which is either a second capacitor or the first terminal.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 17, 2022
    Assignee: pSemi Corporation
    Inventors: Aichen Low, Gregory Szczeszynski, David Giuliano
  • Patent number: 11294438
    Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: receive, by an information handling system that includes a first portion and a second portion, power from a first power supply; determine that the second portion, coupled to the first portion, requires a portion of the power from the first power supply; determine a first voltage value associated with the power from the first power supply; charge multiple capacitors of first circuitry at a first voltage associated with the first voltage value; discharge the multiple capacitors of the first circuitry to the second circuitry; charge multiple capacitors of second circuitry at a second voltage associated with a second voltage value; and discharge the multiple capacitors of the second circuitry to provide the portion of the power from the first power supply to one or more components of the second portion.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: April 5, 2022
    Assignee: Dell Products L.P.
    Inventors: Jace William Files, Gerald Rene Pelissier
  • Patent number: 11271475
    Abstract: Disclosed is an N:1 (where N is an integer such as 3 or higher) resonant star topology converter to generate an input supply (e.g., 1.8V) for a processor (e.g., a system-on-chip (SOC)) from a higher power supply source (e.g., 12.6V) such as a battery or other source. The resonant star topology based regulator can be realized by a combination of on-die and on-package components as opposed to voltage regulators on motherboard with discrete inductor and capacitors. In one example, capacitors of the N:1 resonant star topology are implemented as multilayer ceramic capacitors (MLCC). The architecture of the N:1 resonant star topology based regulator results in high bandwidth. For example, compared to traditional step-down voltage regulators, the N:1 resonant star topology based regulator exhibits ten times higher bandwidth.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Rinkle Jain, Jonathan Douglas, Shivadarshan Rajeurs
  • Patent number: 11258358
    Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: February 22, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Shivam Kalla
  • Patent number: 11251705
    Abstract: A switched mode power supply includes a multilevel buck power converter and a control circuit. The power converter includes a first buck circuit and a second buck circuit each having a power switch, a rectifier, and an inductor. The power supply may further include a resonant power converter coupled to the multilevel buck power converter. In some examples, the control circuit is configured to generate control signals for the first buck circuit's power switch and the second buck circuit's power switch to control the power converter, and adjust a switching frequency of the control signals to control the amount of reverse current flowing in the first buck circuit and the second buck circuit to achieve zero voltage switching of the first buck circuit's power switch and the second buck circuit's power switch. Other example multilevel buck power converters and power supplies are also disclosed.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 15, 2022
    Assignee: Astec International Limited
    Inventors: James Sigamani, Jonathan Ross Bernardo Fauni
  • Patent number: 11251710
    Abstract: A non-isolated multiport DC/DC converter topology is provided. The non-isolated multiport DC/DC converter topology is modular and can incorporate an unlimited number of independent input or output ports. The efficiency of the non-isolated multiport DC/DC converter topology is improved through partial power processing techniques without having isolation in the converter. The non-isolated multiport DC/DC converter topology also provides a balanced DC neutral point, making it an ideal candidate for bipolar DC grid or as the front-end of a multilevel DC/AC converter.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 15, 2022
    Inventors: Yunwei Li, Zhongyi Quan
  • Patent number: 11251719
    Abstract: Switched capacitor multilevel inverter (SCMLI) configuration for high-frequency medium voltage applications is presented. A 5L-SCMLI basic configuration is further extended to 9L operation with a reduced number of active switches having self voltage boosting and balancing ability. Further, the proposed 9L-SCMLI is extended up to n level being considered as the basic configuration for the extension of horizontal extension (HE) and vertical extension (VE). A generalized switching table is provided for the proposed extensions. Design of the size of capacitor demonstrated for the proposed 9L-SCMLI.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 15, 2022
    Assignee: KING ABDULAZIZ UNIVERSITY
    Inventors: M. Jagabar Sathik, Kaustubh Bhatnagar, Yam P. Siwakoti, Hussain M. Bassi, Muhyaddin Rawa, N. Sandeep
  • Patent number: 11245324
    Abstract: A control circuit having: a logic circuit, configured to provide a high side boot-strap capacitor control signal set and a low side boot-strap capacitor control signal set; a high side boot-strap capacitor control circuit, configured to provide a high side power signal to control a high side power switch; a high side boot-strap capacitor, having a first terminal coupled to a control terminal of the high side power switch, and a second terminal coupled to the high side boot-strap capacitor control circuit; a low side boot-strap capacitor control circuit, configured to provide a low side power signal to control a low side power switch; and a low side boot-strap capacitor, having a first terminal coupled to a control terminal of the low side power switch, and a second terminal coupled to the low side boot-strap capacitor control circuit.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: February 8, 2022
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Naixing Kuang
  • Patent number: 11239836
    Abstract: A circuit and a method for providing a switchable current linkage between a first terminal and a second terminal is presented. The circuit has a transistor switch and a charge pump circuit. An output node of the charge pump circuit is coupled to a control terminal of the transistor device, and an input node of the charge pump circuit is coupled to a predetermined voltage. The charge pump generates a boosted voltage. A drive circuit provides feedback control for the current flowing through the transistor. The drive circuit also controls the voltage magnitude at the input node of the charge pump circuit in accordance with the feedback control or to control a magnitude of a voltage at the control terminal of the transistor device in accordance with the feedback control.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: February 1, 2022
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Jerome Sanchez, Fabio Rigoni, Jan Grabinski, Ali Zahabi
  • Patent number: 11190098
    Abstract: The present application discloses a voltage booster circuit and a related circuit, chip and wearable device. The voltage booster circuit has an output terminal, which provides an output voltage and a load current. The voltage booster circuit includes: a first charge pump, which provides a first bias current; a second charge pump, which provides the load current; an output voltage fixing circuit, which draws the first bias current from the first charge pump to the output terminal, wherein the output voltage fixing circuit fixes a first charge pump voltage of the first charge pump by fixing the first bias current and further fixes the output voltage based on the fixed first charge pump voltage; and a load current generation circuit, which draws the load current from the second charge pump to the output terminal based on a second charge pump voltage of the second charge pump.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: November 30, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Wen-Chi Wang
  • Patent number: 11190182
    Abstract: Disclosed herein are non-limiting examples of charge pumps that reduce the introduction of noise into a circuit in which they are implemented and/or lower the output impedance when providing certain voltages (e.g., negative voltage generators). The disclosed technologies utilize a plurality of smaller charge pumps (or charge pump units) working in parallel that operate on different clock phases rather than using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 30, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Florinel G. Balteanu, Paul T. DiCarlo
  • Patent number: 11177735
    Abstract: During its first and second residence times, corresponding first and second currents flow between a charge pump and a circuit that connects to one of the charge pump's terminals. Based on a feedback measurement from the charge pump, a controller adjusts these first and second currents.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: November 16, 2021
    Assignee: pSemi Corporation
    Inventors: Tim Wen Hui Yu, Gregory Szczeszynski
  • Patent number: 11169182
    Abstract: A voltage divider circuit arrangement includes a resistive divider circuit portion constructed from first and second resistors (R1, R2) The first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node between them. A capacitive divider circuit portion is constructed from first and second capacitors (C1, C2). The first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node. A switching circuit portion is arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider is disabled and the output node is not connected to the refresh node.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: November 9, 2021
    Assignee: Nordic Semiconductor ASA
    Inventors: Lukasz Farian, Ola Bruset, Werner Luzi
  • Patent number: 11133742
    Abstract: A current control circuit can include: a current detection circuit configured to obtain a current detection signal for characterizing an output current of a switched capacitor converter, where the switched capacitor converter includes a plurality of first switch groups coupled between an input terminal and a ground, and where each first switch group comprises two switches coupled in series; and a voltage regulation circuit configured to regulate the output current by adjusting an equivalent impedance of the switched capacitor converter in accordance with the current detection signal.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 28, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Wang Zhang, Chen Zhao
  • Patent number: 11095282
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Pavol Balaz
  • Patent number: RE49767
    Abstract: In a power converter, each gate-driving circuit uses charge from a selected pump capacitor operate a corresponding switch. The switches transitions between different states, each of which corresponds to a particular interconnection of pump capacitors. During clocked operations, the first switch closes, thereby establishing a connection with the first pump capacitor. Prior to the first switch closing, the second switch closes.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 26, 2023
    Assignee: PSEMI CORPORATION
    Inventors: Gregory Szczeszynski, David M. Giuliano, Raymond Barrett, Jr.