Abstract: The invention relates to a first circuit arrangement (E) for supplying variable loads that can be connected to the first circuit arrangement (E) from a first current or voltage source (MV) in a first state of the first circuit arrangement having the following features: the first circuit arrangement (E) has a first terminal and a second terminal for connection to the first current or voltage source (MV) and a third terminal, at least one fourth terminal and at least one fifth terminal for connection to a second current or voltage source (Z); the second terminal is at a reference potential; the first circuit arrangement (E) has at least one eighth terminal for connection to two loads (R2; R3); the first circuit arrangement (E) has controllable switching means for changing over between the first state and a second state; in the first state, the at least one eighth terminal for connection to the two loads (R2, R3) is connected to the first terminal and the third terminal and the fifth terminal are connected to th

Abstract: A charge pump circuit with a regulated charge current where the amount of current flowing into the flying capacitor depends on the magnitude of the output voltage error, using an OTA to convert the output voltage error into a current. Thus the flying capacitor is not charged when the output load is very low or when the output voltage error is minimal. Voltage overshoots are reduced by a stop circuit which forces pulse skipping and which inhibits the charging of the flying capacitor. Current limiting devices further limit the charge current into the flying capacitor. Full short-circuit protection is provided in one preferred embodiment by current limiting the driver stage of the charge pump circuit. Except for pulse skipping, the charge pump runs at a constant frequency supplied by a clock.

Abstract: A pumping circuit of a semiconductor device includes a power supply unit for supplying a power source voltage to a first node, a first transfer pump for transferring a first electric potential of the first node to a second node, a first pumping unit coupled to the first node for pumping the power source voltage applied to the first node, a first pump control unit for controlling a voltage applied to a gate of the first transfer pump, a second transfer pump for transferring a second electric potential of the second node to a high voltage output terminal, a second pumping unit coupled to the second node for selectively pumping the second electric potential of the second node, and a second pump control unit for controlling a voltage applied to a gate of the second transfer pump in response to the power source voltage level. If the power source voltage is higher than a predetermined voltage, the first pumping unit performs a pumping operation, and the second pumping unit performs only an on or off operation.

Abstract: A voltage/voltage converter for integrated circuits is characterized in that it presents a multistage symmetrical structure and comprises at least one input stage constituted by a clock booster circuit (CB) of symmetrical structure which delivers two output voltages, a voltage multiplier stage of symmetrical structure comprising two voltage multiplier circuits (CMi; CMip) respectively connected in two branches (B1; B2) of the converter and having applied respectively thereto the output voltages from the first stage, and an output stage (S) constituted by a multiplexer circuit (MX) having applied thereto the two output voltages from the voltage multiplier stage. The invention is particularly applied to EEPROMs and to low-voltage integrated circuits.

Abstract: A switch control circuit (416, 402, 418, 422) and method are provided for transistor-implemented switches (405, 413, 408, 414) of an integrated floating power transfer device (400, 500). The device includes a floating bus (403, 410) driven by a power system which includes a charge pump circuit (419, 408, 414, 420). At least one switch circuit (405, 413) is coupled to the floating bus and the power system for facilitating charging of the floating bus. The switch control circuit (416, 402, 418, 422) includes a level shifting circuit (402) for adjusting a control signal to the at least one switch circuit notwithstanding floating of an input voltage signal thereto to facilitate operation of the switch circuit.

Abstract: A step-up/step-down circuit can be simplified as compared with conventional circuits by including a step-down unit for receiving a system clock pulse alternately providing a reference voltage (GND) and a system voltage VDD in a repeated manner to output a voltage V4 lower than the reference voltage (GND) by using a potential difference between the reference voltage (GND) and the system voltage VDD, a level shift unit for receiving the system clock pulse and the voltage V4 output from the step-down unit to output a pulse signal Vo having a greater potential difference than the potential difference between the reference voltage (GND) and the system voltage VDD, and a step-up unit for receiving the pulse signal Vo output from the level shift unit to output a voltage V7 higher than the reference voltage (GND).

Abstract: A switching arrangement for a high voltage load provides high voltage pulses to the load. The switching arrangement includes switching modules, where n is typically (75). A load capacitance is Cd is required to avoid voltage overshoot at the load and is provided by a capacitance of nCd arranged in parallel with each switch.

Abstract: A charge pump (1) for generating a first output voltage (Vo1) between a first output terminal (E) and a reference terminal (D), and a second output voltage (Vo2) between a second output terminal (F) and the reference terminal (D). The charge pump (1) further comprises a first input terminal (C) for inputting a DC voltage (V), a first storage capacitor (Cr1) coupled between the first output terminal (E) and the reference terminal (D) and a second storage capacitor (Cr2) coupled between the second output terminal (F) and the reference terminal (D). The charge pump (1) further comprises a first terminal (A) and a second terminal (B) for coupling a pump capacitor (Cp) to a first triplet of switches (S1, S2, S5) and to a second triplet of switches (S3, S4, S6). The first triplet of switches (S1, S2, S5) selectively couples the first terminal (A) to either the first input terminal (C) or to the reference terminal (D) or to the second output terminal (F).

Abstract: A charge pump circuit is provided for generating a voltage (1+1/n) times as high as a supply voltage. The charge pump circuit eliminates the need for diodes for preventing a current from flowing back from a high potential side of capacitors to prevent a reduction in the voltage due to a forward voltage, and reduces a reactive current and latch-up when the charge pump circuit is integrated into a single IC chip. The charge pump circuit includes a fourth switching element having a substrate gate connected to a drain for preventing a current from flowing back to an input terminal from a high potential side of fly back capacitors connected in series, and a second switching element having a substrate gate connected to a drain for preventing a current from flowing back from a high potential side of a catch-up capacitor to the fly back capacitors connected in series.

Abstract: A voltage-regulating device for charge pump is disclosed. The charge pump outputs an output voltage according to the operation of at least one clock signal. The voltage-regulating device includes at least one voltage regulating capacitor and at least inverter. The inverter is for receiving the clock signal and outputting an inverse clock signal accordingly. The voltage regulating capacitor has one terminal coupled to the output voltage and the other terminal coupled to the inverter for receiving the inverse clock signal. The width of a PMOS transistor is different from the width of an NMOS transistor in the inverter.

Abstract: A charge pump DC/DC converter circuit of the present invention includes: a monitor circuit that detects a potential difference between terminals of a semiconductor switch that turns on during a first period, so as to output a determining signal corresponding to the potential difference; and each of drive circuits that outputs a drive signal to a semiconductor switch that turns on during a first period, in response to the determining signal. The drive signal increases the on-resistance of the semiconductor switch in proportion to the detected potential difference.

Abstract: A charge pump is proposed. The charge pump is integrated in a chip of semiconductor material and includes a plurality of capacitive elements each one connected to a corresponding circuit node of the charge pump, the circuit nodes being arranged in a sequence from an input node to an output node, a plurality of field effect transistors each one for selectively connecting a corresponding first circuit node with a second adjacent circuit node, each transistor being made in a corresponding insulated body region, and for each transistor first biasing means for equalizing the body region with the first circuit node when the transistor is closed, wherein for each transistor the charge pump further includes second biasing means for equalizing the body region with the second circuit node when the transistor is opened.

Abstract: The present invention discloses a voltage up converter, including: a detector for detecting a level of an internal power to generate the internal power higher than an external power; an asymmetrical oscillator for generating a frequency in which a high level width and a low level width are different according to the output from the detector; and a pump for generating the internal power by performing a pumping operation according to the output from the asymmetrical oscillator.

Abstract: A power source device is provided including a boosting circuit for stepping-up an input voltage to a desired output voltage, a starter circuit for starting the boosting circuit in a starting period thereof, and a drive circuit for driving the boosting circuit as a substitute for the starter circuit after the output voltage of the boosting circuit becomes equal to or greater than a predetermined level. The starter circuit comprises a starter signal generation circuit for generating a starter signal which on/off controls a MOS transistor used for stepping-up in the boosting circuit, and a determining/controlling circuit which detects whether or not a monitor voltage in the boosting circuit is equal to or greater than a predetermined level while the MOS transistor is in the on-state, and inhibits outputting if the starter signal if the monitor voltage is equal to or greater than the predetermined level.

Abstract: A leakage path through a parasitic diode in a charge transfer MOS transistor is cut off to prevent increase in the power consumption and loss of control of a charge pump circuit. A first charge transfer MOS transistor and a second charge transfer MOS transistor are N-channel type and are connected in series with each other. A ground electric potential VSS is supplied to a source of the first charge transfer MOS transistor as an input electric potential, and an output electric potential is obtained from an output terminal connected with a drain of the second charge transfer MOS transistor. A back gate of the first charge transfer MOS transistor is set by a first switching circuit to either an electric potential at a connecting node between the first and the second charge transfer MOS transistors or the ground electric potential VSS.

Abstract: In a basic circuit of a booster circuit, two charging units perform a charging operation and two boosting units perform a boosting operation (discharging operation). One of the charging units is connected to a voltage input and the other is connected to a voltage output. The charging unit that is connected to the voltage input includes three parallel connected MOS transistors Q11, Q12, and Q13, the other charging unit includes a MOS transistor Q4. One of the boosting units is connected to the voltage input and the other is connected to the voltage output. The boosting unit that is connected to the voltage input includes three parallel connected MOS transistors Q31, Q32, and Q33, the other boosting unit includes a MOS transistor Q2. Q11 and Q31 are turned ON immediately after start up, then Q12 and Q32 are turned ON and finally Q13 and Q33 are turned ON.

Abstract: A reverse current is prevented in a charge pump circuit. A complementary pair of clocks CLK and *CLK varies while a first through a fourth charge transfer MOS transistors M11, M12, M13 and M14 are turned off. Then the second charge transfer MOS transistor M12 is turned on to discharge a first pumping capacitor CA and the third charge transfer MOS transistor M13 is turned on to charge a second pumping capacitor CB. Next, the complementary pair of clocks CLK and *CLK varies after the first through the fourth charge transfer MOS transistors M11, M12, M13 and M14 are turned off again. Then the fourth charge transfer MOS transistor M14 is turned on to discharge the second pumping capacitor CB and the first charge transfer MOS transistor M11 is turned on to charge the first pumping capacitor CA.

Abstract: A low noise charge pump circuit includes a first terminal of a first flying capacitor selectively coupled to a first voltage during a first recharging phase and a second terminal of the first flying capacitor selectively coupled to a second voltage during the first recharging phase. The second terminal of the first flying capacitor is coupled to a precharge control circuit during a first parasitic capacitance precharging phase that occurs after the first recharging phase to cause the voltage of the first terminal of the first flying capacitor to equal an output voltage. The first terminal of the first flying capacitor is coupled to an output conductor conducting the output voltage during a first discharging phase that occurs after the first parasitic capacitance precharging phase.

Abstract: A method for controlling a device including a plurality of switching devices operated in accordance with a pulse width modulation technique includes receiving a reference voltage signal associated with a first pair of the switching devices. A switching signal is generated. The first pair of switching devices are controlled based on the reference voltage signal and the switching signal in accordance with the pulse width modulation technique. A frequency of the switching signal is varied based on the value of the reference voltage signal.

Abstract: In an embodiment of the invention, a charge pump circuit has a latch-up prevention circuit. The latch-up prevention circuit has a depletion P-channel MOS transistor and a resistor serially connected with each other between a negative output terminal and a ground terminal. A first bidirectional PNP-transistor is connected between a back gate of the depletion MOS transistor and the ground terminal. A second bidirectional PNP-transistor is connected between the back gate of the depletion MOS transistor and the negative output terminal. A third bidirectional PNP-transistor is between the ends of the resistor to bypass it. The base of the first bidirectional PNP-transistor is connected to the negative output terminal, the gate of the depletion MOS transistor and the bases of the second and third bidirectional PNP-transistors are connected to the ground terminal.

Abstract: A voltage boosting circuit with a closed-loop control mechanism and a controllable slew rate. A tracking capacitor and a control current form the closed-loop and are used to adjust the slew rate of the boosting circuit. The closed-loop control and adjustable slew rate improve the accuracy and predictability of the boosting circuit's final boosted output voltage.

Abstract: In order to restrict variations of an output voltage of a DC—DC conversion circuit using TFTs, in a boost-type, a second n-ch TFT N2 and a second p-ch TFT P2 are newly provided. With regard to the second n-ch TFT N2, a gate thereof is connected to a second capacitor C2, a source thereof is connected to a first reference voltage source YVDD, and a drain thereof is connected to a first capacitor C1. With regard to the second p-ch TFT P2, a gate thereof is connected to the second capacitor C2, a source thereof is connected to a third capacitor C3, and a drain thereof is connected to the first capacitor C1. Thus, a voltage at the first capacitor C1 stops being influenced by the variations of a threshold voltage between a source and drain of a first diode D1.

Abstract: Embodiments provide a capacitive voltage multiplier for efficiently producing multiples, including fractional multiples, of a power supply voltage use high, medium and low voltage field effect transistors for switching terminals of various capacitors into and out of connection with power supply or ground voltages in charge mode and with an output or other capacitor terminals for series connection in pump mode. A single non-overlapping clock is level-shifted up to the maximum voltage level required for switching to produce a desired output, then level shifted back down to lower levels with delay added as necessary according to embodiments.

Abstract: A voltage regulator for supplying two types of loads on a common chip, namely a high current load and a low current load. The voltage regulator employs a feedback loop to supply the low current load with a fine degree of regulation and a feed forward arrangement to supply the high current load with a coarse degree of regulation. The feedback loop employs a bandgap reference source feeding a comparator, with an output driver transistor drawing current from a common supply and having an output electrode connected to a voltage divider, allowing a sample of the output to be fed back to the comparator to maintain the desired output voltage. The output electrode also feeds a control transistor for the feed forward arrangement that also draws current from the common supply and supplies the high current load directly.

Abstract: A multi-level high voltage generator according to embodiments of the invention is capable of simultaneously generating high voltages of various levels by using one charge pump. The multi-level high voltage generator includes a charge pump unit, a voltage divider unit, and a pump control unit. The charge pump unit raises an input voltage applied at an input terminal to simultaneously output a number of high voltages having different levels. The voltage divider unit divides the voltages from the charge pump unit. The pump control unit operates according to an enable signal and generates pump control signals in response to a reference voltage, a control clock signal, and a divided voltage from the voltage divider unit. The charge pump unit generates the high voltages and is controlled by the pump control signals from the pump control unit.

Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, and a charge pump type step-up circuit formed in the semiconductor substrate. The step-up circuit includes a charge pump circuit and a bipolar transistor. The charge pump circuit has an input line to which a power supply voltage is to be applied, and an output line through which an output voltage is to be output. The bipolar transistor is formed in the semiconductor substrate so as to be provided between the input line and the output line. The bipolar transistor is constituted so as to be turned ON when an absolute value of the output voltage is lower than an absolute value of the power supply voltage, and so as to be turned OFF when the absolute value of the output voltage is higher than the absolute value of the power supply voltage.

Abstract: An auxiliary power source (HQ) constructed with conventional components for generating an auxiliary voltage lying above the voltage of a power supply source (U1), in particular for triggering an n-channel MOS transistor (T11) used as a high-side switch for switching a load (I1). An energy store (L1) is connected via a switching element (T1) to the power supply source (U1) and an auxiliary voltage is generated at a power output (U3).

Abstract: A boost circuit includes: level shifters 3 and 4 for shifting a high level of a clock signal; a first boost means which contains transistors QP3 and QP4 for conducting switching in accordance with the clock signal whose high level has been shifted and capacitors C1 and C2 and, thereby, generates a power source potential VDC2 by conducting a charge pump operation; level shifters 1 and 2 for shifting a high level of a clock signal; inverters IV41 to IV52 for shifting a low level of the clock signal whose high level has been shifted; and a second boost means which contains transistors QP1 and QP2 for conducting the switching in accordance with the clock signal whose high level and low level have been shifted and capacitors C3 and C4 and, thereby, generates a power source potential VDC3 by conducting the charge pump operation.

Abstract: Circuits and methods to shut down any charge pump having any number of stages have been achieved. The invention is especially relevant to charge pumps, which have a supply that is incapable of sinking significant current, such as a supply derived from an LDO. The shutdown can be done either until all stages have zero voltage or until all stages have the input voltage level. The shutdown is performed in a staged manner, from the output backwards to the input, so there is reduced charge sharing between the capacitors so that no voltage exceeds its normal operating range. An additional advantage of the present invention is that the charge pump can be switched back on, before the shutdown sequence is complete, with all internal and external nodes of the charge pump staying within their normal operating range.

Abstract: A stabilized power supply circuit includes a charge pump power supply circuit including four switching elements and a capacitor, and an error amplifier comparing the output voltage of the charge pump power supply circuit and a reference voltage and outputting an error signal on the basis of the difference therebetween. A current source is connected in series to the gate of a switching element formed of a MOSFET. The period during which electric charge is discharged from the gate is controlled in accordance with the error signal in order to maintain the output voltage constant.

Abstract: A charge pump includes a plurality of capacitors that are alternately charged and serially coupled. When serially coupled, the voltage across a given capacitor will equal the voltage at its negative terminal and the voltage across the preceding capacitor.

Abstract: A photovoltaic inverter control method includes steps of monitoring a variation in output voltage of a solar battery by a power and voltage monitoring circuit (51) and, when the variation occurs, accelerating or decelerating an electric motor (3) to maximize the output voltage of the solar battery (1), whereby the electric motor for driving, for example, a pump and a fan by the solar battery as a power source can be driven by a photovoltaic inverter always at the maximum power point of the solar battery.

Abstract: A charge pump circuit has an input stage, an output stage and multiple boosting stages coupled between the input stage and the output stage. The boosting stages are driven by four phase clock signals. Each boosting stage has two branch charge pumps, wherein each branch charge pump at least has a main pass transistor, a pre-charge transistor, two substrate transistors and capacitors. The substrate transistors and the main pass transistor are operated in association with the four phase clock signals to keep a potential of the body of the main pass transistors at a low level thus mitigating the body effect.

Abstract: A power conversion circuit includes a current section, a transformer, and a voltage section. The current section includes inductors configured to produce a boosted output voltage from a voltage sourse when then current section is operating in a forward direction. The transformer includes a primary winding electrically coupled to the secondary winding and configured to drive a load. The voltage section includes a pluralaty of balancing switchtes configured to actively driven to provide a DC voltage to the load. The balancing switches balance energy between the current section and the voltage section when the power conversion circuit is the load and operating in the forward direction.

Abstract: A low power charge pump is disclosed. A pump driving node of a first pump stage is selectively coupled to a pump driving node of the subsequent pump stage. Subsequent to a transfer of charge from a first pump stage to a subsequent stage, the first and subsequent pump driving nodes are coupled. Residual charge on a first stage pump driving node is thereby transferred to a subsequent pump driving node. Subsequent to the transfer of charge from the first pump driving node to the second pump driving node, the nodes are uncoupled. By selectively coupling a first pump stage to a pump driving node of the subsequent pump stage, the first pump driving node may pre-charge the subsequent pump driving node, thereby reducing the energy that must be provided by clock driving circuitry to produce a positive-going transition of a driving clock.

Abstract: A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

Abstract: A voltage boosting circuit and a method of generating a boosting voltage alleviate deterioration of a driver transistor caused by high voltage stress when the level of an external supply voltage is high. The voltage boosting circuit includes boosting capacitors and switches. The boosting capacitors include a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage. The switches connect the boosting capacitors in series in response to a control signal. The boosting voltage increases or decreases as the voltage level at the driving node changes according to the logic state of a boosting level control signal. The boosting level control signal is responsive to the external supply voltage level. An external supply voltage detector detects the level of external supply voltage level and generates the boosting level control signal.

Abstract: A voltage boosting circuit, boosting power supply unit and methods thereof are provided. A boosting power supply unit includes a boosting circuit having a small number of externally-mounted capacitors, which generates stepped-up and stepped-down boosted voltages through charging and pumping under two-phase control, so that the simultaneous output of the stepped-up voltage and the stepped-down voltage, the output of only the stepped-up voltage, the output of only the stepped-down voltage, and the cut-off of the output of the stepped-up voltage and the stepped-down voltage can be controlled on the basis of the phase control signal generated from the enable signals of which the logic states are changed in accordance with an amount of load.

Abstract: A DC—DC converter is provided for converting an input voltage to a first output voltage. The input voltage is input to a first selecting switch, controlled by a first signal, and a second selecting switch. A first capacitor has one end, input by the first signal, and the other end, electrically coupled to the first selecting switch and outputs a first control voltage to control the second selecting switch. A second capacitor has one end, input by a second signal, and the other end, electrically coupled to the second selecting switch and outputs a first storage voltage. The first select switch outputs the first storage voltage as the first output voltage according to the first control voltage. The first or the second signal comes to a first and a second voltage levels by turns and they come to the first or the second level at a different time point.

Abstract: A voltage generator with reduced noise features a detector, a controller, a sub-booster, a main booster and a voltage adder. The detector receives an output voltage, a first reference voltage and a second reference voltage lower than the first reference voltage, and then outputs a first sensing signal and a second sensing signal. The controller receives the first sensing signal and the second sensing signal and an action signal to output a first control signal and a second control signal. The sub-booster boosts a voltage in response of the first control signal. The main booster boosts a voltage in response to the second control signal. The voltage adder adds output signals from the sub-booster and main booster, to provide the output voltage.

Abstract: In a charge pump circuit including a first charging switching element connected between an input voltage receiving terminal (IVRT) and a first terminal of a step-up capacitor, a second charging switching element connected between a second terminal of the step-up capacitor and a power supply terminal, a first discharging switching element connected between the IVRT and the second terminal of the step-up capacitor, and a second discharging switching element (DSE2) connected between the first terminal of the step-up capacitor and an output terminal, a first switch circuit is connected between the IVRT and a back gate of the first charging switching element and between the first terminal of the step-up capacitor and the back gate of the first charging switching element. A second switch circuit is connected between the first terminal of the step-up capacitor and back gate of DSE2 and between the output terminal and back gate of DSE2.

Abstract: A power system used for transferring power between a plurality of power sources is provided. A power system according to the present invention is comprised of a plurality of power sources, wherein each source includes a pair of terminals. The power system is further comprised of a power converter, including a pair of switches for each one of the plurality of power sources. Each of these switches are connected to the respective pairs of terminals for each source. Each switch further includes an associated diode, and each switch pair includes a common node. The power converter further includes a plurality of inductors numbering one less than the number of power sources, wherein each inductor is connected across two of the common nodes. The power converter further includes a control unit configured to actuate the switches in accordance with, and to carry out, one of a plurality of modes of operation.

Abstract: According to the charge pump circuit, a constant current charging and discharging circuit using follower circuits is interposed at current paths in charging and discharging a capacitor for stepping up. Transistors of the follower circuits are alternately made ON in accordance with a clock signal inputted from a signal input portion for switching to connect the capacitor for stepping up and restricting a current in cooperation with resistors or the like.

Abstract: A charge pump comprising a charge pump core including output switches. The charge pump core, in response to a drive signal, to generate a charge pump output. A limit swing generator, in response to an input signal, to generate the drive signal to control the charge pump core. The drive signal having voltage levels including a high level and a low level. The limit swing generator including at least one voltage generator to control the voltage levels of the drive signal such that the drive signal tracks a process variable of the output switches. The at least one voltage generator including at least one diode or diode connected device.

Abstract: Disclosed are a power supply circuit which can cope with a multipotential level design and is suitable for generating potentials for driving a liquid crystal, and a liquid crystal device and an electronic instrument which use the power supply circuit. A first step-up circuit in the power supply circuit generates a first stepped-up potential level obtained by stepping up a power-supply level with a ground level taken as a reference. A regulator circuit generates a center potential obtained by regulating the first stepped-up potential level by referring to a reference potential level with the ground level taken as a reference. A second step-up circuit generates a second stepped-up potential level obtained by stepping up the center potential with the ground level taken as a reference.

Abstract: A charge pump circuit in which at least one of the switching elements takes the form of a LVTSCR. The switching on and off of the LVTSCRs may be achieved by making use of a pulsed input and relying on the triggering and holding voltages of the LVTSCRs to switch on and off.

Abstract: A charge pump circuit is provided for generating a voltage (1+1/n) times as high as a supply voltage. The charge pump circuit eliminates the need for diodes for preventing a current from flowing back from a high potential side of capacitors to prevent a reduction in the voltage due to a forward voltage, and reduces a reactive current and latch-up when the charge pump circuit is integrated into a single IC chip. The charge pump circuit includes a fourth switching element having a substrate gate connected to a drain for preventing a current from flowing back to an input terminal from a high potential side of fly back capacitors connected in series, and a second switching element having a substrate gate connected to a drain for preventing a current from flowing back from a high potential side of a catch-up capacitor to the fly back capacitors connected in series.

Abstract: Each boosting cell includes: a first n-transistor having a diode connection; a second n-transistor whose gate and drain are connected to a power supply voltage and whose source is connected to the source of the first n-transistor; and a boosting capacitor provided between the drain of the first n-transistor and a boosting clock input terminal to which a clock signal is input. The boosting capacitor is connected to n auxiliary boosting capacitors in parallel via connection switching circuits controlled with boosting ability switching signals as control signals input from the outside.

Abstract: A high voltage generator (GHT) incorporated in an integrated circuit (IC) and comprising a charge pump (1) whose input voltage is the supply voltage (VDD) of the integrated circuit (IC) and which is clocked by direct clock signals (?) and complemented clock signals ({overscore (?)}), characterized in that it comprises means (5) for re-injecting a fraction (VIN) of the voltage from said charge pump (VHV) into the input (6) to which said supply voltage (VDD) is applied.

Abstract: A hybrid inductive-capacitive charge pump provided with a driving stage that comprises a step-up converter and a buffer capacitor, and a cascade of charge pump stages; the first stage of the stage cascade is connected to a power supply and the last stage of the stage cascade is connected to an output of the charge pump circuit; the charge pump circuit comprises elements for activating alternately the charge pump stages, transferring charge from one stage of the cascade to the next stage of the cascade, each stage of the cascade of charge pumping stages comprising a pass transistor and a capacitor.