Abstract: A read method for reading data from a ROM device is provided, which can be operated with a higher voltage to address the memory cells in the ROM device. The ROM device are formed with word and bit lines formed from metallization layers having a very low resistance so that the data current can be increased for increased performance. This read method is for use on a ROM device of the type including an array of memory cells formed at the intersections between a plurality of word lines and a plurality of bit lines. Of these memory cells, a first selected group are set to a permanently-ON state due to the forming of a contact window connecting the associated word line to the associated bit line, and a second selected group of the memory cells are set to a permanently-OFF state due to the forming of no contact window therein.

Abstract: A cross-coupled sense amplifier includes a voltage-compensating balancing resistor serially connected between the drain of one of the P-channel transistors in the sense amplifier and the corresponding sensing/bit line node. The value of the balancing resistor is optimized so that the voltage imbalance between the P-channel transistor is minimized and sense amplifier sensitivity is maximized. A balancing resistor can also be placed in the N-channel transistors in the sense amplifier if desired. The balancing resistor in a typical application is about 100 to 200 ohms and fabricated from polysilicon.

Abstract: The present invention relates to circuitry and a related method to reliably write data to an array of programmable resistance elements by selectively applying pulses of a sufficient level to impart either a first (high) or second (low) resistance state to selected programmable resistance elements to store either a binary "1" or "0", respectively. Data is then read from the array by supplying currents though the selected programmable resistance element and a fixed resistive element. A comparison of the resulting voltages on nodes coupled to these resistive elements will indicate whether the resistance value of the programmable resistance element is at a high or low state, i.e., a binary "1" or "0". Further, a shunt circuit is coupled to the selected column lines of the array to protect the programmable resistance elements from excessive spurious or noise currents, which can erroneously program the programmable resistance elements.

Abstract: A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V.sub.CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry.

Abstract: A read-only memory cell capable of being programmed by the application of radiant energy. The memory cell includes a trimmable resistor, a diode and a latch. In one embodiment, the cathode of the diode is in electrical communication with a first terminal of the resistor and the anode of the diode is in electrical communication with the second terminal of the resistor. The latch has an input terminal in electrical communication with the second terminal of the resistor and an output terminal. The latch is in a first state when the trimmable resistor is untrimmed and is in a second state when the trimmable resistor is trimmed. In one embodiment, the trimmable resistor is trimmable by laser energy. The invention also relates to a method of storing data in a memory cell.

Abstract: A variable resistance material-based memory cell is disclosed for use in an electronic memory. The memory cell includes a MOS diode for delivering large amounts of current to the variable resistance material, as needed during programming of the memory cell. In one embodiment, a buried contact under the gate is used as the drain of the device. The buried contact allows formation of a very short channel, causing a "snapback" phenomenon in the MOS diode and thereby greatly increasing the amount of current flow across the device. This buried contact construction has the additional advantage of reducing the area needed for the memory cell. Additionally, the processing is simple and may be performed using the same techniques normally used during the fabrication of electronic memories.

Abstract: To read out a data bit stored in a memory cell including a programmable resistor memory element, a first voltage is developed on a first sense node due to initiation of current flow through the memory element and a second voltage is developed on a second sense node due to current flow through a reference resistor. The first and second voltages are separately detected to generate a trip signal in response to a leading edge of either of the first and second voltages achieving a threshold level. A flip-flop circuit is conditioned by the trip signal to produce opposite logic signal voltages on the first and second sense nodes indicative of the binary value of the stored data bit.

Abstract: A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented.

Abstract: In an SRAM cell including two cross-coupled inverters each having a first resistance element and a drive MOS transistor, a second resistance element is connected between the first and the drive MOS transistor. A gate electrode of the drive MOS transistor of one of the inverters is connected between the first and second resistance elements of the other.

Abstract: A programmable metallization cell ("PMC") comprises a fast ion conductor such as a chalcogenide-metal ion and a plurality of electrodes (e.g., an anode and a cathode) disposed at the surface of the fast ion conductor and spaced a set distance apart from each other. Preferably, the fast ion conductor comprises a chalcogenide with Group IB or Group IIB metals, the anode comprises silver, and the cathode comprises aluminum or other conductor. When a voltage is applied to the anode and the cathode, a non-volatile metal dendrite grows from the cathode along the surface of the fast ion conductor towards the anode. The growth rate of the dendrite is a function of the applied voltage and time. The growth of the dendrite may be stopped by removing the voltage and the dendrite may be retracted by reversing the voltage polarity at the anode and cathode. Changes in the length of the dendrite affect the resistance and capacitance of the PMC.

Abstract: In a memory system, a first write address is initially loaded into a first latch and transferred to a second latch. A second write address is then loaded into the first address latch. The two addresses are then compared and, if they differ, data associated with the first address is stored in a memory array. However, if the addresses are the same, it is assumed that the user intended to discard the first data associated with that address and this data is discarded rather than being stored in the array. After the comparison, the second address overwrites the first address in the second latch. A third write address is then loaded in the first latch. A comparison is made again, and data associated with the second address is stored in the array only if the second and third addresses are different, otherwise the original data associated with the second address is discarded. This process is repeated for each write address sent to the memory system.

Abstract: A single pull-up circuit is shared between a redundant row antifuse cell, and a redundant column antifuse cell. Additionally, a single selection circuit is shared between the two antifuse cells. A row selection signal supplied thereto selects the antifuse cell for the redundant row, while a column selection signal selects the antifuse cell for the redundant column. A small channel length transistor is employed within the latch circuit. As a result, the latch can quickly pull up a value when the antifuse cell is not blown, and quickly latch that value within the latch since an RC time constant of the latch is decreased. A pulsed pull-up signal having a very short duration is employed to enable the latch. Since the pulsed pull-up signal has a short duration, a high voltage supply V.sub.CC is provided through the latch and a blown antifuse cell to ground for only a short duration, thereby minimizing the possibility of such a low resistance current path from damaging the circuitry.

Abstract: The present invention provides a fixed resistance sense-routed high density parallel ROM device for maintaining the resistance of a buried N+ region on a sense route constant. When data is read from a ROM cell matrix, the selection of different ROM cell transistors does not change the resistance of the buried N+ region on the sense route and thus enables a simplified design of a sense amplifier. The inactive select gate or transfer gate that is activated by the select line can be isolated by ion implantation for forming a buried P+ isolation and thus avoiding the narrowing or the cutting-off of the width of the active transfer gate or select gate due to ion diffusion.

Abstract: A memory element has a sandwich structure in which rings of ferromagnetic material are spaced apart by a layer of a non-magnetic conductor (which is also typically a ring). These ferromagnetic rings will have differing magnetic hardness. At least one ring will be magnetically hard or antiferromagnetically-pinned. At least one other ring will be magnetically softer than the hard or antiferromagnetically-pinned ring. The non-magnetic conductor is at least thick enough to prevent essentially all exchange coupling between the ferromagnetic rings. Conducting leads provide current to pass through the ferromagnetic rings, perpendicular to magnetic moments in the ferromagnetic rings.

Abstract: The resistance of a resistive memory element, e.g. a synaptic element is programmed, e.g. adjusted to a target value, by pulses of a constant height and variable width. One polarity gives an increase in resistance; the other polarity gives a decrease. A short pulse applied after a longer pulse appears to have no effect. After each polarity change short pulses can again be used to make small adjustments. In a preferred embodiment longer and longer pulses are used until the resistance overshoots the target value. After overshooting the polarity is reversed and a second series of pulses is used to obtain a closer approach to the target. The resistive element comprises a resistive layer located between two electrodes, e.g. a matrix of amorphous silicon doped with boron containing V. One electrode is Cr and the other is V.

Abstract: The present invention comprises a novel memory circuit wherein a plurality of memory cells have passive impedance values representative of the information stored therein. In the circuit, a signal source having a plurality of outputs is operable to provide a sequence of read signals, one signal per output. Each of the plurality of outputs is connected to one of a plurality of memory cells. Each memory cell comprises an impedance element, its impedance value representative of the data value stored therein. All of the memory cells are thereafter connected to a sum line and a read out circuit. When the signal source provides one of the sequence signals to one of the memory cell impedance elements, it affects the signal on the sum line in a manner that is related to the impedance value of the memory cell. By applying each signal in the sequence to a different impedance element, the voltage on the sum line is directly affected by each of the impedance elements in sequence.

Abstract: A programmable storage element for redundancy-programing includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the first resistors in parallel in response to a plurality of second control signals to permit programing of the first resistors, and a sensing circuit for determining whether or not the first resistors have been programmed. The state of the first resistors is determined by comparing a first voltage drop across the first resistors with a second voltage drop across a second resistor. Each of the first resistors is an unsilicided polysilicon conductor which has an irreversible resistance decrease when a predetermined threshold current is applied for a minimum period of time.

Abstract: This disclosure relates to an electrically alterable memory device which can be switched from a high resistance state to a low resistance state. The device increases the concentration of electrically active impurities at correspondent electrode to which respective impurities would migrate during a large number of set-reset cycles. This lessens the decline in the threshold voltage caused by the electromigration of those impurities. The device includes a layered structure in which a layer rich in electrically active impurities is placed between memory material layer and its respective electrode and another layer. A fitted thin layer of dielectric is placed between a memory material layer and the other electrode. The memory layer includes an interface of chalcogenide films. A tellurium layer with a concentration of electrically active impurity 2.5%-4.

Abstract: A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memory cell; a first switch connected between the bit line and a power source; a second switch connected between the power source and the second electrode of the capacitor; and a third switch connected between the second electrode of the capacitor and a ground. A specific memory cell is selected out of the memory cells, and a superposed supply voltage is applied through the capacitor to the anti-fuse of the specific memory by turning on and/or off the first through third switches, so that a storage of information in the memory cell can be performed.

Abstract: An improved memory device based on a non-volatile variable resistance element is disclosed. The resistive element is based on a semiconductor having a resistivity which is determined by the state of polarization of a ferro-electric layer. The semiconductor forms one plate of a parallel plate capacitor having a dielectric comprising the ferro-electric layer. The state of the memory device is determined by measuring the resistivity of the semiconductor layer between two contacts on the semiconductor layer. The state of polarization of the ferro-electric layer is altered by applying a voltage between one of these contacts and the other plate of the capacitor.

Abstract: A Read-Only Memory is comprised of a plurality of memory cells. An antifuse film is disposed between and in contact with an underlying heavily N-doped word line layer and an overlying metallic address line layer. The word line is disposed on an insulating semiconductor substrate and is in contact with a surrounding oxide layer. The programmable material is irreversibly configured between the two resistivity states by application of a threshold voltage. The threshold voltage alters the electrical state of the programmable material only in the proximity of that portion of the programmable material to which the threshold voltage has been applied. The resistivity of the low resistivity state is selectively decreased by implanting nonactivated conductive dopants into film. These dopants are characterized by having a nonactivated state where the conduction of carriers in the film is not enhanced, and an activated state where the conduction of carriers in the film is enhanced.

Abstract: A voltage-programmable device in which the programming voltage V.sub.p and the "off" resistance R.sub.i are separately controlled. The device includes a body of semiconductor material having a doped region therein, and an amorphized layer in the doped region and abutting a surface, and a surface layer in the amorphized layer with the surface layer having a resistivity higher than the resistivity of the amorphized layer prior ot programming of the device. The surface layer has a miniscule thickness (on the order of 50-150 Angstroms) and does not affect the programming of the device. Moreover, the final resistance of the programmed device is not significantly affected by the presence of the first layer. The amorphized layer is formed by ion implantation, and the or by oxygen plasma treatment.

Abstract: An electrically programmable element is fabricated in a P-N junction isolated region of a semiconductor body by first extending the depth of the region in the body by introducing dopants through the region into the body by ion implantation or by diffusion and drive-in, and thereafter forming an amorphotized layer in the first region overlying the extended portion. The increased depth of the first region provided by the second region prevents damage to the P-N junction between the semiconductor body and the first region during formation of the amorphotized layer.

Abstract: A multi-layered, thin-film, digital memory having associative recall. There is a first memory matrix and a second memory matrix.

Abstract: A read/write memory cell is disclosed in which multiple ROM data states can be stored. Independent sensing of the resistance values of each of two resistors accounts for the storage of multiple ROM data states. The resistors are encompassed in a pair of cross-coupled resistive gate devices forming branch circuits, thereby allowing each branch circuit to control the conduction of current in the other branch circuit. This allows for read/write data storage in flip-flop-like fashion. In addition, since resistive gate devices are used, the ROM data may be programmed during the later stages of manufacturing.

Abstract: There is disclosed a thin film photoprogrammable memory array with a substantially increased resistance associated with each cell of the array. First and second sets of orthogonally oriented address lines are formed on a substrate with the first set of address lines crossing the second set of address lines at insulated cross-overs. A plurality of amorphous silicon diodes are deposited on the members of the first set of address lines adjacent the insulated cross over points. Settable memory material, an optically programmable chalcogenide, is deposited in electrical contact with each of the amorphous silicon diodes and in electrical contact with a member of the second set of address lines adjacent the cross-over region. When the settable memory material has been set to its high conductivity state, the electrical resistance between the amorphous silicon diode and the adjacent member of the second set of address lines is proportional to an effective electrical length measured along the settable storage member.

Abstract: A remote control device for operating vehicle locks having a transmitter for transmitting a remote control signal. The transmitter converts keyword information into pulses of corresponding pulse widths and then pulse modulates these converted pulses prior to transmission as a remote control signal. A receiver is provided for demodulating and decoding the signal and comparing it to a preset code. If the signal corresponds to the preset code an execution signal is generated to produce the locking and locking function.

Abstract: A programmable read only memory (PROM) includes voltage programmable structures which are readily fabricated to provide predictable and selectable programming voltages. The resistor structure includes a body of semiconductor material having high electrical conductance and a surface contact region having a crystalline structure characterized by relatively high electrical resistance. The relatively high electrical resistance can be established by amorphotizing the surface region or by forming lattice defects in the crystalline structure such as by ion implantation. In programming the PROM, a sufficient voltage is applied across, or sufficient current is applied through, selected structures whereby the surface regions thereof are heated sufficiently to reduce the relatively high electrical resistance.

Abstract: A resistor personalized memory cell consisting of a resistive gate field effect transistor. One end of the gate electrode is connected to the memory cell access line, the other end to one of its source or drain regions. The source or drain region not connected to the gate electrode is connected to the memory cell bit line. Memory cell personalization is accomplished by selecting the resistance of the resistive gate. Memory cell data is read by detecting the current flow through the cell, the magnitude of the current flow being proportional to the gate resistance.

Abstract: A mechanically programmable read only memory in the form of a card for use with a reading circuit to which the card is applied, an insulating substrate with a multiplicity of resistive coating strips arranged in a pattern on the face of a substrate, a multiplicity of circuit interrupters between corresponding ends of resistive strips and being removable along with any surface media applied thereover; conductor strips laid over the circuit interrupters and intersecting with the resistive strips for electrical connection therewith; additional conductor strips or bus strips applied on the substrate to intersect with the other ends of the resistive strips, all of the conductor strips having ends clustered at one edge of the substrate forming connector contacts for assembly with such reading circuitry; the resistive strips, circuit interrupters, and conductor strips being applied by screen printing technology; the circuit interrupters being formed of scratch off ink or mechanically abradable and removable ink; the

Abstract: An electrically programmable read only memory assembly having cells arranged at the intersections of bit lines (BL1) and word lines (WL1, WL2), wherein each cell is formed of a bipolar transistor provided with a base region (70) and an emitter region (71) covered with a dielectric layer (2) made of an oxide or titanate of a transition metal. The cell in this condition represents a binary 0 information bit. The application of an appropriate voltage of approximately 4 volts to the pads of this cell through its corresponding bit line (BL1) and word line (WL2) causes the dielectric layer to break down and places the bit line in ohmic contact with the emitter, which sets the cell in its second condition representing a binary "1" information bit.

Abstract: In the disclosed memory, address decode means are integrated into a surface of a substrate, for addressing cells in the memory; an insulating layer covers the address decode means and the substrate; an array of spaced-apart memory cell select lines lie on the insulating layer; and outputs from the address decode means respectively couple through the insulating layer to the select lines. Each cell of the memory is comprised of a pair of the select lines and further includes a resistive means between that pair which irreversibly switches from a relatively high resistance state to a relatively low resistance state upon the application of a threshold voltage thereacross, and the resistance states are representative of the information in the cell.

Abstract: A memory is provided having a plurality of addressable memory elements, each one thereof having a first programmable device electrically coupled to a second programmable device, the first programmable device having a normally low resistance characteristic which, when programmed, is changed to a relatively high resistance characteristic, and the second programmable device having a normally high resistance characteristic which, when programmed, is changed to a relatively low resistance characteristic. The first programmable device and second programmable device are serially connected to provide an array of memory elements having a relatively high resistance characteristic in an initial, unprogrammed condition. The memory is first programmed by changing the resistance characteristic of selected ones of the second programmable elements. If it is desired to reprogram the memory, the resistance characteristic of selected ones of the first programmable elements are changed.

Abstract: An electrically programmable memory cell comprises two terminals, a unidirectional and/or controllable semiconductor device having anode and cathode regions and a programmable resistor, said anode and cathode regions of the semiconductor device and the programmable resistor being connected in series between the terminals. The programmable resistor comprises a mixture of finely divided metallic material dispersed in a thermoplastic resin. The programmable resistor is initially substantially nonconductive (having a resistivity, for example, in excess of 1 mega ohms per cubic cm). By forcing a sufficient current through the terminals for a period of time, the resistance of the programmable resistor drops drastically to the extent that it may be considered a conductor (having a resistivity, for example, of less than 100 ohms per cubic cm).

Abstract: A memory device is provided for an integrated injection logic (I.sup.2 L) device in solid state form by a resistor connected at one end to the logic device, and a diode having its cathode connected to the other end of the resistor at a programming junction, and its anode connected to a common point. If the diode conductors are melted or deformed by reverse diode current from the programming junction to the common point, a low impedance path is formed, and the logic portion is provided with a first logic input. If the diode conductors are left unmelted or intact, the logic portion is provided with a second logic input.

Abstract: A memory array wherein each memory cell includes a resistive device which switches from a high to a low resistance state when a potential above its programmable threshold is applied and including a reference cell per word line having a reference switchable resistive device. Using a ramp addressing potential, the array output is disabled by an output disable circuit after a reference resistive device switches which is after the switching of an addressed low threshold resistive device cell and before the switching of an addressed high threshold resistive device cell.