Read Only Systems (i.e., Semipermanent) Patents (Class 365/94)
  • Patent number: 10867996
    Abstract: An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10366779
    Abstract: A method and system are provided for predicting chemical structures. The method includes receiving, at a user interface, intended structural feature values and intended chemical property values, as vectors. The method further includes constructing, by a hardware processor, a prediction model, wherein the prediction model predicts other structural feature values from the intended structural feature values and the intended chemical property values, and automatically configuring, by the hardware processor, at least one chemical structure candidate from the other structural feature vectors.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hsiang H. Hsu, Gakuto Kurata, Koji Masuda, Shigeru Nakagawa, Hajime Nakamura, Seiji Takeda
  • Patent number: 10325909
    Abstract: An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10318188
    Abstract: A memory access control method that can prevent a cell hammer phenomenon includes setting at least a part of all the memory cells a safe memory region, and setting the remaining memory cells to a normal memory region. In the safe memory region, some cells set to an enabled state are accessible for data writing or reading, and the remaining cells set to a disabled state are inaccessible. Based on a safe address mapping algorithm, access to all memory cells in the safe memory region is controlled such that access to the enabled memory cells is allowed and access to the disabled memory cells is prevented. The enabled memory cells in the safe memory region are spaced apart from each other by at least one disabled memory cell in a horizontal and/or vertical direction.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jin Park, Chan-Ik Park, Won-Seok Lee
  • Patent number: 10275711
    Abstract: The present invention relates to methods, systems and apparatus for capturing, integrating, organizing, navigating and querying large-scale data from high-throughput biological and chemical assay platforms. It provides a highly efficient meta-analysis infrastructure for performing research queries across a large number of studies and experiments from different biological and chemical assays, data types and organisms, as well as systems to build and add to such an infrastructure.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 30, 2019
    Assignee: Nextbio
    Inventors: Ilya Kupershmidt, Qiaojuan Jane Su, Francois Andry
  • Patent number: 10224334
    Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
  • Patent number: 10215743
    Abstract: Methods, system and device are provided for detection and quantitative and qualitative analysis of components in a gaseous mixture distinguished by high selectivity and high resolution. The influence of individual gases may be distinguished through detection of changes associated with a sensor's sensitive layer that interacts with the components of the gaseous mixture. Through periodic variations of parameters or conditions of the sensor, the characteristics of the gas components may be derived. For example, the concentration of a gas or multiple gases in a mixture may be determined with a high degree of accuracy. Non-invasive detection of biological off-gases may be implemented. Other uses abound.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: February 26, 2019
    Inventors: Pavel Nosovitskiy, Gennadiy Nosovitskiy
  • Patent number: 10195439
    Abstract: An example of a system for programming a neurostimulator may include a storage device and a pattern generator. The storage device may store a pattern library and one or more neuronal network models. The pattern library may include fields and waveforms of neuromodulation. The one or more neuronal network models may each be configured to allow for evaluating effects of one or more fields in combination with one or more waveforms in treating one or more indications for neuromodulation. The pattern generator may be configured to construct and approximately optimize a spatio-temporal pattern of neurostimulation and/or its building blocks using at least one neuronal network model.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: G. Karl Steinke, Michael A. Moffitt, Hemant Bokil
  • Patent number: 10074442
    Abstract: A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: September 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Susumu Takahashi
  • Patent number: 9982300
    Abstract: Systems, methods, and apparatuses for performing a prenatal diagnosis of a sequence imbalance are provided. A shift (e.g. to a smaller size distribution) can signify an imbalance in certain circumstances. For example, a size distribution of fragments of nucleic acids from an at-risk chromosome can be used to determine a fetal chromosomal aneuploidy. A size ranking of different chromosomes can be used to determine changes of a rank of an at-risk chromosome from an expected ranking. Also, a difference between a statistical size value for one chromosome can be compared to a statistical size value of another chromosome to identify a significant shift in size. A genotype and haplotype of the fetus may also be determined using a size distribution to determine whether a sequence imbalance occurs in a maternal sample relative to a genotypes or haplotype of the mother, thereby providing a genotype or haplotype of the fetus.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: May 29, 2018
    Assignee: The Chinese University of Hong Kong
    Inventors: Yuk Ming Dennis Lo, Kwan Chee Chan, Wai Kwun Rossa Chiu, Wenli Zheng
  • Patent number: 9947397
    Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, crosspoint array decoder includes a number of field effect transistor decoder switches corresponding to specific lines in a crosspoint array and a sense amplifier coupled to at least some of the field effect transistor decoder switches and includes a set of inference field effect transistors matched to the field effect transistor decoder switches to infer a stimulus voltage applied to a memory element in a crosspoint array.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Yoocharn Jeon
  • Patent number: 9893059
    Abstract: An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9824768
    Abstract: An integrated One-Time Programmable (OTP) memory to emulate an Multiple-Time Programmable (MTP) memory with a built-in program count tracking and block address mapping is disclosed. The integrated OTP memory has at least one non-volatile block register and count register to respectively store block sizes and program counts for different block/count configurations. The count register can be programmed before each round of programming occurs to indicate a new block for access. The integrated OTP memory also can generate a block address based on values from the count and block registers. By combining the block address with the lower bits of an input address, a final address can be generated and used to access different blocks (associated with different program counts) in the OTP memory to mimic an MTP memory.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 21, 2017
    Assignee: ATTOPSEMI TECHNOLOGY CO., LTD
    Inventor: Shine C. Chung
  • Patent number: 9767867
    Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: September 19, 2017
    Assignee: Virident Systems, Inc.
    Inventors: Kenneth Alan Okin, George Moussa, Kumar Ganapathy, Vijay Karamcheti, Rajesh Parekh
  • Patent number: 9729334
    Abstract: Provided is an apparatus for generating a digital value that may generate a random digital value, and guarantee time invariance of the generated digital value. The apparatus may include a digital value generator to generate a random digital value using semiconductor process variation, and a digital value freezing unit that may be connected to the digital value generator and fixed to one of a first state and a second state based on the generated digital value, to freeze the digital value.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: August 8, 2017
    Assignee: ICTK CO., LTD
    Inventors: Byong Deok Choi, Dong Kyue Kim, Tae Wook Kim
  • Patent number: 9428807
    Abstract: A method for nucleic acid sequencing includes disposing template polynucleotide strands in defined spaces on a sensor array, at least some of the template polynucleotide strands having a sequencing primer and a polymerase operably bound therewith; exposing the template polynucleotide strands to a series of flows of nucleotide species flowed according to a predetermined ordering; and determining, for each of the series of flows of nucleotide species, how many nucleotide incorporations occurred for that particular flow to determine a predicted sequence of nucleotides corresponding to the template polynucleotide strands, wherein the predetermined ordering (a) is not a series of consecutive repetitions of a 4-flow permutation of four different nucleotide species, (b) is not specifically tailored to a particular combination of a particular template polynucleotide strand to be sequenced and a particular sequencing primer to be used, and (c) comprises a phase-protecting flow ordering.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: August 30, 2016
    Assignee: LIFE TECHNOLOGIES CORPORATION
    Inventors: Earl Hubbell, Jonathan Schultz
  • Patent number: 9384852
    Abstract: A semiconductor device which includes a normal cell, a replica cell, a word line, a first bit line, a bias generation circuit, a second bit line, and a current generation circuit. The normal cell is a one-time programmable (OTP) type memory cell. The replica cell has characteristics equivalent to those of the normal cell. The word line is electrically connected in common to a control terminal of the normal cell and a control terminal of the replica cell. The first bit line is electrically connected to an input-output terminal of the replica cell. The bias generation circuit is electrically connected to the first bit line. The second bit line is electrically connected to an input-output terminal of the normal cell. The current generation circuit is electrically connected to the second bit line. The bias generation circuit and the current generation circuit are controlled through a common control line.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: July 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Kawasumi
  • Patent number: 9343173
    Abstract: A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of bits and to output a result indicating whether or not a value of the count exceeds a predetermined determination threshold value, as a bit determination result signal, and a selection control circuit to select a non-volatile program element to be cut off, based on the bit determination result signal and the address signal. Additional apparatus and methods are described.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Susumu Takahashi
  • Patent number: 9343176
    Abstract: A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 17, 2016
    Inventor: Shine C. Chung
  • Patent number: 9299392
    Abstract: Semiconductor memory devices include unit cells two-dimensionally arranged along rows and columns in one cell array block. The unit cells are classified into a plurality of cell subgroups, and each of the cell subgroups includes the unit cells constituting a plurality of the rows. Each of the unit cells includes a selection element and a data storage part. A word line is connected to gate electrodes of selection elements of the unit cells constituting each column. Bit lines are connected to data storage parts of the unit cells constituting the rows. A source line, parallel to the bit line, is electrically connected to source terminals of the selection elements of the unit cells in each cell subgroup. The source line is parallel to the bit line. A distance between the source line and the select bit line is equal to a distance between the bit lines adjacent to each other.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: March 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaekyu Lee, Changkyu Kim
  • Patent number: 9286997
    Abstract: An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: March 15, 2016
    Assignee: Broadcom Corporation
    Inventors: Narayana Rao Vedula, Dechang Sun, Myron Buer
  • Patent number: 9224470
    Abstract: A method includes applying a first voltage setting to a first node and a second node of a selected memory cell for a first predetermined period of time in response to a command for programming a first logical state to the selected memory cell. A first stored logical state of the selected memory cell is obtained after the applying the first voltage setting operation. If the first stored logical state differs from the first logical state, a second voltage setting is applied to the first node and the second node of the selected memory cell; and a first retrial is performed. The first retrial includes applying the first voltage setting to the first node and the second node of the selected memory cell for the first predetermined period of time.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: December 29, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chieh Chiu, Chih-Yang Chang, Tassa Yang, Wen-Ting Chu
  • Patent number: 9117750
    Abstract: A method for manufacturing a resistive element of a non-volatile memory includes the following steps. An insulation layer is formed on a conductive region. The insulation layer is etched to form a via in the insulation layer, wherein a bottom of the via is contacted with a top surface of the conductive region. A dielectric layer is formed on an inner wall and the bottom of the via. A barrier layer is formed on the dielectric layer. A metal layer is filled into the via. The dielectric layer and the barrier layer are reacted with each other to form a transition layer.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: August 25, 2015
    Inventor: Chrong-Jung Lin
  • Patent number: 9058855
    Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 16, 2015
    Assignee: III Holdings 2, LLC
    Inventor: Michael C. Stephens, Jr.
  • Publication number: 20150078060
    Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. The low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. In some applications where only the integrated circuit can read the data, a second control signal internal to the integrated circuit generates start, stop, device ID, read pattern, starting address, and actual read cycles, while the first control signal external to the integrated circuit can do the same for the program or erase path.
    Type: Application
    Filed: November 25, 2014
    Publication date: March 19, 2015
    Inventor: Shine C. Chung
  • Publication number: 20150078059
    Abstract: The present document relates to the programming of programmable memory devices, e.g. one-time programmable (OTP) memory device. In particular, the present document relates to efficient methods and systems for generating the supply voltage for programming a programmable memory device. A controller configured to control the programming of a data word into a programmable memory device is described. The controller is configured to set one or more digital control signals for programming the data word into the programmable memory device. Furthermore, the controller is configured to, subsequent to setting the one or more digital control signals, increasing a device supply voltage for the programmable memory device from a default operation level to a programming level.
    Type: Application
    Filed: April 11, 2014
    Publication date: March 19, 2015
    Applicant: Dialog Semiconductor GmbH
    Inventor: Horst Knoedgen
  • Patent number: 8976564
    Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Il Lim, Cheol Kim, Sang-Ho Shin
  • Patent number: 8976616
    Abstract: Methods and systems that extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements are provided. Accordingly, significantly reduced area requirements and control circuitry complexity of memory elements is enabled. The provided methods and systems can be used in non-volatile memory storage, and are suitable for use in system on chip (SoC) products.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: Broadcom Corporation
    Inventor: Myron Buer
  • Patent number: 8958232
    Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jonathan Tsung-Yung Chang, Cheng Hung Lee, Chung-Cheng Chou, Hung-Jen Liao, Bin-Hau Lo
  • Patent number: 8953357
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the bit lines, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the bit lines of the bit line group and spaces between the bit lines.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiaki Dozaka
  • Patent number: 8942023
    Abstract: A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2 or larger). At least one of the ReRAM elements is an effective element where the cell data is recorded. In reading the cell data, the control circuit at least selects the effective element and reads data recorded thereon as the cell data.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Tsuda, Yoshitaka Kubota, Kenichi Hidaka, Hiromichi Takaoka
  • Patent number: 8942051
    Abstract: This description relates to a system for storing repair data of a random access memory (RAM) array in a one-time programming memory (OTPM). The system includes the RAM array, wherein the RAM array includes a main memory, redundant rows and columns, and a first repair register memory. The system further includes a built-in self-test-and-repair (BISTR) module having a second repair register memory, wherein the BISTR module is used to test and repair the RAM array. The system further includes the one-time programming memory (OTPM) for storing repair data from more than one test and repair stages for the RAM array, wherein the repair data from different test and repair stages are stored in a same data segment.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Saman Adham, Chao-Jung Hung
  • Publication number: 20150009743
    Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one dies can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each dies in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventor: Shine C. Chung
  • Patent number: 8923030
    Abstract: In one embodiment described herein, on-die programmable fuses may be used. On-die programmable fuses may be programmed by entities other than the chip manufacturer after the fuse array chip has been manufactured and shipped out. However, other non-volatile memories may also be used.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Jason G. Sandri, Ian S. Walker, Monib Ahmed
  • Patent number: 8923029
    Abstract: The field programmable read-only memory device includes a memory cell having a switching element for storing bit information. The switching element provides a switchable electrical connection between a word line and a bit line and includes a static body and a movable connecting element. The switchable electrical connection is non-volatile.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: December 30, 2014
    Assignee: Thomson Licensing
    Inventors: Meinolf Blawat, Holger Kropp
  • Patent number: 8917533
    Abstract: Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: December 23, 2014
    Inventor: Shine C. Chung
  • Patent number: 8897054
    Abstract: A ROM memory circuit is disclosed having at least one electrical line, at least one keeper circuit electrically connected to the at least one electrical line, the keeper circuit including a first transistor, a terminal of the first transistor is driven by a dedicated control signal, wherein the dedicated control signal is configured to keep the voltage of the at least one electrical line at a first voltage.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Vianney Choserot, Marie Lafont Marazel
  • Patent number: 8879346
    Abstract: Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Intel Corporation
    Inventors: Timothy Y. Kam, Jay D. Schwartz, Seongwoo Kim, Stephen H. Gunther
  • Patent number: 8879302
    Abstract: Various embodiments may generally be directed to a variable resistance data storage device and a method of managing the device. A data storage device may have at least a controller configured to re-characterize at least one variable resistance memory cell in response to an identified variance from a predetermined resistance threshold.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 4, 2014
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Ryan James Goss, Jon D. Trantham
  • Publication number: 20140321190
    Abstract: A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6 F2.
    Type: Application
    Filed: May 20, 2014
    Publication date: October 30, 2014
    Inventor: Daniel R. Shepard
  • Patent number: 8873269
    Abstract: A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rahul K. Nadkarni, Daniel R. Baratta, Konark Patel, Hoan H. Nguyen
  • Patent number: 8861248
    Abstract: Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 14, 2014
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Eran Rotem
  • Patent number: 8855939
    Abstract: In one embodiment, a method for analyzing data generated by probe arrays is described that comprises receiving user selections of two or more data files and an identification of one or more subsets of intensity values acquired from a biological probe array. The method includes iteratively opening each data file, identifying the selected subset of intensity values associated with each open data file, determining parameters for processing, storing the parameters and the identified intensity values, and closing the open data file prior to the subsequent iteration. The method then includes processing the stored intensity values using the parameters to identify one or more biological events.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: October 7, 2014
    Assignee: Affymetrix, Inc.
    Inventors: Alan J. Williams, Charles W. Sugnet, James H. Gorrell
  • Patent number: 8827917
    Abstract: According to embodiments, a method and system for artifact detection in signals is disclosed. The artifacts may take the form of movement artifacts in physiological (e.g., pulse oximetry) signals. Artifacts in the wavelet space of the physiological signal may be removed, replaced, ignored, filtered, or otherwise modified by determining the energy within a predefined moving area of the wavelet scalogram, comparing the determined energy within the predefined moving area of the wavelet scalogram to a threshold value, and masking at least one area of artifact in the wavelet scalogram based, at least in part, on the comparison. From the enhanced signal, physiological parameters, for example, respiration, respiratory effort, pulse, and oxygen saturation, may be more reliably and accurately derived or computed.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: September 9, 2014
    Assignee: Nelleor Puritan Bennett Ireland
    Inventors: James Watson, Paul Stanley Addison
  • Patent number: 8824185
    Abstract: A NOR-type ROM with hierarchical-BL structure, dynamic segmentation shielding, and source programming includes a plurality of bitcells forming a plurality of cell arrays, a plurality of WLs, a plurality of local bit lines LBLs electrically connected with the drains of the bitcells, a plurality of odd/even selection circuits electrically connected the LBLs that the bitcells in one of the cell array correspond to, a plurality of GBLs electrically connected the odd/even selection circuits that the bitcells in columns correspond to, and a plurality of odd-even precharge circuits electrically connected with the GBLs. The source of each bitcell is selectively grounded or floating according to the code-pattern.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 2, 2014
    Assignee: National Chung Cheng University
    Inventors: Jinn-Shyan Wang, Chao-Hsiang Wang
  • Publication number: 20140233295
    Abstract: A ROM memory circuit is disclosed having at least one electrical line, at least one keeper circuit electrically connected to the at least one electrical line, the keeper circuit including a first transistor, a terminal of the first transistor is driven by a dedicated control signal, wherein the dedicated control signal is configured to keep the voltage of the at least one electrical line at a first voltage.
    Type: Application
    Filed: February 18, 2013
    Publication date: August 21, 2014
    Applicant: Intel Mobile Communications GmbH
    Inventors: Vianney Choserot, Marie Lafont Marazel
  • Patent number: 8812248
    Abstract: Methods and systems for the analysis of genotyping data are presented. According to various embodiments of methods and systems, an angle configuration search may be performed. In various embodiments, an exhaustive search over the entirety of an angle configuration space may be performed to provide a fit to a plurality of angles determined for a plurality of points in a data set generated from a plurality of biological samples. For various embodiments, the angle configuration space may be defined to ensure that a global fit may be determined. According to various methods and systems, a data base of possible angle configurations may be searched, in which each angle configuration may include three angles. According to various methods and systems, a data base of possible angle configurations may include for each angle configuration a probability that the angle configuration may occur.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: August 19, 2014
    Assignee: Life Technologies Corporation
    Inventor: Marcin Sikora
  • Publication number: 20140211567
    Abstract: A low-pin-count non-volatile memory (NVM) embedded an integrated circuit can be accessed without any additional pins. The NVM has one or more memory cells and at least one of the NVM cells can have at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector can be coupled to a second supply voltage line and has a selecting signal. The integrated circuit can include at least one test mode detection circuit to activate a test mode upon detecting an abnormal (or out of normal) operation condition(s). Once a test mode is activated, at least one I/O or supply voltage of the integrated circuit can be used as the I/O or supply voltage of the NVM to select at least one NVM cell for read, program into nonvolatile, or volatile state. At least one NVM cell can be read during ramping of at least one supply voltage line.
    Type: Application
    Filed: March 31, 2014
    Publication date: July 31, 2014
    Inventor: Shine C. Chung
  • Publication number: 20140198555
    Abstract: Methods and apparatus for the encoding of an input sequence of digit data into a sequence of storage cells of a ROM device are disclosed. The input sequence is divided into a first kind of groups and a second kind of groups. A first kind of group comprises a plurality of consecutive first digits, two first kind of groups are separated by a second kind of group, the second kind of group comprises consecutive digits without any consecutive first digits, and the second kind of group has a starting digit which is the second digit. A starting storage cell is programmed to the active state to store the starting digit of the second kind of group. The rest digits of the second kind of group are programmed one digit at a time, based on a shared terminal which has been programmed for the proceeding storage cell.
    Type: Application
    Filed: June 14, 2013
    Publication date: July 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: He-Zhou Wan, Shao-Yu Chou
  • Patent number: 8781754
    Abstract: Disclosed are a method of and system for detecting a consensus motif in a data sequence. The method comprises the steps of obtaining the data sequence, identifying potential signal (PS) segments of interest in the data sequence, and carrying out comparison and alignment processes amongst the PS segments to extract the consensus motif. Preferably, an unsupervised motif discovery process is used to identify the PS segments. More specifically, this may be done by extracting all common motifs across the sequence using the unsupervised motif discovery process; and for each of at least selected positions in the sequence, computing the weighted sum of the common motifs that cover said position. The PS segments that cover the positions where said number is above a given threshold may then be identified as the PS segments.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matteo Comin, Laxmi P. Parida