Abstract: The embodiments of the present disclosure propose a booster circuit and a method for driving the same, a shutdown circuit and a method for driving the same, and a display apparatus.

Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

Abstract: A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a first impurity region in the active region, an anti-fuse gate electrode on the semiconductor substrate and extending across the first impurity region, an anti-fuse gate dielectric layer between the anti-fuse gate electrode and the first impurity region, a selection gate electrode on the semiconductor substrate and extending across the active region, a selection gate dielectric layer between the selection gate electrode and the active region, and a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode. The first and second impurity regions have impurities of a second conductivity type. The first impurity region has an impurity concentration less than the impurity concentration of the second impurity region.

Abstract: The invention provides a capacitive sensor circuit in which a capacitance to be sensed is selectively coupled into a ring oscillator circuit. The ring oscillator frequency is measured with the capacitance coupled and not coupled, and a capacitance is derived from the change in ring oscillator frequency.

Abstract: An novel impedance sensor is provided having a plurality of substantially parallel drive lines configured to transmit a signal into a surface of a proximally located object, and also a plurality of substantially parallel pickup lines oriented substantially perpendicular to the drive lines and separated from the pickup lines by a dielectric to form intrinsic electrode pairs that are impedance sensitive at each of the drive and pickup crossover locations.

Abstract: The memory cell of a memory device comprises a MOS capacitor having a n-type gate and a n-type well, a first switch to temporarily apply a breakthrough voltage across the n-type gate and the n-type well to generate a permanent conductive breakthrough structure between the n-type gate and the n-type well.

Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).

Abstract: An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead (706) is connected to the switch of each memory cell in a first column. A bit line (718) is connected to the current path of each access transistor in the first column. A read select lead (721) is connected to a control terminal of each access transistor in the first row. A first row select lead (700) is connected to a control terminal of the switch in each memory cell in a first row.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.

Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

Abstract: Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal.

Abstract: An anti-fuse circuit and an integrated circuit (IC) including the same are disclosed, which are applied to a technology for use in all kinds of semiconductor devices or system ICs, each of which includes an anti-fuse circuit using the breakdown phenomenon of a gate oxide, so as to prevent the occurrence of an anti-breakdown phenomenon. The anti-fuse circuit includes an anti-fuse, a breakdown of which occurs by a program voltage, configured to be electrically short-circuited, a read controller configured to be controlled by a read voltage received through the anti-fuse so as to output a short-circuiting status of the anti-fuse, and a switching unit configured to form a path that prevents a current flowing through the anti-fuse from being applied to the read controller during a program operation and prevents a current from flowing in the anti-fuse during a read operation.

Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.

Abstract: The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.

Abstract: An anti-fuse circuit and an integrated circuit (IC) including the same are disclosed, which are applied to a technology for use in all kinds of semiconductor devices or system ICs, each of which includes an anti-fuse circuit using the breakdown phenomenon of a gate oxide, so as to prevent the occurrence of an anti-breakdown phenomenon. The anti-fuse circuit includes an anti-fuse, a breakdown of which occurs by a program voltage, configured to be electrically short-circuited, a read controller configured to be controlled by a read voltage received through the anti-fuse so as to output a short-circuiting status of the anti-fuse, and a switching unit configured to form a path that prevents a current flowing through the anti-fuse from being applied to the read controller during a program operation and prevents a current from flowing in the anti-fuse during a read operation.

Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

Abstract: A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data.

Abstract: An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell.

Abstract: A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write voltage to the output terminal; and a second switching unit connected to the output terminal to transfer a read voltage to the output terminal.

Abstract: A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned silicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.

Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

Abstract: An analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory capacitor (102) connected at a first end to a first port (104), which is connected a reference potential (106). A drain of a first transistor (108) —switch transistor—is connected to a second end of the memory capacitor (102). A source of the first transistor (108) is connected to a second port (110), which is connected to circuitry (112) for providing an input signal for storage in the memory capacitor (102), and a gate of the first transistor (108) is connected to a third port (114), which is connected to a first current sink (116). A source of a second transistor (118) is connected to the source of the first transistor (108) and a drain of the second transistor (118) is connected to the gate of the first transistor (108).

Abstract: An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines.

Abstract: A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device.

Abstract: Since a power source voltage is generated from a communication signal in a wireless chip, there is a risk that a large amount of voltage be generated in the wireless chip to electrically destroy a circuit in the case of supplying a strong communication signal. Therefore, the present invention is made with an aim to provide a wireless chip having resistance to a strong communication signal. A wireless chip of the present invention has an element in which a power source wire and a grounding wire are electrically short-circuited if a power source voltage exceeds a voltage at which an electric circuit is destroyed, i.e., exceeds the specified voltage range. Accordingly, a wireless chip of the present invention has resistance to a strong communication signal.

Abstract: A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate electrode, respectively; a first salicide layer disposed on one of the source/drain regions; a capacitive dielectric layer disposed on the gate electrode and the other of the source/drain regions; a first conductive plug disposed on the first salicide layer; and a second conductive plug disposed on the capacitive dielectric layer. The size of the first conductive plug is different form the size of the second conductive plug.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of said pairs including a first bit line, a second bit line, a memory cell coupled to said first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line.

Abstract: An integrated circuit includes a memory array portion and a support circuitry portion arranged on a semiconductor substrate. An insulative layer is formed on the semiconductor substrate. Data storage capacitors are located in the memory array portion and extending through the insulative layer. Non-data storage capacitors are located in the support circuitry portion and terminating above the insulative layer.

Abstract: A ferroelectric semiconductor storage device includes: a block having a plurality of ferroelectric memory cells connected in series, each of the plurality of ferroelectric memory cells including a ferroelectric capacitor and a transistor connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each of the transistors; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; and a plate line connected to the other end of the block. The number of ferroelectric memory cells connected in each block in the ferroelectric semiconductor storage device is odd.

Abstract: A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two rows and at least two columns. A star-type topology is disposed to be electrically connected to the memory devices. One or more pairs of adjacent ones of the memory devices have a point-symmetric structure.

Abstract: To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage.

Abstract: For realizing high speed one time programmable memory, bit line is multi-divided for reducing capacitance, so that the bit line is quickly charged when reading and multi-stage sense amps are used for connecting divided bit line, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense amp for reading the memory cell, a second dynamic circuit serving as a segment sense amp for reading the local sense amp, and a tri-state inverter serving as an amplify circuit of a global sense amp for reading the segment sense amp. When reading data, a voltage difference in the bit line is converted to a time difference for differentiating high data (programmed) and low data (unprogrammed) by the multi-stage sense amps. And buffered data path is connected to the global sense amp for realizing fast data transfer. Additionally, alternative circuits and memory cell structures are described.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: For realizing high speed one time programmable memory, bit line is multi-divided for reducing capacitance, so that the bit line is quickly charged when reading and multi-stage sense amps are used for connecting divided bit line, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense amp for reading the memory cell, a second dynamic circuit serving as a segment sense amp for reading the local sense amp, and a tri-state inverter serving as an amplify circuit of a global sense amp for reading the segment sense amp. When reading data, a voltage difference in the bit line is converted to a time difference for differentiating high data (programmed) and low data (unprogrammed) by the multi-stage sense amps. And buffered data path is connected to the global sense amp for realizing fast data transfer. Additionally, alternative circuits and memory cell structures are described.

Abstract: The invention provides an ID chip to which data can be written only once in order to maintain high security as a non-contact type ID chip to which signals are inputted wirelessly from an antenna. A non-contact type ID chip includes a nonvolatile FeRAM in the chip. Data representative of whether data is written or not to the FeRAM is written when writing identification data, thereby data cannot be written additionally to the FeRAM of the ID chip once the data has been written.

Abstract: Information stored in a nonvolatile storage device mounted to a semiconductor device is read by inputting an address signal or the like and by using a sense amplifier or the like. At this time, since a prescribed period of time is required, it is necessary to design a semiconductor device taking that delay into consideration. Also, a sense amplifier consumes an enormous amount of current. Further, since the number of reading bits is set, it is also necessary to read other unnecessary information when only 1 bit is to be read. A nonvolatile storage circuit is formed by a memory element that is formed by an electrical element having an electrically conducting or insulating means, a reset element, and a latch element. In the storage element, different information is stored in the latch element depending on whether the electrical element is electrically insulated or conductive, when the wireless chip is reset.

Abstract: A One-Time Programmable (OTP) unit cell and a nonvolatile memory device having the same are disclosed. A unit cell of a nonvolatile memory device includes: an anti-fuse connected between an output terminal and a ground voltage terminal; a first switching unit connected to the output terminal to transfer a write voltage to the output terminal; and a second switching unit connected to the output terminal to transfer a read voltage to the output terminal.

Abstract: A system and method are disclosed for providing EEPROM devices that combine the high endurance features of complex and expensive EEPROM devices and the low manufacturing costs of CMOS compatible EEPROM devices. A memory cell of the invention comprises a control capacitor, an erase capacitor, and a program capacitor, each of which comprises an NMOS transistor. The gates of the three NMOS transistors are connected together to form a floating gate. The drain of the NMOS transistor of the program capacitor is separately connected so that the program capacitor can also serve as a read transistor. A memory cell of the invention can be programmed or erased in an array of memory cells without disturbing the other memory cells in the array.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming apparatus. The invention provides for the programming apparatus to comprise a charge storage device and a switchable charging apparatus. The inventive method for programming memory cells of the CBRAM type is carried out in such a manner that, a given quantity of an electrical charge is stored in a charge storage device, and the stored quantity of electrical charge is transferred to the memory cell to be programmed.

Abstract: An electrostatic capacitance detection device, for detecting electrostatic capacitance that changes in accordance with a distance from a target object to read surface contours of the target object, can sense electrostatic capacitance highly accurately even with using thin-film semiconductor devices. The electrostatic capacitance detection device includes electrostatic capacitance detection elements arranged in M rows and N columns, a power supply line that supplies power to the electrostatic capacitance detection elements, an output line that outputs a signal from the electrostatic capacitance detection elements, M row lines that select the electrostatic capacitance detection elements disposed on a specific row, and N column lines that select the electrostatic capacitance detection elements disposed on a specific column. Further, the electrostatic capacitance detection elements each include a signal detection element, a row selection element, a column selection element, and a signal amplification element.

Abstract: A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.

Abstract: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.

Abstract: The present memory device includes first and second electrodes, an active layer; and a passive layer, the active and passive layers being between the first and second electrodes, with at least one of the active layer and passive layer being a doped a sol-gel.

Abstract: A required value of decoupling capacitance is calculated in advance for every functional cell, a virtual cell which has a functional cell, and a decoupling capacitance placing area required for placing the decoupling capacitance with the calculated value is created, the virtual cell is placed on a chip, and the decoupling capacitance cell is subsequently placed in the decoupling capacitance placing area of the virtual cell. A layout method of an integrated circuit and a computer program, in which a decoupling capacitance with an amount required for preventing malfunction caused by a noise can be surely placed, and there is no possibility that the functional cell will need to be replaced due to a shortage of the decoupling capacitance after placing the functional cell can be realized.

Abstract: A semiconductor device includes a first DRAM section formed on a semiconductor substrate and composed of a plurality of first memory cells and a second DRAM section formed on the semiconductor substrate and composed of a plurality of second memory cells. The operating speed of the first DRAM section is higher than that of the second DRAM section, and the capacitance of each said first memory cell is larger than that of each said second memory cell.