Abstract: Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.

Abstract: According to one embodiment, a system includes a head, where the head includes: an optical signal source configured to emit a first optical signal, and a near-field transducer (NFT) configured to focus the first optical signal on a moving ferroelectric storage medium positioned below the head. The system also includes a detector operatively coupled to the head, where the detector is configured to detect a second optical signal generated in and reflected from the ferroelectric storage medium, and where the second optical signal has twice the optical frequency as the first optical signal.

Abstract: Provided is an oxide electronic device, including: an oxide substrate; an oxide thin film layer formed on the oxide substrate and containing an oxide that is heterogeneous with respect to the oxide substrate; and a ferroelectric layer formed on the oxide thin film layer and controlling electric conductivity of two-dimensional electron gas (2DEG) generated at an interface between the oxide substrate and the oxide thin film layer. Provided also is a method for manufacturing an oxide electronic device, including: depositing, on an oxide substrate, an oxide that is heterogeneous with respect to the oxide substrate to form an oxide thin film layer; and forming a ferroelectric layer on the oxide thin film layer, wherein the ferroelectric layer controls electric conductivity of 2DEG generated at an interface between the oxide substrate and the oxide thin film layer.

Abstract: A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed.

Abstract: Loadless 4 transistor SRAM cell operation can be substantially improved, yielding area saving and more stable operation by use of optical-light load. Parasitic photocurrents in PMOS anodes-substrate junctions act as load currents. Light can be introduced by either ambient light through transparent window on top of the chip or by cheap LED diode attached to chip surface.

Abstract: A semiconductor memory cell includes: a memory element formed by a first field effect transistor having a gate insulating film made of a ferroelectric film; and a select switching element formed by a second field effect transistor having a gate insulating film made of a paraelectric film. The ferroelectric film and the paraelectric film are stacked together with a semiconductor film of a compound semiconductor interposed therebetween. A first gate electrode of the first field effect transistor is formed on a side of the ferroelectric film, and a second gate electrode of the second field effect transistor is formed on a side of the paraelectric film so as to face the first gate electrode. The semiconductor film forms a common channel layer of the first and second field effect transistors.

Abstract: The present invention uses a ferromagnetic thin wire having a domain wall inside, with the magnetic moment at the center thereof being perpendicular to the longitudinal axis of the thin wire. With the domain wall being fixed by a domain wall fixation device (e.g. antiferromagnetic thin wires) so that the domain wall is prevented from moving in the ferromagnetic thin wire, when a direct current is supplied, the magnetic moment rotates in the immobilized domain wall. This rotation of the moment can be detected by a TMR element or the like. This configuration of the ferromagnetic thin wire element can be directly used to create a microwave oscillator or magnetic memory.

Abstract: A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation.

Abstract: Provided are a photonic memory device, a method of storing data using the photonic memory device, and a photonic sensor device. The photonic memory device comprises a signal line through which a photon is input; a ring resonator receiving a photon through an input gap that is adjacent to the signal line and storing the photon; and a detect line outputting the photon stored in the ring resonator through an output gap that is adjacent to the ring resonator, wherein data is read/written and stored/deleted by the input/output of the photon.

Abstract: A ferroelectric semiconductor storage device includes: a block having a plurality of ferroelectric memory cells connected in series, each of the plurality of ferroelectric memory cells including a ferroelectric capacitor and a transistor connected in parallel to both ends of the ferroelectric capacitor; a word line connected to each of the transistors; a selection transistor connected to one end of the block; a bit line connected to the selection transistor; and a plate line connected to the other end of the block. The number of ferroelectric memory cells connected in each block in the ferroelectric semiconductor storage device is odd.

Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. An extraction region is disposed on a first side of the active region and extracts minority carriers from the active region. It also has majority carriers within the extraction region flowing toward the active region in a condition of reverse bias. An exclusion region is disposed on a second side of the active region and has minority carriers within the exclusion region flowing toward the active region. It receives majority carriers from the active region. At least one of the extraction and exclusion region provides a barrier for substantially reducing flow of one of the majority carriers or the minority carriers, whichever is flowing toward the active region, while permitting flow of the other minority carriers or majority carriers flowing out of the active region.

Abstract: A semiconductor device includes a pull-up unit pulling up a voltage of an output node to a first voltage in response to a control signal, a photo sensing unit pulling down a voltage of the output node to a second voltage in response to an incident light, and a CPU, the CPU reset in response to the voltage of the output node produced in response to the incident light.

Abstract: One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed.

Abstract: A ferroelectric memory device includes: a plurality of bit lines; a plurality of memory cells connected to each of the plurality of bit lines, and each storing “0” data with a smaller amount of readout charge or “1” data with a greater amount of readout charge according to a polarization state; a plurality of data lines; a plurality of charge transfer circuits that connect the plurality of bit lines to the plurality of data lines, respectively, based on a potential on each of the bit lines; a capacitor connected to each of the plurality of data lines for storing negative charge; a positive charge canceling circuit that pulls out positive charge corresponding to the amount of “0” data readout charge from each of the plurality of bit lines; and a sense amplifier that judges data read out from the memory cells.

Abstract: A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into corresponding electrical address signals applied to the address decoder and control signals applied to the control logic. A read/write circuit on the substrate is coupled to a data converter formed in the substrate. The data converter is operable to receive and convert optical write data signals into corresponding electrical data signals to be applied to the read/write circuit and to receive and convert electrical read data signals into corresponding optical read data signals.

Abstract: A nonvolatile semiconductor memory device obtained by combining a nonvolatile memory device with a SRAM is provided to improve operating speed and reliability. The nonvolatile semiconductor memory device includes a plurality of data registers. Preferably, each of the plurality of data registers includes a pull-up driving unit adapted and configured to pull up a storage node, a pull-down driving unit adapted and configured to pull down the storage node, a data input/output unit adapted and configured to selectively input and output data between a bit line and the storage node depending on a voltage applied to a word line, and a data storing unit adapted and configured to store data of the storage node depending on a voltage applied to a top word line and a bottom word line or to output the stored data to the storage node.

Abstract: A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into corresponding electrical address signals applied to the address decoder and control signals applied to the control logic. A read/write circuit on the substrate is coupled to a data converter formed in the substrate. The data converter is operable to receive and convert optical write data signals into corresponding electrical data signals to be applied to the read/write circuit and to receive and convert electrical read data signals into corresponding optical read data signals.

Abstract: A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into corresponding electrical address signals applied to the address decoder and control signals applied to the control logic. A read/write circuit on the substrate is coupled to a data converter formed in the substrate. The data converter is operable to receive and convert optical write data signals into corresponding electrical data signals to be applied to the read/write circuit and to receive and convert electrical read data signals into corresponding optical read data signals.

Abstract: At switching normal operation mode to low power mode, a first switch disconnects a virtual power supply line and a normal power supply line in response to activation of a switch control signal. The power supply voltage to a first circuit block connected to the virtual power supply line is suspended during the low power mode. A second switch of a floating prevention circuit connects a node between output of the first circuit block and input of a second circuit block to a first voltage line in response to inactivation of the switch control signal during the low power mode. This prevents the input of the second circuit block from floating even without the power supply voltage supplied to the first circuit block, and therefore prevents feedthrough current from flowing through the second circuit block, which enables reduction in power consumption during the low power mode.

Abstract: Aspects of the invention can prevent delay in output timing of inverted data for each of ferroelectric capacitors, there can be provided NMOSs that can electrically connect upper electrodes of the ferroelectric capacitor with a plate line and electrically connect lower electrodes of the ferroelectric capacitor with bit lines. Further there can be provided NMOSs that can electrically connect the lower electrodes of the ferroelectric capacitor with the plate line, and electrically connect the upper electrodes of the ferroelectric capacitor with bit lines.

Abstract: Ferroelectric memory includes a hollow formed in a first insulation film. A lower electrode is formed in this hollow by sol-gel method including an application process due to a spin coat method. In this application process, a precursor solution is dripped on a surface of the first insulation film and splashed away due to centrifugal force. Due to this, a first conductive film to being formed has an increased film thickness at portion of the hollow where the precursor solution is ready to correct, or portion to be formed into a lower electrode, and a decreased film thickness at portion other than the hollow. Accordingly, it is satisfactory to etch only the hollow portion when forming a lower electrode by dry-etching the first conductive film.

Abstract: Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states may be written to and read from the ferroelectric memory device which are associated with a single polarization direction, thereby allowing for a single cell to contain more than one bit of data.

Abstract: A ferroelectric memory device capable of structurally reducing data deterioration. In this ferroelectric memory device, bitlines are hierarchized, and sub-bitlines subordinate to the bitlines through sub-bitline select switches are provided in each of a plurality of block regions. The block regions are sequentially selected along an increment direction, and wordlines in each block are sequentially selected along the increment direction from the lowest wordline to the highest wordline. The number “n” of wordlines arranged in each block region is set equal to or less than a predetermined limit number about relaxation.

Abstract: A solid state memory device is fabricated by forming a level of the device; identifying defective areas in the level; and programming address logic of the level to avoid the defective areas in the level.

Abstract: A test circuit is integrated in a ferroelectric memory component in order to make analog measurements of bit line signals of ferroelectric memory cells. The test circuit, when in a test mode, reads out analog signal values for the respective memory content of the cells and feds the analog signal values to a downstream evaluation device. The test circuit is integrated as an analog circuit in the ferroelectric memory component and, in the test mode with non-activated or disconnected sense amplifiers, is configured to output analog bit line signals from the memory component to a point outside the memory component.

Abstract: In a ferroelectric data processing device for processing and/or storage of data with passive or electrical addressing a data-carrying medium is used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched between these and is provided as a continuous layer in or adjacent toelectrode structures in the form of a matrix. A logic element (4) is formed at the intersection between an x electrode (2) and a y electrode (3) of the electrode matrix. The logic element (4) is addressed by applying to the electrodes (2, 3) a voltage greater than the coercivity field of the ferroelectric material.

Abstract: A reverse bias voltage in combination with selective illumination can selectively write data into optical memory. The writing process can be completed quickly since parallel writing of data may be performed. The writing process generates an avalanche current that is used to change an element. The change can be destruction of the element or may be the alteration of property such as conductance or work function.

Abstract: A ferroelectric thin film coated substrate is obtained by a producing method of forming a crystalline thin film on a substrate by means of a MOCVD method at a substrate temperature at which crystal grows and of forming a ferroelectric thin film on the crystalline thin film by means of the MOCVD method at a film forming temperature, which is lower than the film forming temperature of the crystalline thin film. This producing method makes it possible to produce a ferroelectric thin film, where a surface of the thin film is dense and even, leakage current properties are excellent and sufficiently large remanent spontaneous polarization is shown, at a lower temperature.

Abstract: A manganese oxide material that can be used as a switching device or as a memory device or the like is formed of Mn-based oxide material. The Mn-based oxide material exhibits insulator-to-metal transitions induced by irradiating the material with laser light.

Abstract: A photosensitive member which has an electrode provided on the front side and a photoconductive layer stacked on the electrode, the photosensitive member being disposed face-to-face with an electrostatic information recording medium that includes a charge retaining layer having an electrode provided on the rear side, either in or out of contact with each other, to carry out exposure with a voltage being applied between the two electrodes, thereby forming an electrostatic charge pattern on the electrostatic information recording medium in accordance with an exposure light pattern. The layer arrangements of the photosensitive member and the photoconductive layer as well as the method of forming the photoconductive layer are improved so that electrostatic information can be recorded on the electrostatic information recording medium with high sensitivity and it is also possible to improve the contrast ratio of the information charge at the exposed region to that at the unexposed region.

Abstract: A digital memory element having three miniaturized electron tubes, which is faster and smaller by at least one further order of magnitude than known digital memory elements, can be produced through conventional and additive lithography. The digital memory element is a small memory capacitor linked to the anode of a write-in tube, to the cathode of an erase tube, and to a deflection element of a read-out tube which deflects an electron beam, in dependence upon the charge state, to one of two detectors.

Abstract: The invention relates to a read-write optical memory comprising a plurality of juxtaposed memory cells (11), each receiving a respective light beam (3). Each memory cell contains a storage medium (10), which includes a storage element (23) having stable optical states. The storage element (23) is divided into a number of memory points, and the optical state in a given memory point can be both changed and read by means of a light beam (3) directed towards the memory point. The memory can be implemented entirely without any movable mechanical parts and has a very short read-write time and an exceptionally high storage capacity. Parallel writing and reading of multibit words is possible.

Abstract: A multilayer structure has an a nonlinear optical film epitaxially grown on an underlying buffer layer of substantially lower refractive index. The buffer layer itself is epitaxially grown on a single crystal substrate with an intermediate epitaxial electrode.

Abstract: A ferroelectric thin film element 1 constructed by forming a MgO thin film 3 oriented in the direction (100), a lower electrode 4 composed of an alloy thin film of a Ni--Cr--Al system oriented in the direction (100), a ferroelectric thin film 5 composed of a PbTiO.sub.3 thin film oriented in the direction (111), and an upper electrode 6 in this order on a substrate composed of (100) silicon 2.

Abstract: Methods and apparatii are described for information storage in photoconductive film of single layer composition by irradiation of memory elements simultaneously with application of an electric field. Information is stored as trapped charge accumulations in the film when the irradiation is removed, but trapped charge can be released by subsequent irradiation. Repeated information storage, followed by erasure, returns the films to their original state without degradation.

Abstract: Methods and apparatii are described for information storage in photoconductive film of single layer composition by irradiation of memory elements simultaneously with application of an electric field. Information is stored as trapped charge accumulations in the film when the irradiation is removed, but trapped charge can be released by subsequent irradiation. Repeated information storage, followed by erasure, returns the films to their original state without degradation.

Abstract: In a semiconductor memory array, each cell includes a semiconductor switching element and a capacitor with a ferroelectric material layer. The ferroelectric material layer is sandwiched between opposing electrodes and exhibits a polarization varied in response to a voltage applied across the electrodes in such a manner that the direction of polarization is reversed if the voltage reaches a polarization reversal voltage. First electrodes of the capacitor elements are constituted by portions of semiconductor regions of the associated switching elements, while the second electrodes of the capacitor elements of the cells are constituted by a single common conductor layer. A first conductor is connected in common with the second main semiconductor regions of the switching elements of those cells which are on one column. A second conductor is connected in common with control electrodes of the switching elements of those cells which are on one row.

Abstract: A ferroelectric space charge capacitor memory device includes a pair of spaced first and second electrodes; a ferroelectric dielectric disposed between the electrodes; a coercive voltage supply for applying a coercive voltage to the dielectric to write the dielectric into one of two polarization states and to establish in each polarization state in the dielectric a space charge region proximate each electrode having a charge opposite to that of the electrode with a neutral region between the space charge regions, the relative sizes of the neutral and space charge regions defining the capacitance of the dielectric, the neutral region having an internal polarization field opposite to that represented by the space charge regions; a bias voltage supply for applying to the dielectric a bias voltage less than the coercive voltage at a rate lower than the rate of space charge formation to define a capacitance level representative of one of the polarization states; a pulse generator for introducing to the dielectric

Abstract: An improved read/write optical disk is disclosed which is capable of being rewritten more than 10.sup.6 times. The disk utilizes a storage medium in which data is stored by causing a localized region of the storage medium to assume one of two states. The two states can be converted from one to another by the application of electric fields to the localized region of the storage medium. The localized region in question is selected by illuminating an area on an addressing layer directly above the region in question with light. The preferred embodiment utilizes a lead lanthanum zirconate titanate material for the storage medium.

Abstract: A ferroelectric memory includes a ferroelectric thin film having first and second surfaces opposite to each other, a first electrode assembly having a plurality of stripe electrodes arranged in parallel on the first surface side of the ferroelectric thin film, a second electrode assembly having a plurality of stripe electrodes arranged in parallel on the second surface side of the ferroelectric thin film to intersect the stripe electrodes of said first electrode assembly, first and second common electrodes arranged separately from the end portions of the respective first and second electrode assemblies to extend in respective directions in which the stripe electrodes of the first and second electrode assemblies are arranged, and selecting sections for respectively connecting the first and second electrode assemblies to the first and second common electrodes and selectively activating at least one of the stripe electrodes of each of the first and second electrode assemblies.

Abstract: An improved read/write optical disk is disclosed which is capable of being rewritten more than 10.sup.6 times. The disk utilizes a storage medium in which data is stored as different polarization states in the same phase of the material. The preferred embodiment utilizes a lead lanthanum zirconate titanate material for the storage medium. The state of polarization of the material at the location of a specified data bit is changed by applying a voltage to the bit location in question. The location is specified by illuminating the surface of the disk with light in the infra-red.

Abstract: The invention comprises a data storage device in which ferroelectric photorefractive cells 12 susceptible to polarization for the storage of digital information are positioned on a carrier medium, preferably a disk 10, which supports the cells and allows access to them by optical beams 14, 16 and electric fields 21. A non-contacting data writing means comprising dual electrodes 20, 22 is used to change the polarity of the cells. A non-contacting data reading means comprising lasers 14, 16 and detectors 30, 34 is used to observe photorefractive effects so that the polarity of such cells 12 can be determined. The polarity of the ferroelectric photorefractive cells is coded for the storage of digital information.

Abstract: The information recorded in the data carrier in the form of a locally variable electric polarization is scanned and selected by means of an electron beam. For this purpose, the secondary electrons produced on the surface of the data carrier are used. The data carrier is simultaneously either periodically heated by radiating electromagnetic waves or charged with ultrasonics. Potential fluctuations of equal frequency thereby arise on the surface of the data carrier dependent on local polarization, which fluctuations result in a modulation of the secondary electrons. The secondary electron flow thus receives information via the polarization conditions stored in the data carrier. To recover this information, the secondary electron flow is frequency-selectively amplified and electronically evaluated according to amount and/or phase. A polyvinylidene flouride film (PVDF) is preferably used as data carrier.

Abstract: The photosensitivity of lead lanthanum zirconate titanate (PLZT) ceramic material used in high resolution, high contrast, and non-volatile photoferroelectric image storage and display devices is enhanced significantly by positive ion implantation of the PLZT near its surface. Implanted ions include H.sup.+, He.sup.+, Ne.sup.+, Ar.sup.+, as well as chemically reactive ions from Fe, Cr, and Al. The positive ion implantation advantageously serves to shift the absorption characteristics of the PLZT material from near-UV light to visible light. As a result, photosensitivity enhancement is such that the positive ion implanted PLZT plate is sensitive even to sunlight and conventional room lighting, such as fluorescent and incandescent light sources. The method disclosed includes exposing the PLZT plate to the positive ions at sufficient density, from 1.times.10.sup.12 to 1.times.10.sup.17, and with sufficient energy, from 100 to 500 KeV, to provide photosensitivity enhancement.

Abstract: A semiconductor memory device of an MOS static type comprising a current switching mechanism, such as depletion type transistors, arranged between a power supply and bit lines. The current switching mechanism is controlled by column selection signals and supplied a larger current to the bit lines during the selected mode than the non-selected mode.

Abstract: A three dimensional memory which is comprised of a plurality of stacked memory planes, each of which includes at least a continuous transparent photovoltaic-ferroelectric layer sandwiched between two continuous plane transparent electrodes. In one embodiment, the memory planes are comprised of only the photovoltaic-ferroelectric layer sandwiched between the two electrodes, and in another embodiment the ferroelectric layer and a continuous transparent photoconductive layer are sandwiched between the two electrodes.

Abstract: A three dimensional memory having an increased storage capacity. The memory block has a matrix of cylindrical cavities, each of which has a fiber optic light guide means disposed therein. Each light guide means is comprised of a cylindrical core having a first index of refraction and a cladding surrounding the core having a second, smaller index of refraction; a plurality of spaced deformations are formed at the core-cladding interface for allowing light to leak out of the guide laterally.

Abstract: A flat PLZT plate is utilized to form erasable images thereon which images may be projected or viewed directly. One embodiment includes electrically conductive islands on one side of the PLZT plate which are surrounded by and electrically isolated from an electrically conductive grid pattern. The portion of the PLZT plate located between an island and the surrounding portion of the grid pattern constitutes a pixel or image forming element. By grounding the grid pattern and applying an electrical charge to selected ones of the islands, an image can be formed on the PLZT plate which can be viewed directly or projected by means of polarized light. In order to form the erasable images on the PLZT plate by optical means, the grid pattern and islands are coated with a layer of photoconductive material upon which a layer of a transparent conductor is coated.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.