Abstract: Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block.

Abstract: A ferrite module matrix driver circuit comprises a controller, a charging circuit, a plurality of ferrite modules arranged in the form of a matrix, a plurality of first switches driven by the controller, a plurality of second switches driven by the controller, and one or more comparators coupled to the charging circuit and the controller. Each switch in the first plurality of switches connects a respective column of said plurality of ferrite modules to the charging circuit. Each switch in the second plurality of switches connects a respective row of said plurality of ferrite modules to ground. And, after a specific voltage has been reached by the charging circuit, one of the comparators signals to the controller, which in turn selects a specific ferrite module to be polarized by driving one of the plurality of first switches and one of the plurality of second switches.

Abstract: Various examples are provided for low ohmic loss radial superlattice conductors. In one example, among others, a conductor includes a plurality of radially distributed layers that include a non-permalloy core, a permalloy layer disposed on and encircling the non-permalloy core, and a non-permalloy layer disposed on and encircling the permalloy layer. The non-permalloy core and non-permalloy layer can include the same or different materials such as, e.g., aluminum, copper, silver, and gold. In some implementations, the non-permalloy core includes a void containing air or a non-conductive material such as, e.g., a polymer. The permalloy layer can include materials such as, e.g., NiFe, FeCo, NiFeCo, or NiFeMo. In another example, a via connector includes the plurality of radially distributed layers including the permalloy layer and the non-permalloy layer disposed on and encircling the permalloy layer. The via connector can extend through glass, silicon, organic, or other types of substrates.

Abstract: A semiconductor device capable of assessing and rewriting data at a desired timing is provided. A semiconductor device includes a register circuit, a bit line, and a data line. The register circuit includes a flip-flop circuit, a selection circuit, and a nonvolatile memory circuit electrically connected to the flip-flop circuit through the selection circuit. The data line is electrically connected to the flip-flop circuit. The bit line is electrically connected to the nonvolatile memory circuit through the selection circuit. The selection circuit selectively stores data based on a potential of the data line or a potential of the bit line in the nonvolatile memory circuit.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Abstract: A ferroelectric memory of an embodiment of the present invention includes m platelines arranged in a first interconnect layer (m is a positive integer), n bitlines arranged in a second interconnect layer (n is a positive integer), and m×n memory cells arranged at m×n intersection points of the m platelines and the n bitlines, each of the m×n memory cells including a ferroelectric capacitor and a zener diode connected in series between any one of the m platelines and any one of the n bitlines.

Abstract: A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

Abstract: The present invention relates to a method and related structure for reducing ground bounce during write operations from a microprocessor. More specifically, the address and data signal lines of the microprocessor are divided into three transmission groups. The first transmission group transitions its data onto the bus lines with no delay. The second transmission group transitions its signal lines onto the bus with a half clock period delay of the core frequency clock. Finally, the third transmission group transitions its signal lines onto the bus with a full clock period delay of the core frequency clock. In this way, parallel writes by the microprocessor have their current sinking associated with that write distributed over an entire clock period of the core frequency clock such that ground bounce associated with that current sinking is reduced.

Abstract: A threshold magnetic switch is described, with adjustable threshold level for varying applications, or for purposes of matching sensitivities of several switches in utilizing apparatus.