Abstract: A memory device includes a pass transistor circuit included in a first wafer, and configured to transfer an operating voltage to row lines of a memory cell array; and a discharge transistor circuit included in a second wafer that overlaps with the first wafer in a vertical direction, and configured to transfer a discharge voltage to at least one of the row lines.

Abstract: SMA actuators and related methods are described. One embodiment of an actuator includes a base; a plurality of buckle arms; and at least a first shape memory alloy wire coupled with a pair of buckle arms of the plurality of buckle arms. Another embodiment of an actuator includes a base and at least one bimorph actuator including a shape memory alloy material. The bimorph actuator attached to the base.

Abstract: Disclosed is a nanofilm, a thin film transistor and manufacture methods thereof. The nanofilm of the present disclosure comprises a plurality of regions distributed in a film plane dimension, wherein each of the regions is composed of one kind of nanomaterial, and nanomaterials of adjacent regions are different from each other and contact with each other to form a heterojunction or a Schottky junction.

Abstract: A method for manufacturing a magnetic memory element structure using a Ru hard mask and a post pillar thermal annealing process. A Ru hard mask is formed over a plurality of memory element layers and an ion milling is performed to transfer the image of the Ru hard mask onto the underlying memory element layers. A high-angle ion milling an be performed to remove any redeposited material from the sides of the memory element layers, and a non-magnetic, dielectric material can be deposited. A thermal annealing process can then be performed to repair any damage caused by the previously performed ion milling processes.

Abstract: A method for manufacturing a magnetic memory element array that includes the use of a Ru hard mask layer and a diamond like carbon hard mask layer formed over the Ru hard mask layer. A plurality of magnetic memory element layers are deposited over a wafer and a Ru hard mask layer is deposited over the plurality of memory element layers. A layer of diamond like carbon is deposited over the Ru hard mask layer, and a photoresist mask is formed over the layer of diamond like carbon. A reactive ion etching is then performed to transfer the image of the photoresist mask onto the diamond like carbon mask, and an ion milling is performed to transfer the image of the patterned diamond like carbon mask onto the underlying Ru hard mask and memory element layers. The diamond like carbon mask can then be removed by reactive ion etching.

Abstract: A memory storage device is disclosed herein which having volatile memory cells and non-volatile memory cells. The memory storage device can be implemented within a portable electronic device. These portable electronic devices often load data from non-volatile memory cells into volatile memory cells, for example, upon powering up. Conventionally, portable electronic devices often include separate non-volatile memory storage devices and volatile memory storage devices which requires a significant amount of time to transfer data stored in non-volatile memory storage devices to the volatile memory storage devices. However, the memory storage device integrates the volatile memory cells and the non-volatile memory cells into a single integrated memory device.

Abstract: A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.

Abstract: A non-volatile memory device has a circuit branch associated to a bit line connected to a memory cell. When the memory cell is read, in a precharging step, the bit line is precharged. In a characteristic shift step, the memory cell is activated, and a current source is activated to supply a shift current to the first bit line and cause the bit line to charge or discharge on the basis of the datum stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to an input of a comparator stage that compares the voltage on the bit line with a reference voltage to supply an output signal indicating a datum stored in the memory cell.

Abstract: A memory signal phase difference calibration circuit includes: a clock generator providing clocks allowing a physical layer (PHY) circuit of DDR SDRAM to generate a data input/output signal (DQ) and a data strobe signal (DQS) for accessing a storage circuit; a calibration control circuit outputting a phase control signal according to an adjustment range to adjust the phase of a target signal (DQ or DQS), and outputting a calibration control signal; an access control circuit reading storage data representing predetermined data from the storage circuit according to the calibration control signal; a comparison circuit comparing the predetermined data with the storage data to output a result allowing the calibration control circuit to alter the adjustment range accordingly; and a phase controller outputting a clock control signal according to the phase control signal to set the phase of a target clock used for the PHY circuit generating the target signal.

Abstract: A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The method includes determining, by a current determining circuit, a cell current and a cell current change rate of at least one of the cells; determining, by a control circuit, whether the cell current change rate is outside of a cell current change rate predefined range; performing, by the control circuit, a predetermined action if the control circuit determination is positive; and storing, in a memory, the determined cell current at predetermined times, and to store the determined cell current change rate.

Abstract: To calibrate an electronic circuit, a calibration controller tests the electronic circuit with an initial separate read check allowing for a read delay and with an initial separate write check allowing for a write delay. The calibration controller, responsive to passing the initial read check and the initial write check, for each condition of a range of conditions, iteratively performs a write test with the write delay concurrent with a read test with the read delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay and adjusting the read delay for each iteration until one or more of a read edge and a write edge are detected.

Abstract: A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a current determining circuit configured to determine a cell current and a cell current change rate of at least one of the cells; and a control circuit configured to: determine whether the cell current change rate is outside of a cell current change rate predefined range; and perform a predetermined action if the control circuit determination is positive.

Abstract: A system includes a CPU, a serial interface, and an adaptive clock delay compensator. The adaptive clock delay compensator is configured to generate a clock signal at a first frequency, detect an edge on a data signal, and count the number of clock cycles of a counter clock to measure the delay between an edge of the clock signal and the detected edge on the data signal to produce a first delay value. The CPU is configured to convert the first delay value to a different clock domain at a second frequency to produce a converted delay value, and initiate a data transfer operation using the second frequency as a clock signal. The adaptive clock delay compensator is configured to generate a delayed clock signal at the second frequency to the serial interface that is delayed from the clock signal at the second frequency by the converted delay value.

Abstract: A deposition accuracy determination method, including: capturing an image of a thin film for inspection formed on a substrate by depositing a mask; and converting the image to a color profile to distinguish false measurement data.

Abstract: To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

Abstract: A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first transistor is a planar transistor, a source of the first transistor being connected with the voltage supply, and a gate of the first transistor receiving a control signal. The second transistor includes a gate formed in at least two planes. A source of the second transistor is connected with the voltage supply, a gate of the second transistor receives the control signal, and a drain of the second transistor is connected with a drain of the first transistor and forms an output of the voltage boosting circuit for generating a boosted supply voltage as a function of the control signal.

Abstract: A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.

Abstract: An electromechanical memory element includes a fixed body and a deformable element attached to the fixed body. An actuator causes a deformation of the deformable element from a first position (associated with a first logic state) to a second position (associated with a second logic state) where a mobile element makes contact with a fixed element. A programming circuit then causes a weld to be formed between the mobile element and the fixed element. The memory element is thus capable of associating the first and second positions with two different logic states. The weld may be selectively dissolved to return the deformable element back to the first position.

Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states.

Abstract: A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is converted by a D/A converter and stored in the memory cell and the stored data is read by converting a signal output from the memory cell into a multi-bit digital signal with an A/D converter and the multi-bit digital signal is output from the memory circuit, and a signal transmission path for a single-level cell mode in which a single-bit digital signal representing any of two states input to the memory circuit is directly stored in the memory cell and the signal stored in the memory cell is directly output from the memory cell.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.

Abstract: A quantum memory component including a quantum dot molecule having first and second quantum dots provided in respective first and second layers separated by a barrier layer; an exciton comprising an electron and hole bound state in said quantum dot molecule, the spin state of said exciton forming a qubit; first and second electrical contacts respectively provided below the first quantum dot and above the second quantum dot; a voltage source to apply an electric field across said quantum dot molecule; a controller to modulate the electric field across the quantum dot molecule, including an information acquiring circuit to acquire information concerning the relationship between fine structure splitting of the exciton and the applied electric field and a timing circuit to allow switching of the exciton from an indirect configuration to a direct configuration at predetermined times derived from the fine structure splitting.

Abstract: Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.

Abstract: An objective lens for an optical pickup device is characterized in that compatibility of three types of optical discs, which are a BD, a DVD, and a CD, may be realized by a common objective lens, and a flare can be created by providing an over-spherical aberration when a third optical disc is used from a size relationship between a pitch on a central region side and a pitch on an intermediate region side across a boundary and a relationship of a direction of a step in the base structures superimposed in a central region and an intermediate region of the objective lens.

Abstract: A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.

Abstract: A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer comprising a metal oxide positioned between the first electrode and the second electrode. The variable resistance layer includes: a first oxide layer having a resistivity ?x, on the first electrode; a second oxide layer having a resistivity ?y (?x<?y), on the first oxide layer; a third oxide layer having a resistivity ?z (?y<?z), on the second oxide layer; and a localized region that is positioned in the third oxide layer and the second oxide layer to be in contact with the second electrode and not to be in contact with the first oxide layer, and is, in resistivity, lower than the third oxide layer and different from the second oxide layer.

Abstract: To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.

Abstract: A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied.

Abstract: Integrated circuit memory devices include an array of static random access memory (SRAM) cells arranged as a plurality of columns of SRAM cells electrically coupled to corresponding plurality of pairs of bit lines and a plurality of rows of SRAM cells electrically coupled to a corresponding plurality of word lines. A word line driver and a column decoder are provided. The word line driver, which is electrically coupled to the plurality of word lines, is configured to drive a selected word line with a positive voltage and a plurality of unselected word lines with a negative voltage during an operation to write data into a selected one of the SRAM cells. The column decoder includes a plurality of pairs of selection switches therein, which are electrically coupled to corresponding ones of the plurality of pairs of bit lines.

Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m—1 or the like). Further, each cell includes selection transistors STr1—n—m and STr2—n—m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2—n—m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.

Abstract: The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

Abstract: Storing data in a non-volatile latch may include applying a bias voltage to a memristor pair in electrical communication with at least one logic gate and applying a gate voltage to a transmission gate to allow an input voltage to be applied to the at least one logic gate where the input voltage is greater than the bias voltage and the input voltage determines a resistance state of the memristor pair.

Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Abstract: A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.

Abstract: The present invention relates to non-volatile memory chips having graphene drums. In some embodiments, the non-volatile memory chips have one or more layers that each includes a plurality of graphene-drum memory chip cells.

Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.

Abstract: A stacked memory device for a configurable bandwidth memory interface includes a first number of contact pads arranged in a pattern on a first surface of the memory device and a second number of contact pads arranged in the same pattern on a second surface. Each of the second contact pads may be electrically coupled to a corresponding contact pad on the first surface using a via. When the memory device is oriented in a first orientation and stacked in vertical alignment and electrical connection upon a second memory device having the same pattern of contact pads, each data signal of the memory bus is coupled to a corresponding data signal of both the memory devices. When the memory device is oriented in a second orientation, a given data signal of the memory bus is coupled to the corresponding data signal of only one of the memory devices.

Abstract: A dynamic phase shifter and staticizer circuit and method includes a clock domino configured to receive a phase memory signal from a memory array and a clock signal and output the intermediate signal, and a staticizer configured to receive the intermediate signal from the clock domino and the clock signal and output a static memory signal. The static memory signal is shifted by one clock cycle from the phase memory signal. Setup and holding is done with respect to the clock edge, shifting the output of the clock domino, and the received phase memory signal can borrow into the next cycle when being sampled. The phase memory signal is converted from a half-cycle in length to the static memory signal that is a full-cycle in length.

Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

Abstract: In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.

Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.

Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.