Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled through a clock tree, and a feedback signal is generated that is indicative of the propagation delay of the internal clock signal through the clock tree. The feedback signal is applied to the synchronized mirror delay to allow the synchronized mirror delay to delay the internal clock signal by a delay interval that compensates for the propagation delay in the clock tree. A lock detector may be used to initially generate the internal clock signal directly from the external clock signal. A fine delay circuit that delays the internal clock signal in relatively fine increments may be used to couple the internal clock signal to the clock tree.

Abstract: A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled through a clock tree, and a feedback signal is generated that is indicative of the propagation delay of the internal clock signal through the clock tree. The feedback signal is applied to the synchronized mirror delay to allow the synchronized mirror delay to delay the internal clock signal by a delay interval that compensates for the propagation delay in the clock tree. A lock detector may be used to initially generate the internal clock signal directly from the external clock signal. A fine delay circuit that delays the internal clock signal in relatively fine increments may be used to couple the internal clock signal to the clock tree.

Abstract: A ferroelectric memory device according to the present invention includes memory cells. Each memory cell is constructed such that a lower electrode is formed on a silicon substrate, a ferroelectric capacitor having a hysteresis characteristic with at least two non-linear characteristic portions is formed on the lower electrode, and an upper electrode is formed on the ferroelectric capacitor. The memory cells are arranged in a matrix and are provided with a column switching controller and a row switching controller. These controllers are connected via a switching circuit to a write circuit, a read circuit and a detector. When a voltage lower than a coercive voltage is applied to the memory cells, the data storage states of the memory cells are discriminated on the basis of the difference in differential dielectric constants between "1" and "0", thus reading out the data in a non-destructive manner.

Abstract: An insulating layer is formed on a transistor having a source region/drain region and a gate electrode. Contact holes are formed in this insulating layer in association with the source region/drain region and the gate electrode. A memory element having a ferroelectric substance layer is provided in that contact hole which is associated with the source region/drain region. This memory element comprises a first electrode provided on the source region/drain region, a ferroelectric substance layer provided on the first electrode, and a second electrode provided on the ferroelectric substance layer. Providing this memory element in the contact hole which is associated with the source region/drain region can make cells flatter and permit metal wires to be surely formed in the contact holes.