Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Abstract: A magnetic memory includes a first magnetic layer, a second magnetic layer, a third magnetic layer, a first intermediate layer, a second intermediate layer, an insulator film, and an electrode. The third magnetic layer is provided between the first magnetic layer and the second magnetic layer in a first direction being perpendicular to the plane of both the first magnetic layer and the second magnetic layer. The insulator film is provided on the third magnetic layer in a second direction perpendicular to the first direction. The electrode is provided on the insulator film so that the insulator is sandwiched between the third magnetic layer and the electrode in the second direction. In addition, a positive voltage is applied to the electrode and a first current passes from the first magnetic layer to the second magnetic layer, thereby writing information to the second magnetic layer.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each of the cell transistors. Ferroelectric capacitors corresponding in number to the cell transistors, are provided above the local bit line, where each of the ferroelectric capacitors has an upper electrode and a lower electrode electrically connected to the other one of the source diffusion layer and drain diffusion layer of the corresponding one of the cell transistors. A plate line is provided above the upper electrodes and electrically connected to the upper electrodes. A reset transistor and a block selection transistor are provided on the surface of the semiconductor substrate.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A series connected TC unit type ferroelectric memory device is provided, in which a substantially constant read signal margin can be obtained regardless of the position of the selected word line. A memory cell MC includes parallel-connected ferroelectric capacitor C and cell transistor T. Cell blocks MCB0 and MCB1 each includes a plurality of series-connected memory cells MC are arranged between terminals N1 and N2 along a pair of bit lines BBL and BL. The terminals N1 are connected to the bit lines BBL and BL via block selecting transistors BST0 and BST1. The terminals N2 are connected to plate lines BPL and PL. A gate of each cell transistor is connected to a word line WL. A sense amplifier 2 is connected to the bit lines BBL and BL. When data is read, an offset voltage applying circuit 4 compensates for the imbalance in read signal margin caused by the difference in position of word line by applying to the bit line an offset voltage which differs depending on the position of the selected word line.

Abstract: A nonvolatile ferroelectric memory device is provided that has a plurality of cell arrays in a matrix and includes a plurality of pull-down sensing amplifiers between adjacent cell arrays arranged in a vertical direction that pull-down amplify a data in a corresponding cell array and a pull-up amplifier. The pull-up amplifier between the vertically adjacent cell arrays is shared by an upper and a lower cell arrays to selectively pull-up amplify a data in the upper cell array or data in the lower cell array. The nonvolatile ferroelectric memory device having the plurality of vertically arranged cell arrays efficiently reduces a layout and ensures a stability of amplification by dividing a structure of a sensing amplifier formed between cell arrays into the pull-down sensing amplifiers and the pull-up sensing amplifier, and subsequently making the pull-up sensing amplifier shared by the upper cell array and the lower cell array.

Abstract: A magnetic switching device, includes a first electrode, a second electrode, and a nanoparticle having a magnetic moment and being disposed between the first and second electrodes. At least one of the first electrode and the second electrode includes a magnetic material which has a net spin polarization in its conduction band for injecting, into the nanoparticle, an electrical current including a net spin polarization for overcoming the magnetic moment of the nanoparticle upon selection of a predetermined magnitude for the electrical current.