Abstract: A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.

Abstract: An apparatus for providing concurrent communications between multiple memory devices and a processor is disclosed. Each of the memory device includes a driver, a phase/cycle adjust sensing circuit, and a bus alignment communication logic. Each phase/cycle adjust sensing circuit detects an occurrence of a cycle adjustment from a corresponding driver within a memory device. If an occurrence of a cycle adjustment has been detected, the bus alignment communication logic communicates the occurrence of a cycle adjustment to the processor. The bus alignment communication logic also communicates the occurrence of a cycle adjustment to the bus alignment communication logic in the other memory devices. There are multiple receivers within the processor, and each of the receivers is designed to receive data from a respective driver in a memory device. Each of the receivers includes a cycle delay block.

Abstract: A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.