Ternary Patents (Class 365/168)
  • Patent number: 10892013
    Abstract: A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Shu-Ru Wang, Chun-Yen Tseng
  • Patent number: 10877664
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: December 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
  • Patent number: 10832769
    Abstract: Techniques are provided for sensing a signal associated with a memory cell capable of storing three or more logic states. To sense a state of the memory cell, a charge may be transferred between a digit line and a node coupled with a plurality of sense components using a charge transfer device. Once the charge is transferred, one or more of the plurality of sense components may sense the charge with one of a variety of sensing schemes. Based on the charge being transferred using the charge transfer device and each sense component sensing the charge, a logic state associated with the memory cell may be determined. The number of sensed states may be correlated to the number of sense amplifiers. The ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than one.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, John F. Schreck
  • Patent number: 10788994
    Abstract: A system, computer program product, and computer-executable method for managing flash devices within a data storage environment utilized by an application of one or more applications, wherein the application accesses the managed flash devices through a pool of flash storage provided by the data storage, the system, computer program product, and computer-executable method comprising receiving a data I/O from the application, analyzing the data I/O directed toward the pool of flash storage in relation to the flash devices, and managing the flash devices based on data I/Os directed toward the pool of flash storage by the application.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 29, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: John S. Harwood, Robert W. Beauchamp, Roy E. Clark, Dragan Savic
  • Patent number: 10705736
    Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: July 7, 2020
    Inventor: Jin-Ki Kim
  • Patent number: 10630588
    Abstract: Methods and systems for range matching. The system holds a definition of one or more ranges of Internet Protocol (IP) addresses. The definition may specify any desired number of ranges of any suitable size, and some ranges may overlap one another or be contained in one another. The definition may also specify certain returned values and/or relative priorities for the various ranges. In a pre-processing phase, a hash table that is subsequently queried with addresses to be range-matched. The hash table may be updated at run-time. During operation, the system receives addresses (e.g., extracts addresses from monitored communication traffic) and identifies by querying the hash table, for each address, whether the address falls within any of the ranges.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 21, 2020
    Assignee: VERINT SYSTEMS LTD.
    Inventor: Yitshak Yishay
  • Patent number: 10522222
    Abstract: A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 10497406
    Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Sean Feeley
  • Patent number: 10373684
    Abstract: A semiconductor device includes an N number of sub-blocks each of including a memory cell array, a setting register specifying number of entry data for pre-searching, of first to N-th entry data divided and correspond respectively to the sub-blocks, and a search data changing unit changing a data arrangement order for search data input based on a value of the register. A sub-block for pre-searching searches for entry data matching with data for pre-searching in accordance with the arrangement order changed by the changing unit, in response to an instruction, and outputs a search result representing matching or non-matching. A sub-block for post-searching searches for entry data matching with data for post-searching other than the data for pre-searching, of entry data stored in association with each row of the array, based on a search result of the sub-block for pre-searching, and outputs a search result representing matching or non-matching.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 6, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Daigo Hayashi
  • Patent number: 10255977
    Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 9, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Mai Shimizu, Koji Kato, Yoshihiko Kamata, Mario Sako
  • Patent number: 10083078
    Abstract: Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Wanmo Wong
  • Patent number: 9916889
    Abstract: An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell in the array may be a single-port or a multiport memory cell. Memory cells in the same column of the array are connected to shared bit lines, whereas memory cells in the same row of the array are connected to shared word lines. The memory cells in the same row may also be connected to a row control line. During normal operations, the row control line may provide a positive power supply voltage to each memory cell along that row. During write operations, the row control line may be driven to ground or tri-stated to help improve the write margin and the write performance of the selected memory cells. The aspect ratio of these memory cells may also be more square-like or balanced to help improve power delivery.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventor: Kenneth Duong
  • Patent number: 9892782
    Abstract: A digital-to-analog converter (DAC) and memory device includes an array of memory cells including resistive memory elements programmable between a high resistive and low resistive state. In implementations the array of memory cells is segmented into unary and binary coded sub-arrays. The device includes a binarizer configured to couple to the memory array to assign binary weights, or segmented unary and binary weights, to currents through a plurality of memory cells or voltages across a plurality of memory cells. The memory device further includes a summer to sum the weighted outputs of the binarizer. A current to voltage converter coupled with the summer generates an analog output voltage corresponding with digital data stored in a plurality of memory cells.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: February 13, 2018
    Assignee: Terra Prime Technologies, LLC
    Inventor: Peter K. Nagey
  • Patent number: 9881681
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Patent number: 9824757
    Abstract: The consumption current of a TCAM device is reduced. A semiconductor device includes multiple sub-arrays each including a TCAM cell array. Each sub-array searches the corresponding part of the input search data. Each sub-array outputs the search result indicative of a match for every entry without searching, when the corresponding first control signal is activated.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: November 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Watanabe, Futoshi Igaue
  • Patent number: 9762261
    Abstract: A ternary content addressable memory (TCAM) is disclosed. The TCAM includes a memory array, a data match module, and compare circuitry. The memory array stores a data entry for a data word and a corresponding duplicate data entry for the data word. The data match module compares the data entry to an input word to produce a first match output, and compares the duplicate data entry to the input word to produce a second match output. The compare circuitry compares the first match output and the second match output.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: September 12, 2017
    Assignee: eSilicon Corporation
    Inventors: Michael Anthony Zampaglione, Thomas Robert Wik
  • Patent number: 9679540
    Abstract: A method of writing image data to a pixel array includes decoding an address and activating, based on the decoded address, two or more row selection signals. The address may be a ternary address having at least one trit. The method further includes providing the two or more row selection signals to the pixel array to select two or more rows of the pixel array, the activation of which writes the image data to pixels in the two or more rows of the pixel array.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: June 13, 2017
    Assignee: KOPIN CORPORATION
    Inventors: Pin Anupongongarch, Frederick P. Herrmann
  • Patent number: 9613674
    Abstract: A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second n-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John K. DeBrosse
  • Patent number: 9595354
    Abstract: A system and method of refreshing a nonvolatile memory having memory cells. The method includes identifying one or more of the memory cells that do not satisfy a data retention test; remapping the one or more identified memory cells from original memory addresses to spare memory addresses; and refreshing the identified memory cells.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: March 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Karl Hofmann, Michael Goessel
  • Patent number: 9575862
    Abstract: A logic design may include control and datapath circuitry. The datapath circuitry may be implemented in a double modular redundancy arrangement that generates respective first and second data signals. The control circuitry may be implemented in a triple modular redundancy arrangement. Storage circuitry may be used to buffer the first and second data signals. Real-time error detection circuitry may perform real-time error detection operations on the first and second data signals. Background error checking circuitry may perform background error checking operations such as cyclic redundancy check calculations on configuration data. In response to an error detected by the real-time error detection circuitry, the circuitry may select between the buffered first and second data signals to produce the output data signal. The selection may be performed based on the background error checking operations and may be delayed relative to the real-time detection of the error.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: February 21, 2017
    Assignee: Altera Corporation
    Inventors: Michael David Hutton, Dalon L. Westergreen
  • Patent number: 9543954
    Abstract: A driver circuit with device variation compensation function and an operation method thereof are provided. The driver circuit includes a pull-up switch unit, an isolating switch and a pull-down switch unit. A first terminal of the pull-up switch unit is coupled to a first voltage. A second terminal of the pull-up switch unit is coupled to an output terminal of the driver circuit. A first terminal of the isolating switch is coupled to the second terminal of the pull-up switch unit. A first terminal of the pull-down switch unit is coupled to a second terminal of the isolating switch. A second terminal of the pull-down switch unit is coupled to a second voltage. The pull-down switch unit has a device variation compensation function.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: January 10, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Liang Wu, Ya-Hsiang Tai, Yung-Hui Yeh, Zong-Hua Cai
  • Patent number: 9480027
    Abstract: The specification and drawings present a new method, apparatus and software related product (e.g., a computer readable memory) for implementing power control for uplink orthogonal and non-orthogonal resources for an uplink channel, e.g. for PUCCH or PUCSH, when CoMP is utilized in a wireless network (e.g., LTE).
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: October 25, 2016
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Kari Juhani Hooli, Jari Olavi Lindholm, Kari Pekka Pajukoski, Esa Tapani Tiirola, Timo Erkki Lunttila
  • Patent number: 9449695
    Abstract: A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is configured to count a clock to generate a current time, program dummy data at predetermined memory cells among the plurality of memory cells at a power-off state, detect a charge loss of the predetermined memory cells when a power-on state occurs after the power-off state, and restore the current time based on the detected charge loss.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: September 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungryun Kim, Sangyong Yoon, Kiwhan Song
  • Patent number: 9450609
    Abstract: A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 20, 2016
    Assignee: Altera Corporation
    Inventors: Herman Henry Schmit, Michael David Hutton
  • Patent number: 9437752
    Abstract: A resonant inter-band tunnel diode (RITD) can be fabricated using semiconductor processing similar to that used for Complementary Metal-Oxide-Semiconductor (CMOS) device fabrication, such as can include using silicon. A memory cell (e.g., a random access memory (RAM) cell) can be fabricated to include one or more negative differential resistance device, such as tunneling diodes, such as to provide a single-bit or multi-bit cell. In an example, a “hybrid” memory cell can be fabricated, such as including one or more negative resistance devices, a MOS transistor structure, and a capacitor structure, such as including an integrated capacitor configuration similar to a generally-available dynamic RAM (DRAM) structure, but such as without requiring a refresh and offering a higher area efficiency.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: September 6, 2016
    Assignee: QuTel, Inc.
    Inventor: Paul Berger
  • Patent number: 9378795
    Abstract: A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second re-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John K. DeBrosse
  • Patent number: 9355739
    Abstract: A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: May 31, 2016
    Assignee: Globalfoundries Inc.
    Inventors: Pamela Castalino, Toshiaki Kirihata, Derek H. Leu
  • Patent number: 9357036
    Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 31, 2016
    Assignee: KANDOU LABS, S.A.
    Inventors: John Fox, Brian Holden, Peter Hunt, John D. Keay, Amin Shokrollahi, Richard Simpson, Anant Singh, Andrew Kevin John Stewart, Giuseppe Surace
  • Patent number: 9343131
    Abstract: A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second n-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John K. DeBrosse
  • Patent number: 9329797
    Abstract: A method and system are disclosed for improved block erase cycle life prediction and block management in a non-volatile memory. The method includes the storage device tracking information relating to a first erase cycle count at which the block erase time exceeded a predetermined threshold relative to a first erase cycle at which this occurred in other blocks. Blocks having a later relative erase cycle at which the erase time threshold is exceeded are assumed to have a greater erase cycle life than those that need to exceed the erase time threshold at an earlier erase cycle. This information is used to adjust wear leveling in the form of free block selection, garbage collection block selection and other block management processes. Alternatively or in combination, the predicted erase cycle life information is used to adjust program and/or erase parameters such as erase voltage and time.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: May 3, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Neil Richard Darragh, Eran Erez, Sergey Anatolievich Gorobets
  • Patent number: 9318189
    Abstract: A sense amplifier circuit includes first and second lines and first and second inverters. Each inverter includes an input terminal, an output terminal, and a power source terminal. A second signal line potential is supplied to the first inverter input terminal. The second inverter input terminal is connected to the first inverter input terminal. A first signal line potential is supplied to the second inverter input terminal. A first switch transistor is connected to the first inverter power source terminal and has a gate connected to the second signal line. A switch second transistor is connected to the second inverter power source terminal and has a gate connected to the first signal line.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takaaki Nakazato
  • Patent number: 9305640
    Abstract: Disclosed is a system and method for reading flash memory cells with dynamically adjusted probability values (e.g., log-likelihood ratios). In connection with reading bit values from flash memory cells, one or more predetermined first probability values are adjusted relative to one or more predetermined second probability values. The one or more predetermined first probability values are associated with reading one or more memory cells programmed to a first binary value, and the one or more predetermined second probability values are associated with reading one or more memory cells programmed to a second binary value. The plurality of bit values read from the plurality of non-volatile memory cells and the one or more adjusted first probability values are provided to a decoder for use in decoding the plurality of bit values.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: April 5, 2016
    Assignee: HGST Netherlands B.V.
    Inventor: Xinde Hu
  • Patent number: 9256548
    Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Donald Edward Steiss, Marvin Wayne Martinez, Jr., John H. W. Bettink, John C. Carney, Mark Warden Hervin
  • Patent number: 9230649
    Abstract: The 4T2R cell comprises a write transistor, a first variable resistive element, a first transistor, a second variable resistive element, a second transistor, and a charge control transistor. The first transistor is electrically coupled to the first variable resistive element in series, and the second transistor is electrically coupled to the second variable resistive element in series, for providing search paths. For operating in a search phase, a pulse voltage is applied across the gate electrode and the source electrode of the first transistor (or across the gate electrode and the source electrode of the second transistor) for determining whether the gate voltage of the charge control transistor changes larger than a match threshold during the period of the pulse. Different RC-delay of the variable resistive elements controlling the voltage change speed of the gate voltage of the charge control transistor determines the matching result.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: January 5, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Li-Yue Huang
  • Patent number: 9104550
    Abstract: A method for converting a measured physical level of a cell into a logical value, in an array of memory cells storing physical levels which diminish over time, the method may include: determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in the array; and reading the individual cell including reading a physical level in said cell and converting said physical level into a logical value using at least some of said thresholds, wherein said determining extent of deterioration comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and determining extent of deterioration by computing deterioration of said predefined physical levels.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: August 11, 2015
    Assignee: DENSBITS TECHNOLOGIES LTD.
    Inventors: Hanan Weingarten, Shmuel Levy, Michael Katz
  • Patent number: 9086993
    Abstract: A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: July 21, 2015
    Assignee: Apple Inc.
    Inventors: Dotan Sokolov, Naftali Sommer, Uri Perlmutter, Ofir Shalvi
  • Publication number: 20140204669
    Abstract: A method (and structure) of quantum computing. Two independent magnitudes of a three-state physical (quantum) system are set to simultaneously store two real, independent numbers as a qubit. The three-state physical (quantum) system has a first energy level, a second energy level, and a third energy level capable of being degenerate with respect to one another, thereby forming basis states for the qubit.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Applicant: International Business Machines Corporation
    Inventors: Waseem Ahmed Roshen, Sham Madhukar Vaidya
  • Patent number: 8767461
    Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: July 1, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 8553457
    Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 8, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventor: Jin-Ki Kim
  • Patent number: 8391064
    Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 5, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventor: Jin-Ki Kim
  • Patent number: 8355269
    Abstract: A memory bit cell suitable for use in semiconductor integrated circuits that utilizes pushed design rules and layout geometries optimized by a semiconductor foundry for standard memory bit cells and edge-cell structures that provides a different functionality from that provided by the foundry standard bit cell. This different functionality is achieved by interconnecting the elements of one or a plurality of standard foundry bit cells and edge cells to implement a different circuit with different operation from the original bit cells and edge cells. The positioning and interconnection of the standard bit cells and edge cells are implemented in a manner so as to maintain the same periodic geometric proximity effects to the maximum degree possible. A preferred embodiment of this invention is to interconnect two standard foundry six-transistor SRAM bit cells and two edge cells to create a Ternary Content Addressable Memory bit cell with mask and compare functionality in addition to bit storage functionality.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 15, 2013
    Assignee: eSilicon Corporation
    Inventor: Michael Anthony Zampaglione
  • Patent number: 8331142
    Abstract: An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 11, 2012
    Assignee: Technische Universitat Berlin
    Inventors: Dieter Bimberg, Martin Geller, Andreas Marent, Tobias Nowozin
  • Patent number: 8315080
    Abstract: Provided are a luminescent device and a method of manufacturing the same. The luminescent device includes a charge trapping layer having bistable conductance and negative differential resistance (NDR) characteristics, and an organic luminescent layer electrically connected to the charge trapping layer. The charge trapping layer comprise a nanocrystal layer intervened in an organic layer, and the nanocrystal layer comprises a plurality of nanocrystals.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: November 20, 2012
    Assignee: IUCF-HYU
    Inventors: Jea Gun Park, Gon Sub Lee, Su Hwan Lee, Dal Ho Kim, Sung Ho Seo, Woo Sik Nam, Hyun Min Seung, Jong Dae Lee, Dong Won Shin
  • Patent number: 8233302
    Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort
  • Patent number: 8120937
    Abstract: A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brian L. Ji, Chung H. Lam, Robert K. Montoye, Bipin Rajendran
  • Patent number: 8045377
    Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: October 25, 2011
    Assignee: MOSAID Technologies Incorporated
    Inventor: Jin-Ki Kim
  • Patent number: 7974149
    Abstract: An electronic system includes at least one reduced-complexity integrated circuit memory coupled to a memory controller. By reducing the complexity of each integrated circuit memory and concentrating the complexity within the memory controller, overall system costs may be greatly reduced and reliability improved.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: July 5, 2011
    Assignee: Ovonyx, Inc.
    Inventor: Tyler Lowrey
  • Patent number: 7940595
    Abstract: A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: May 10, 2011
    Assignee: Sidense Corp.
    Inventor: Wlodek Kurjanowicz
  • Patent number: 7924588
    Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Michael T. Fragano, Rahul K. Nadkarni, Reid A. Wistort
  • Patent number: 7924604
    Abstract: A stacked memory cell for use in a high-density static random access memory is provided that includes first and second pull-down transistors formed in a first layer, a pass transistor connected between a gate of the second pull-down transistor and a bit line and formed in the first layer and a first and second pull-up transistors formed in a second layer located above the first layer and connected with the first and second pull-down transistors respectively to form an inverter latch. With the construction of a stacked memory cell having a lone pass transistor, cell size is reduced compared to a conventional six-transistor cell, and driving performance of the pass transistor can be improved.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyang-Ja Yang, Uk-Rae Cho